Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	292759	1			T1	27		T2	1497		T3	11
all_values[1]	292759	1			T1	27		T2	1497		T3	11
all_values[2]	292759	1			T1	27		T2	1497		T3	11
all_values[3]	292759	1			T1	27		T2	1497		T3	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

581690

1

T1

44

T2

2978

T3

5

auto[1]

589346

1

T1

64

T2

3010

T3

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

687242

1

T1

57

T2

4382

T3

26

auto[1]

483794

1

T1

51

T2

1606

T3

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	85319	1			T1	7		T2	481		T11	35
all_values[0]	auto[0]	auto[1]	59829	1			T1	6		T2	281		T11	35
all_values[0]	auto[1]	auto[0]	87275	1			T1	7		T2	453		T3	8
all_values[0]	auto[1]	auto[1]	60336	1			T1	7		T2	282		T3	3
all_values[1]	auto[0]	auto[0]	84715	1			T1	3		T2	433		T3	2
all_values[1]	auto[0]	auto[1]	61021	1			T1	3		T2	334		T3	1
all_values[1]	auto[1]	auto[0]	86201	1			T1	11		T2	414		T3	4
all_values[1]	auto[1]	auto[1]	60822	1			T1	10		T2	316		T3	4
all_values[2]	auto[0]	auto[0]	85346	1			T1	8		T2	510		T3	1
all_values[2]	auto[0]	auto[1]	60254	1			T1	5		T2	183		T3	1
all_values[2]	auto[1]	auto[0]	86553	1			T1	7		T2	594		T3	5
all_values[2]	auto[1]	auto[1]	60606	1			T1	7		T2	210		T3	4
all_values[3]	auto[0]	auto[0]	85096	1			T1	6		T2	756		T11	31
all_values[3]	auto[0]	auto[1]	60110	1			T1	6		T11	30		T12	9
all_values[3]	auto[1]	auto[0]	86737	1			T1	8		T2	741		T3	6
all_values[3]	auto[1]	auto[1]	60816	1			T1	7		T3	5		T11	36