Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	292759	1			T1	27		T2	1497		T3	11
all_pins[1]	292759	1			T1	27		T2	1497		T3	11
all_pins[2]	292759	1			T1	27		T2	1497		T3	11
all_pins[3]	292759	1			T1	27		T2	1497		T3	11

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	928456	1			T1	77		T2	5180		T3	28
values[0x1]	242580	1			T1	31		T2	808		T3	16
transitions[0x0=>0x1]	160474	1			T1	17		T2	588		T3	5
transitions[0x1=>0x0]	160709	1			T1	17		T2	588		T3	6

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	232423	1			T1	20		T2	1215		T3	8
all_pins[0]	values[0x1]	60336	1			T1	7		T2	282		T3	3
all_pins[0]	transitions[0x0=>0x1]	59750	1			T1	7		T2	282		T3	2
all_pins[0]	transitions[0x1=>0x0]	60465	1			T1	7		T3	5		T11	36
all_pins[1]	values[0x0]	231937	1			T1	17		T2	1181		T3	7
all_pins[1]	values[0x1]	60822	1			T1	10		T2	316		T3	4
all_pins[1]	transitions[0x0=>0x1]	34034	1			T1	5		T2	192		T3	1
all_pins[1]	transitions[0x1=>0x0]	33548	1			T1	2		T2	158		T11	20
all_pins[2]	values[0x0]	232153	1			T1	20		T2	1287		T3	7
all_pins[2]	values[0x1]	60606	1			T1	7		T2	210		T3	4
all_pins[2]	transitions[0x0=>0x1]	33265	1			T1	1		T2	114		T3	1
all_pins[2]	transitions[0x1=>0x0]	33481	1			T1	4		T2	220		T3	1
all_pins[3]	values[0x0]	231943	1			T1	20		T2	1497		T3	6
all_pins[3]	values[0x1]	60816	1			T1	7		T3	5		T11	36
all_pins[3]	transitions[0x0=>0x1]	33425	1			T1	4		T3	1		T11	14
all_pins[3]	transitions[0x1=>0x0]	33215	1			T1	4		T2	210		T11	11