Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	299	1			T166	7		T167	7		T223	4
all_values[1]	299	1			T166	7		T167	7		T223	4
all_values[2]	299	1			T166	7		T167	7		T223	4
all_values[3]	299	1			T166	7		T167	7		T223	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

651

1

T166

11

T167

18

T223

3

auto[1]

545

1

T166

17

T167

10

T223

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

440

1

T166

8

T167

9

T223

13

auto[1]

756

1

T166

20

T167

19

T223

3

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

702

1

T166

13

T167

16

T223

13

auto[1]

494

1

T166

15

T167

12

T223

3

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

67

1

T166

1

T167

1

T222

1

all_values[0]

auto[0]

auto[0]

auto[1]

35

1

T166

1

T222

1

T341

2

all_values[0]

auto[0]

auto[1]

auto[0]

42

1

T167

4

T223

4

T222

1

all_values[0]

auto[0]

auto[1]

auto[1]

30

1

T166

1

T341

1

T342

1

all_values[0]

auto[1]

auto[0]

auto[1]

65

1

T166

1

T167

1

T222

3

all_values[0]

auto[1]

auto[1]

auto[1]

60

1

T166

3

T167

1

T222

1

all_values[1]

auto[0]

auto[0]

auto[0]

57

1

T167

2

T223

1

T342

1

all_values[1]

auto[0]

auto[0]

auto[1]

32

1

T167

1

T222

1

T244

1

all_values[1]

auto[0]

auto[1]

auto[0]

50

1

T223

2

T222

1

T341

1

all_values[1]

auto[0]

auto[1]

auto[1]

34

1

T166

2

T244

1

T341

2

all_values[1]

auto[1]

auto[0]

auto[1]

66

1

T166

3

T167

3

T223

1

all_values[1]

auto[1]

auto[1]

auto[1]

60

1

T166

2

T167

1

T222

2

all_values[2]

auto[0]

auto[0]

auto[0]

61

1

T166

1

T167

1

T222

1

all_values[2]

auto[0]

auto[0]

auto[1]

40

1

T167

3

T222

1

T244

1

all_values[2]

auto[0]

auto[1]

auto[0]

60

1

T166

3

T223

4

T222

1

all_values[2]

auto[0]

auto[1]

auto[1]

30

1

T167

1

T244

2

T341

1

all_values[2]

auto[1]

auto[0]

auto[1]

66

1

T166

2

T167

1

T222

2

all_values[2]

auto[1]

auto[1]

auto[1]

42

1

T166

1

T167

1

T222

2

all_values[3]

auto[0]

auto[0]

auto[0]

54

1

T167

1

T222

3

T244

1

all_values[3]

auto[0]

auto[0]

auto[1]

29

1

T166

1

T167

1

T244

1

all_values[3]

auto[0]

auto[1]

auto[0]

49

1

T166

3

T223

2

T222

2

all_values[3]

auto[0]

auto[1]

auto[1]

32

1

T167

1

T342

1

T343

1

all_values[3]

auto[1]

auto[0]

auto[1]

79

1

T166

1

T167

3

T223

1

all_values[3]

auto[1]

auto[1]

auto[1]

56

1

T166

2

T167

1

T223

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal