Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	86878	1			T4	690		T5	179		T18	574
accum_cnt_1000	190108	1			T2	842		T11	70		T4	603
accum_cnt_100	19910	1			T2	133		T11	58		T4	122
accum_cnt_50	48373	1			T1	9		T2	107		T11	47
accum_cnt_10	157835	1			T1	17		T2	2290		T3	11
accum_cnt_0	330732	1			T1	26		T2	1132		T3	29

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	217676	1			T1	13		T2	1126		T3	10
class_index[0x1]	217676	1			T1	13		T2	1126		T3	10
class_index[0x2]	217676	1			T1	13		T2	1126		T3	10
class_index[0x3]	217676	1			T1	13		T2	1126		T3	10

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	20374	1			T14	207		T64	495		T66	186
class_index[0x0]	accum_cnt_1000	46221	1			T11	23		T4	5		T7	651
class_index[0x0]	accum_cnt_100	4708	1			T11	22		T4	22		T5	3
class_index[0x0]	accum_cnt_50	10113	1			T11	16		T4	43		T5	39
class_index[0x0]	accum_cnt_10	41668	1			T1	13		T2	1124		T3	4
class_index[0x0]	accum_cnt_0	86677	1			T2	2		T3	6		T11	3
class_index[0x1]	accum_cnt_2000	21291	1			T4	690		T5	54		T18	161
class_index[0x1]	accum_cnt_1000	44440	1			T4	598		T5	755		T21	24
class_index[0x1]	accum_cnt_100	5130	1			T4	63		T5	29		T18	6
class_index[0x1]	accum_cnt_50	14376	1			T4	66		T5	136		T18	8
class_index[0x1]	accum_cnt_10	36892	1			T2	1124		T3	7		T11	5
class_index[0x1]	accum_cnt_0	84150	1			T1	13		T2	2		T3	3
class_index[0x2]	accum_cnt_2000	21595	1			T5	124		T18	413		T20	15
class_index[0x2]	accum_cnt_1000	51173	1			T2	842		T11	27		T5	175
class_index[0x2]	accum_cnt_100	4559	1			T2	133		T11	14		T5	69
class_index[0x2]	accum_cnt_50	10249	1			T2	107		T11	14		T5	119
class_index[0x2]	accum_cnt_10	39374	1			T2	42		T11	9		T13	23
class_index[0x2]	accum_cnt_0	81079	1			T1	13		T2	2		T3	10
class_index[0x3]	accum_cnt_2000	23618	1			T5	1		T19	219		T63	406
class_index[0x3]	accum_cnt_1000	48274	1			T11	20		T5	884		T21	2
class_index[0x3]	accum_cnt_100	5513	1			T11	22		T4	37		T5	61
class_index[0x3]	accum_cnt_50	13635	1			T1	9		T11	17		T12	18
class_index[0x3]	accum_cnt_10	39901	1			T1	4		T11	7		T12	9
class_index[0x3]	accum_cnt_0	78826	1			T2	1126		T3	10		T11	1