Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4709	1			T4	1709		T18	140		T20	43
alert[0x1]	2766	1			T4	35		T17	1		T20	137
alert[0x2]	6276	1			T5	2567		T15	2		T16	1
alert[0x3]	4808	1			T4	1126		T20	138		T91	1
alert[0x4]	3854	1			T4	8		T5	60		T64	1083
alert[0x5]	1931	1			T15	1		T64	80		T122	1
alert[0x6]	2165	1			T7	2		T20	104		T91	1
alert[0x7]	2649	1			T4	65		T18	167		T16	1
alert[0x8]	2702	1			T4	30		T5	156		T7	1
alert[0x9]	4981	1			T18	362		T20	350		T226	1
alert[0xa]	4357	1			T4	4		T5	3		T20	5
alert[0xb]	3727	1			T4	6		T64	1031		T75	1
alert[0xc]	1943	1			T4	24		T5	25		T20	45
alert[0xd]	7734	1			T18	16		T6	95		T20	43
alert[0xe]	2927	1			T20	86		T64	419		T225	3
alert[0xf]	2800	1			T18	128		T6	1		T91	1
alert[0x10]	3836	1			T4	110		T15	1		T18	57
alert[0x11]	2597	1			T5	3		T6	11		T20	39
alert[0x12]	3070	1			T4	137		T18	175		T71	571
alert[0x13]	2042	1			T13	3		T5	54		T18	394
alert[0x14]	2485	1			T18	142		T64	257		T228	2
alert[0x15]	1954	1			T4	30		T20	34		T64	97
alert[0x16]	4921	1			T16	1		T17	1		T73	1
alert[0x17]	5377	1			T4	148		T16	1		T20	16
alert[0x18]	10322	1			T4	537		T5	62		T91	1
alert[0x19]	4127	1			T4	1692		T16	1		T122	1
alert[0x1a]	1824	1			T4	40		T6	1		T20	25
alert[0x1b]	3635	1			T4	19		T5	20		T16	1
alert[0x1c]	2863	1			T5	22		T15	1		T64	1214
alert[0x1d]	4486	1			T4	2944		T18	22		T17	1
alert[0x1e]	3803	1			T4	37		T18	45		T51	72
alert[0x1f]	7684	1			T13	1		T5	1715		T18	108
alert[0x20]	3183	1			T4	367		T20	59		T226	1
alert[0x21]	7560	1			T4	48		T5	349		T16	1
alert[0x22]	6754	1			T4	114		T20	54		T73	1
alert[0x23]	11831	1			T13	1		T4	76		T6	2
alert[0x24]	1697	1			T18	159		T20	6		T64	46
alert[0x25]	3077	1			T18	63		T16	1		T20	33
alert[0x26]	1497	1			T4	46		T18	77		T6	4
alert[0x27]	3938	1			T4	238		T6	2		T20	36
alert[0x28]	1553	1			T2	1		T20	125		T91	1
alert[0x29]	1727	1			T20	3		T225	4		T71	98
alert[0x2a]	2734	1			T4	8		T18	14		T91	2
alert[0x2b]	2845	1			T15	1		T18	173		T16	1
alert[0x2c]	1926	1			T4	58		T5	32		T18	91
alert[0x2d]	1460	1			T4	163		T73	8		T122	1
alert[0x2e]	3786	1			T4	6		T18	4		T67	1
alert[0x2f]	7635	1			T15	1		T18	1301		T20	7
alert[0x30]	2891	1			T4	41		T17	1		T20	140
alert[0x31]	2226	1			T4	99		T5	110		T18	183
alert[0x32]	6425	1			T4	56		T5	69		T18	904
alert[0x33]	10574	1			T4	206		T17	2		T46	161
alert[0x34]	2870	1			T4	5		T18	13		T91	1
alert[0x35]	1180	1			T13	3		T16	1		T20	4
alert[0x36]	4365	1			T20	261		T91	1		T46	27
alert[0x37]	2535	1			T73	1		T46	6		T71	179
alert[0x38]	6321	1			T4	268		T18	224		T20	30
alert[0x39]	7798	1			T13	20		T4	195		T5	22
alert[0x3a]	2494	1			T18	140		T64	10		T69	1
alert[0x3b]	2425	1			T17	1		T20	28		T91	1
alert[0x3c]	3217	1			T5	1365		T17	2		T46	629
alert[0x3d]	3472	1			T4	457		T16	1		T91	1
alert[0x3e]	1610	1			T18	361		T17	1		T20	320
alert[0x3f]	7850	1			T4	4		T91	1		T64	41
alert[0x40]	1671	1			T13	6		T18	30		T91	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	57749	1			T4	8		T5	15		T7	3
class_i[0x1]	81449	1			T13	27		T5	38		T15	7
class_i[0x2]	83643	1			T2	1		T13	7		T4	2
class_i[0x3]	35641	1			T4	11146		T6	8		T16	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

257774

1

T13

34

T4

11156

T5

6634

alert_ping_fail

708

1

T2

1

T7

3

T15

7

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4698	1			T4	1709		T18	140		T20	43
alert_integrity_fail	alert[0x1]	2757	1			T4	35		T20	137		T230	4
alert_integrity_fail	alert[0x2]	6263	1			T5	2567		T225	22		T71	62
alert_integrity_fail	alert[0x3]	4798	1			T4	1126		T20	138		T64	975
alert_integrity_fail	alert[0x4]	3844	1			T4	8		T5	60		T64	1083
alert_integrity_fail	alert[0x5]	1917	1			T64	80		T46	30		T22	1
alert_integrity_fail	alert[0x6]	2151	1			T20	104		T64	203		T46	26
alert_integrity_fail	alert[0x7]	2639	1			T4	65		T18	167		T66	1
alert_integrity_fail	alert[0x8]	2686	1			T4	30		T5	156		T64	13
alert_integrity_fail	alert[0x9]	4971	1			T18	362		T20	350		T46	142
alert_integrity_fail	alert[0xa]	4349	1			T4	4		T5	3		T20	5
alert_integrity_fail	alert[0xb]	3722	1			T4	6		T64	1031		T75	1
alert_integrity_fail	alert[0xc]	1934	1			T4	24		T5	25		T20	45
alert_integrity_fail	alert[0xd]	7725	1			T18	16		T6	95		T20	43
alert_integrity_fail	alert[0xe]	2914	1			T20	86		T64	419		T225	3
alert_integrity_fail	alert[0xf]	2789	1			T18	128		T6	1		T51	22
alert_integrity_fail	alert[0x10]	3822	1			T4	110		T18	57		T69	10
alert_integrity_fail	alert[0x11]	2587	1			T5	3		T6	11		T20	39
alert_integrity_fail	alert[0x12]	3065	1			T4	137		T18	175		T71	571
alert_integrity_fail	alert[0x13]	2025	1			T13	3		T5	54		T18	394
alert_integrity_fail	alert[0x14]	2475	1			T18	142		T64	257		T46	321
alert_integrity_fail	alert[0x15]	1939	1			T4	30		T20	34		T64	97
alert_integrity_fail	alert[0x16]	4904	1			T73	1		T46	482		T230	1
alert_integrity_fail	alert[0x17]	5362	1			T4	148		T20	16		T64	40
alert_integrity_fail	alert[0x18]	10315	1			T4	537		T5	62		T64	26
alert_integrity_fail	alert[0x19]	4122	1			T4	1692		T71	1045		T260	2
alert_integrity_fail	alert[0x1a]	1809	1			T4	40		T6	1		T20	25
alert_integrity_fail	alert[0x1b]	3626	1			T4	19		T5	20		T20	19
alert_integrity_fail	alert[0x1c]	2854	1			T5	22		T64	1214		T66	1
alert_integrity_fail	alert[0x1d]	4469	1			T4	2944		T18	22		T46	68
alert_integrity_fail	alert[0x1e]	3796	1			T4	37		T18	45		T51	72
alert_integrity_fail	alert[0x1f]	7671	1			T13	1		T5	1715		T18	108
alert_integrity_fail	alert[0x20]	3173	1			T4	367		T20	59		T75	3
alert_integrity_fail	alert[0x21]	7543	1			T4	48		T5	349		T64	19
alert_integrity_fail	alert[0x22]	6746	1			T4	114		T20	54		T73	1
alert_integrity_fail	alert[0x23]	11821	1			T13	1		T4	76		T6	2
alert_integrity_fail	alert[0x24]	1695	1			T18	159		T20	6		T64	46
alert_integrity_fail	alert[0x25]	3071	1			T18	63		T20	33		T71	6
alert_integrity_fail	alert[0x26]	1485	1			T4	46		T18	77		T6	4
alert_integrity_fail	alert[0x27]	3927	1			T4	238		T6	2		T20	36
alert_integrity_fail	alert[0x28]	1538	1			T20	125		T66	1		T118	80
alert_integrity_fail	alert[0x29]	1718	1			T20	3		T225	4		T71	98
alert_integrity_fail	alert[0x2a]	2720	1			T4	8		T18	14		T64	34
alert_integrity_fail	alert[0x2b]	2835	1			T18	173		T20	9		T66	26
alert_integrity_fail	alert[0x2c]	1908	1			T4	58		T5	32		T18	91
alert_integrity_fail	alert[0x2d]	1448	1			T4	163		T73	8		T46	91
alert_integrity_fail	alert[0x2e]	3770	1			T4	6		T18	4		T46	323
alert_integrity_fail	alert[0x2f]	7618	1			T18	1301		T20	7		T64	434
alert_integrity_fail	alert[0x30]	2872	1			T4	41		T20	140		T64	508
alert_integrity_fail	alert[0x31]	2218	1			T4	99		T5	110		T18	183
alert_integrity_fail	alert[0x32]	6415	1			T4	56		T5	69		T18	904
alert_integrity_fail	alert[0x33]	10567	1			T4	206		T46	161		T51	24
alert_integrity_fail	alert[0x34]	2853	1			T4	5		T18	13		T64	16
alert_integrity_fail	alert[0x35]	1172	1			T13	3		T20	4		T66	1
alert_integrity_fail	alert[0x36]	4357	1			T20	261		T46	27		T225	7
alert_integrity_fail	alert[0x37]	2524	1			T73	1		T46	6		T71	179
alert_integrity_fail	alert[0x38]	6314	1			T4	268		T18	224		T20	30
alert_integrity_fail	alert[0x39]	7790	1			T13	20		T4	195		T5	22
alert_integrity_fail	alert[0x3a]	2486	1			T18	140		T64	10		T69	1
alert_integrity_fail	alert[0x3b]	2412	1			T20	28		T64	243		T225	4
alert_integrity_fail	alert[0x3c]	3207	1			T5	1365		T46	629		T225	7
alert_integrity_fail	alert[0x3d]	3460	1			T4	457		T66	1		T46	31
alert_integrity_fail	alert[0x3e]	1604	1			T18	361		T20	320		T66	2
alert_integrity_fail	alert[0x3f]	7845	1			T4	4		T64	41		T69	41
alert_integrity_fail	alert[0x40]	1664	1			T13	6		T18	30		T46	29
alert_ping_fail	alert[0x0]	11	1			T226	1		T302	1		T303	1
alert_ping_fail	alert[0x1]	9	1			T17	1		T91	1		T226	1
alert_ping_fail	alert[0x2]	13	1			T15	2		T16	1		T303	1
alert_ping_fail	alert[0x3]	10	1			T91	1		T226	1		T122	1
alert_ping_fail	alert[0x4]	10	1			T303	1		T304	1		T305	1
alert_ping_fail	alert[0x5]	14	1			T15	1		T122	1		T301	1
alert_ping_fail	alert[0x6]	14	1			T7	2		T91	1		T302	1
alert_ping_fail	alert[0x7]	10	1			T16	1		T17	2		T304	1
alert_ping_fail	alert[0x8]	16	1			T7	1		T16	1		T228	1
alert_ping_fail	alert[0x9]	10	1			T226	1		T122	1		T306	1
alert_ping_fail	alert[0xa]	8	1			T228	1		T307	1		T34	1
alert_ping_fail	alert[0xb]	5	1			T308	1		T309	1		T310	1
alert_ping_fail	alert[0xc]	9	1			T311	1		T312	1		T313	2
alert_ping_fail	alert[0xd]	9	1			T228	1		T122	1		T307	1
alert_ping_fail	alert[0xe]	13	1			T302	1		T309	1		T314	1
alert_ping_fail	alert[0xf]	11	1			T91	1		T228	2		T303	1
alert_ping_fail	alert[0x10]	14	1			T15	1		T122	1		T309	1
alert_ping_fail	alert[0x11]	10	1			T91	1		T302	1		T38	1
alert_ping_fail	alert[0x12]	5	1			T305	1		T315	1		T311	1
alert_ping_fail	alert[0x13]	17	1			T16	1		T122	1		T301	1
alert_ping_fail	alert[0x14]	10	1			T228	2		T229	1		T252	1
alert_ping_fail	alert[0x15]	15	1			T38	1		T316	2		T304	1
alert_ping_fail	alert[0x16]	17	1			T16	1		T17	1		T228	1
alert_ping_fail	alert[0x17]	15	1			T16	1		T226	1		T299	1
alert_ping_fail	alert[0x18]	7	1			T91	1		T312	1		T317	1
alert_ping_fail	alert[0x19]	5	1			T16	1		T122	1		T237	1
alert_ping_fail	alert[0x1a]	15	1			T91	2		T299	1		T307	2
alert_ping_fail	alert[0x1b]	9	1			T16	1		T91	1		T122	1
alert_ping_fail	alert[0x1c]	9	1			T15	1		T122	1		T318	1
alert_ping_fail	alert[0x1d]	17	1			T17	1		T307	1		T319	1
alert_ping_fail	alert[0x1e]	7	1			T302	1		T38	1		T312	2
alert_ping_fail	alert[0x1f]	13	1			T300	1		T301	1		T308	1
alert_ping_fail	alert[0x20]	10	1			T226	1		T302	1		T320	2
alert_ping_fail	alert[0x21]	17	1			T16	1		T17	2		T226	1
alert_ping_fail	alert[0x22]	8	1			T122	1		T252	1		T307	1
alert_ping_fail	alert[0x23]	10	1			T226	1		T302	1		T320	1
alert_ping_fail	alert[0x24]	2	1			T320	1		T314	1		-	-
alert_ping_fail	alert[0x25]	6	1			T16	1		T38	1		T237	1
alert_ping_fail	alert[0x26]	12	1			T91	1		T122	1		T308	1
alert_ping_fail	alert[0x27]	11	1			T226	1		T228	1		T122	1
alert_ping_fail	alert[0x28]	15	1			T2	1		T91	1		T226	1
alert_ping_fail	alert[0x29]	9	1			T314	1		T237	1		T321	1
alert_ping_fail	alert[0x2a]	14	1			T91	2		T38	1		T304	1
alert_ping_fail	alert[0x2b]	10	1			T15	1		T16	1		T17	1
alert_ping_fail	alert[0x2c]	18	1			T17	1		T91	1		T228	1
alert_ping_fail	alert[0x2d]	12	1			T122	1		T320	1		T304	1
alert_ping_fail	alert[0x2e]	16	1			T67	1		T122	1		T39	1
alert_ping_fail	alert[0x2f]	17	1			T15	1		T308	1		T34	1
alert_ping_fail	alert[0x30]	19	1			T17	1		T228	1		T308	1
alert_ping_fail	alert[0x31]	8	1			T309	1		T304	2		T322	1
alert_ping_fail	alert[0x32]	10	1			T122	1		T307	1		T320	2
alert_ping_fail	alert[0x33]	7	1			T17	2		T307	1		T320	1
alert_ping_fail	alert[0x34]	17	1			T91	1		T228	2		T122	1
alert_ping_fail	alert[0x35]	8	1			T16	1		T307	1		T308	1
alert_ping_fail	alert[0x36]	8	1			T91	1		T302	1		T38	1
alert_ping_fail	alert[0x37]	11	1			T304	1		T323	1		T313	1
alert_ping_fail	alert[0x38]	7	1			T91	1		T308	1		T38	1
alert_ping_fail	alert[0x39]	8	1			T228	1		T309	1		T312	1
alert_ping_fail	alert[0x3a]	8	1			T305	1		T324	1		T312	1
alert_ping_fail	alert[0x3b]	13	1			T17	1		T91	1		T122	1
alert_ping_fail	alert[0x3c]	10	1			T17	2		T308	1		T305	1
alert_ping_fail	alert[0x3d]	12	1			T16	1		T91	1		T122	1
alert_ping_fail	alert[0x3e]	6	1			T17	1		T307	1		T314	1
alert_ping_fail	alert[0x3f]	5	1			T91	1		T228	1		T237	1
alert_ping_fail	alert[0x40]	7	1			T91	1		T305	1		T306	3

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	57595	1			T4	8		T5	15		T18	13
alert_integrity_fail	class_i[0x1]	81274	1			T13	27		T5	38		T18	5472
alert_integrity_fail	class_i[0x2]	83434	1			T13	7		T4	2		T5	6581
alert_integrity_fail	class_i[0x3]	35471	1			T4	11146		T6	8		T20	17
alert_ping_fail	class_i[0x0]	154	1			T7	3		T16	1		T17	14
alert_ping_fail	class_i[0x1]	175	1			T15	7		T16	10		T17	1
alert_ping_fail	class_i[0x2]	209	1			T2	1		T16	1		T91	20
alert_ping_fail	class_i[0x3]	170	1			T16	1		T17	1		T226	10