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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.24 99.99 98.65 97.09 100.00 100.00 99.38 99.56


Total test records in report: 829
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T769 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.243141671 Aug 16 05:41:47 PM PDT 24 Aug 16 05:48:47 PM PDT 24 23817603609 ps
T770 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.170175267 Aug 16 05:41:17 PM PDT 24 Aug 16 05:41:19 PM PDT 24 21826511 ps
T771 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2896082522 Aug 16 05:41:19 PM PDT 24 Aug 16 05:46:17 PM PDT 24 8473101899 ps
T772 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.13875475 Aug 16 05:41:19 PM PDT 24 Aug 16 05:41:28 PM PDT 24 60504285 ps
T773 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.4048732626 Aug 16 05:41:14 PM PDT 24 Aug 16 05:41:49 PM PDT 24 525233044 ps
T146 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3930080351 Aug 16 05:41:49 PM PDT 24 Aug 16 05:45:55 PM PDT 24 2114935755 ps
T774 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1274563239 Aug 16 05:41:51 PM PDT 24 Aug 16 05:41:52 PM PDT 24 10058658 ps
T775 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2334063862 Aug 16 05:41:17 PM PDT 24 Aug 16 05:41:19 PM PDT 24 20241364 ps
T776 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2648278539 Aug 16 05:41:19 PM PDT 24 Aug 16 05:41:27 PM PDT 24 218105496 ps
T161 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1237183166 Aug 16 05:41:44 PM PDT 24 Aug 16 05:44:23 PM PDT 24 2385610436 ps
T777 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1794289235 Aug 16 05:41:34 PM PDT 24 Aug 16 05:41:36 PM PDT 24 7474813 ps
T778 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1529712114 Aug 16 05:41:55 PM PDT 24 Aug 16 05:42:11 PM PDT 24 453484028 ps
T779 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1317401751 Aug 16 05:41:41 PM PDT 24 Aug 16 05:41:52 PM PDT 24 158395023 ps
T780 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.738382572 Aug 16 05:41:32 PM PDT 24 Aug 16 05:42:07 PM PDT 24 2091834185 ps
T156 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3172613629 Aug 16 05:41:14 PM PDT 24 Aug 16 05:50:42 PM PDT 24 11521953787 ps
T781 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1664695651 Aug 16 05:41:21 PM PDT 24 Aug 16 05:41:29 PM PDT 24 103228032 ps
T782 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3025649880 Aug 16 05:41:52 PM PDT 24 Aug 16 05:41:53 PM PDT 24 12846743 ps
T170 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1814671129 Aug 16 05:41:45 PM PDT 24 Aug 16 05:41:47 PM PDT 24 298644973 ps
T783 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.4063469241 Aug 16 05:41:29 PM PDT 24 Aug 16 05:41:51 PM PDT 24 2695317074 ps
T784 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1162819461 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:16 PM PDT 24 6449251 ps
T785 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1495476687 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:25 PM PDT 24 445886151 ps
T786 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2109112688 Aug 16 05:41:32 PM PDT 24 Aug 16 05:42:45 PM PDT 24 596310601 ps
T787 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.304867321 Aug 16 05:41:39 PM PDT 24 Aug 16 05:41:44 PM PDT 24 34914913 ps
T788 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2007992995 Aug 16 05:41:10 PM PDT 24 Aug 16 05:41:15 PM PDT 24 33530666 ps
T789 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3552248291 Aug 16 05:41:26 PM PDT 24 Aug 16 05:41:38 PM PDT 24 368417592 ps
T790 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.447032821 Aug 16 05:41:41 PM PDT 24 Aug 16 05:41:49 PM PDT 24 104002559 ps
T791 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1990257565 Aug 16 05:41:39 PM PDT 24 Aug 16 05:45:44 PM PDT 24 1704606951 ps
T792 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1863791301 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:18 PM PDT 24 14739663 ps
T793 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1255815544 Aug 16 05:41:39 PM PDT 24 Aug 16 05:41:50 PM PDT 24 131826779 ps
T147 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4062834381 Aug 16 05:41:30 PM PDT 24 Aug 16 06:02:02 PM PDT 24 32636237934 ps
T794 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1118252153 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:27 PM PDT 24 150579018 ps
T795 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2307423579 Aug 16 05:41:19 PM PDT 24 Aug 16 05:41:37 PM PDT 24 957018418 ps
T246 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.665080107 Aug 16 05:41:59 PM PDT 24 Aug 16 05:42:37 PM PDT 24 632223592 ps
T132 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3664698303 Aug 16 05:41:29 PM PDT 24 Aug 16 05:58:21 PM PDT 24 49285792785 ps
T155 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.858006462 Aug 16 05:41:20 PM PDT 24 Aug 16 05:50:04 PM PDT 24 11888892873 ps
T796 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3896855617 Aug 16 05:41:55 PM PDT 24 Aug 16 05:42:13 PM PDT 24 257427744 ps
T797 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2084348138 Aug 16 05:41:20 PM PDT 24 Aug 16 05:41:22 PM PDT 24 9657306 ps
T798 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2179093277 Aug 16 05:41:40 PM PDT 24 Aug 16 05:41:58 PM PDT 24 955344035 ps
T157 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3328524737 Aug 16 05:41:47 PM PDT 24 Aug 16 05:44:04 PM PDT 24 5457238825 ps
T799 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2721091747 Aug 16 05:41:47 PM PDT 24 Aug 16 05:41:52 PM PDT 24 50945702 ps
T800 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.80436506 Aug 16 05:41:50 PM PDT 24 Aug 16 05:41:51 PM PDT 24 7469223 ps
T801 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3175991633 Aug 16 05:41:28 PM PDT 24 Aug 16 05:42:08 PM PDT 24 539125245 ps
T802 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3104668472 Aug 16 05:41:38 PM PDT 24 Aug 16 05:41:42 PM PDT 24 60249563 ps
T159 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3606820228 Aug 16 05:41:46 PM PDT 24 Aug 16 05:56:38 PM PDT 24 13003453090 ps
T803 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.989109524 Aug 16 05:41:14 PM PDT 24 Aug 16 05:42:00 PM PDT 24 706891062 ps
T804 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.357299043 Aug 16 05:41:34 PM PDT 24 Aug 16 05:41:43 PM PDT 24 259971012 ps
T172 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3775424040 Aug 16 05:41:17 PM PDT 24 Aug 16 05:42:02 PM PDT 24 1252813141 ps
T805 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.409892678 Aug 16 05:41:44 PM PDT 24 Aug 16 05:41:49 PM PDT 24 474340440 ps
T806 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1286167860 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:26 PM PDT 24 358286926 ps
T807 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.860235275 Aug 16 05:42:00 PM PDT 24 Aug 16 05:42:22 PM PDT 24 685338828 ps
T808 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1599165259 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:24 PM PDT 24 1817639940 ps
T809 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1396356036 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:58 PM PDT 24 2145033358 ps
T810 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.209893671 Aug 16 05:41:37 PM PDT 24 Aug 16 05:41:39 PM PDT 24 14763894 ps
T134 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.4235282747 Aug 16 05:41:18 PM PDT 24 Aug 16 05:52:03 PM PDT 24 60316907183 ps
T811 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3018228915 Aug 16 05:41:17 PM PDT 24 Aug 16 05:48:01 PM PDT 24 7752515016 ps
T812 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.603732064 Aug 16 05:41:14 PM PDT 24 Aug 16 05:41:27 PM PDT 24 104984584 ps
T813 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2774403236 Aug 16 05:41:32 PM PDT 24 Aug 16 05:42:17 PM PDT 24 729073503 ps
T158 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.59947066 Aug 16 05:41:35 PM PDT 24 Aug 16 05:46:53 PM PDT 24 4538579292 ps
T180 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3794478585 Aug 16 05:41:10 PM PDT 24 Aug 16 05:41:23 PM PDT 24 53730133 ps
T814 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1921232645 Aug 16 05:41:13 PM PDT 24 Aug 16 05:42:42 PM PDT 24 7048140812 ps
T169 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2980706823 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:19 PM PDT 24 845319247 ps
T168 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2332163951 Aug 16 05:41:27 PM PDT 24 Aug 16 05:41:30 PM PDT 24 24485263 ps
T345 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.914576265 Aug 16 05:42:03 PM PDT 24 Aug 16 05:47:11 PM PDT 24 4470799876 ps
T815 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.950726005 Aug 16 05:41:12 PM PDT 24 Aug 16 05:41:14 PM PDT 24 8012728 ps
T816 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1202741412 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:17 PM PDT 24 26425689 ps
T148 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2871758580 Aug 16 05:41:13 PM PDT 24 Aug 16 05:42:57 PM PDT 24 907733707 ps
T817 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1596377002 Aug 16 05:41:02 PM PDT 24 Aug 16 05:41:10 PM PDT 24 205965254 ps
T818 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3541793106 Aug 16 05:41:18 PM PDT 24 Aug 16 05:41:20 PM PDT 24 8466337 ps
T819 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.480233161 Aug 16 05:41:27 PM PDT 24 Aug 16 05:41:28 PM PDT 24 8540118 ps
T820 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.912282390 Aug 16 05:41:30 PM PDT 24 Aug 16 05:41:39 PM PDT 24 118986779 ps
T821 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3724300202 Aug 16 05:41:34 PM PDT 24 Aug 16 05:41:35 PM PDT 24 13193346 ps
T822 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.18168224 Aug 16 05:41:43 PM PDT 24 Aug 16 05:41:47 PM PDT 24 247000441 ps
T823 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3007346110 Aug 16 05:41:21 PM PDT 24 Aug 16 05:44:31 PM PDT 24 3876637893 ps
T824 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2765161804 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:47 PM PDT 24 449639550 ps
T825 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3016925745 Aug 16 05:41:37 PM PDT 24 Aug 16 05:46:54 PM PDT 24 8642284542 ps
T826 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2531544832 Aug 16 05:41:21 PM PDT 24 Aug 16 05:43:06 PM PDT 24 1084989783 ps
T827 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3156124759 Aug 16 05:41:29 PM PDT 24 Aug 16 05:41:34 PM PDT 24 270061871 ps
T828 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.765973600 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:17 PM PDT 24 15005463 ps
T829 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3524321928 Aug 16 05:41:43 PM PDT 24 Aug 16 05:41:54 PM PDT 24 62347646 ps

Test location /workspace/coverage/default/5.alert_handler_stress_all.3900366523
Short name T4
Test name
Test status
Simulation time 31478638463 ps
CPU time 1392.45 seconds
Started Aug 16 04:36:47 PM PDT 24
Finished Aug 16 05:00:00 PM PDT 24
Peak memory 298600 kb
Host smart-9b525b4f-0c1b-4866-be95-e7927fc1a8ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900366523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3900366523
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2299499451
Short name T6
Test name
Test status
Simulation time 17962730643 ps
CPU time 193.99 seconds
Started Aug 16 04:37:52 PM PDT 24
Finished Aug 16 04:41:07 PM PDT 24
Peak memory 266292 kb
Host smart-19187b70-5cef-4c4e-a983-c2a902b41423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299499451 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2299499451
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1933476839
Short name T8
Test name
Test status
Simulation time 2311326213 ps
CPU time 77.93 seconds
Started Aug 16 04:36:35 PM PDT 24
Finished Aug 16 04:37:53 PM PDT 24
Peak memory 276156 kb
Host smart-4fa3fa25-d9d5-4256-b1ff-93d4faa57a41
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1933476839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1933476839
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.691256529
Short name T18
Test name
Test status
Simulation time 113542811586 ps
CPU time 1841.45 seconds
Started Aug 16 04:37:41 PM PDT 24
Finished Aug 16 05:08:23 PM PDT 24
Peak memory 286420 kb
Host smart-272adf79-cdb3-47ce-9e54-160cdb96b30e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691256529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.691256529
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3703920796
Short name T129
Test name
Test status
Simulation time 68734864940 ps
CPU time 944.66 seconds
Started Aug 16 05:41:38 PM PDT 24
Finished Aug 16 05:57:23 PM PDT 24
Peak memory 265636 kb
Host smart-ef45a2e1-5171-4b96-a4d8-1f7011421e2f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703920796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3703920796
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3605517017
Short name T97
Test name
Test status
Simulation time 45074517442 ps
CPU time 393.44 seconds
Started Aug 16 04:37:26 PM PDT 24
Finished Aug 16 04:44:00 PM PDT 24
Peak memory 268068 kb
Host smart-de08212b-609d-4e1c-b945-97894035c9ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605517017 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3605517017
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1911896542
Short name T49
Test name
Test status
Simulation time 533001010191 ps
CPU time 3091.51 seconds
Started Aug 16 04:37:18 PM PDT 24
Finished Aug 16 05:28:50 PM PDT 24
Peak memory 289248 kb
Host smart-7dc2dee9-ff68-42bf-83a4-8a84a8b81644
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911896542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1911896542
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3313373519
Short name T128
Test name
Test status
Simulation time 4868875558 ps
CPU time 350.24 seconds
Started Aug 16 05:41:29 PM PDT 24
Finished Aug 16 05:47:19 PM PDT 24
Peak memory 265668 kb
Host smart-e74299fc-5645-46f9-a6b5-27336ef01fc4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3313373519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3313373519
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1316918658
Short name T27
Test name
Test status
Simulation time 3471439462 ps
CPU time 415.48 seconds
Started Aug 16 04:36:58 PM PDT 24
Finished Aug 16 04:43:53 PM PDT 24
Peak memory 270276 kb
Host smart-44321a34-1306-477a-b3ba-c580fe9048cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316918658 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1316918658
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1740994282
Short name T46
Test name
Test status
Simulation time 21870857363 ps
CPU time 1049.81 seconds
Started Aug 16 04:36:56 PM PDT 24
Finished Aug 16 04:54:26 PM PDT 24
Peak memory 288148 kb
Host smart-834b4012-0700-4dfd-9a59-b5fe71737728
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740994282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1740994282
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4117447123
Short name T127
Test name
Test status
Simulation time 4363948661 ps
CPU time 668.8 seconds
Started Aug 16 05:41:21 PM PDT 24
Finished Aug 16 05:52:30 PM PDT 24
Peak memory 265672 kb
Host smart-6d1afcfb-2544-4a2e-b7c7-d1895bd717be
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117447123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.4117447123
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3887211687
Short name T299
Test name
Test status
Simulation time 27581301992 ps
CPU time 1878.24 seconds
Started Aug 16 04:37:00 PM PDT 24
Finished Aug 16 05:08:18 PM PDT 24
Peak memory 272488 kb
Host smart-8a16deb1-1765-487e-95d4-50a81bf39c42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887211687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3887211687
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.726424404
Short name T24
Test name
Test status
Simulation time 19515875276 ps
CPU time 1416.18 seconds
Started Aug 16 04:36:52 PM PDT 24
Finished Aug 16 05:00:29 PM PDT 24
Peak memory 273216 kb
Host smart-437bcea5-71ae-4053-b22b-11860433a13d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726424404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.726424404
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1852475114
Short name T164
Test name
Test status
Simulation time 457632650 ps
CPU time 37.76 seconds
Started Aug 16 05:41:49 PM PDT 24
Finished Aug 16 05:42:27 PM PDT 24
Peak memory 246160 kb
Host smart-56d59c99-6cbe-4716-8400-eb14a2c138a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1852475114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1852475114
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2954975009
Short name T141
Test name
Test status
Simulation time 7325258468 ps
CPU time 288.72 seconds
Started Aug 16 05:41:37 PM PDT 24
Finished Aug 16 05:46:26 PM PDT 24
Peak memory 265668 kb
Host smart-58a0cf4e-881a-48da-8539-09c2333e89f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2954975009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2954975009
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.404910242
Short name T102
Test name
Test status
Simulation time 20346624889 ps
CPU time 613.15 seconds
Started Aug 16 04:37:16 PM PDT 24
Finished Aug 16 04:47:29 PM PDT 24
Peak memory 271192 kb
Host smart-e46ae739-9c20-4642-93e8-bb6ab3afad8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404910242 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.404910242
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.279832616
Short name T224
Test name
Test status
Simulation time 355030109 ps
CPU time 15.53 seconds
Started Aug 16 04:36:36 PM PDT 24
Finished Aug 16 04:36:51 PM PDT 24
Peak memory 248612 kb
Host smart-6a7fdaf6-bfdf-4cab-b9e0-05b970a43bdb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=279832616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.279832616
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2750998127
Short name T122
Test name
Test status
Simulation time 23903357824 ps
CPU time 514.28 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:45:30 PM PDT 24
Peak memory 248636 kb
Host smart-97d2b52a-56a0-4987-aaec-c1ae0f5445e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750998127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2750998127
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3339724075
Short name T7
Test name
Test status
Simulation time 29205688673 ps
CPU time 1832.93 seconds
Started Aug 16 04:36:57 PM PDT 24
Finished Aug 16 05:07:35 PM PDT 24
Peak memory 281864 kb
Host smart-48e6e74e-43d7-43d2-a0a3-fe19a6daf5c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339724075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3339724075
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.4603363
Short name T222
Test name
Test status
Simulation time 17101230 ps
CPU time 1.49 seconds
Started Aug 16 05:41:21 PM PDT 24
Finished Aug 16 05:41:23 PM PDT 24
Peak memory 237796 kb
Host smart-da188c73-7d86-47cc-9a14-ca83f49a2312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4603363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.4603363
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.940027857
Short name T153
Test name
Test status
Simulation time 51236465174 ps
CPU time 1062.28 seconds
Started Aug 16 05:41:50 PM PDT 24
Finished Aug 16 05:59:33 PM PDT 24
Peak memory 265616 kb
Host smart-e51ad1cd-78eb-4312-ac13-a13ef657fc0e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940027857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.940027857
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2888285068
Short name T330
Test name
Test status
Simulation time 170358212528 ps
CPU time 2411.56 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 05:17:13 PM PDT 24
Peak memory 288848 kb
Host smart-a8a30d80-07bc-4fb4-9b91-da3e7db27c32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888285068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2888285068
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3454391579
Short name T150
Test name
Test status
Simulation time 4981721477 ps
CPU time 207.67 seconds
Started Aug 16 05:41:38 PM PDT 24
Finished Aug 16 05:45:06 PM PDT 24
Peak memory 273744 kb
Host smart-e1896676-8ce3-4c0e-9016-eddcb83cd490
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3454391579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3454391579
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2942824325
Short name T34
Test name
Test status
Simulation time 94472713040 ps
CPU time 2748.89 seconds
Started Aug 16 04:37:09 PM PDT 24
Finished Aug 16 05:22:59 PM PDT 24
Peak memory 288948 kb
Host smart-478e7e3f-b3e7-49aa-8052-ba6f6d59ca73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942824325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2942824325
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3196066352
Short name T5
Test name
Test status
Simulation time 13101338217 ps
CPU time 1112.51 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 04:55:33 PM PDT 24
Peak memory 289708 kb
Host smart-a893f8be-8b98-401a-8388-af670bd036c7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196066352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3196066352
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2761593926
Short name T237
Test name
Test status
Simulation time 9454571775 ps
CPU time 403.87 seconds
Started Aug 16 04:37:15 PM PDT 24
Finished Aug 16 04:44:00 PM PDT 24
Peak memory 256660 kb
Host smart-25137f23-66ba-4922-9ba9-c2045a951cc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761593926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2761593926
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1872939374
Short name T302
Test name
Test status
Simulation time 5720407051 ps
CPU time 244.72 seconds
Started Aug 16 04:36:58 PM PDT 24
Finished Aug 16 04:41:03 PM PDT 24
Peak memory 248760 kb
Host smart-3a04b189-e4b3-4e2c-b41d-ddf38f574b73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872939374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1872939374
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.84135618
Short name T131
Test name
Test status
Simulation time 18694546179 ps
CPU time 303.73 seconds
Started Aug 16 05:41:20 PM PDT 24
Finished Aug 16 05:46:24 PM PDT 24
Peak memory 273764 kb
Host smart-fe01651b-75c2-4096-99d3-a3fd4638e117
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=84135618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_error
s.84135618
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.4248482804
Short name T57
Test name
Test status
Simulation time 22399462346 ps
CPU time 429.26 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 04:44:14 PM PDT 24
Peak memory 268716 kb
Host smart-a50882ed-f885-4941-bf8e-74cd8dbf404f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248482804 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.4248482804
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1870422034
Short name T118
Test name
Test status
Simulation time 10630837440 ps
CPU time 1061.82 seconds
Started Aug 16 04:37:20 PM PDT 24
Finished Aug 16 04:55:02 PM PDT 24
Peak memory 289520 kb
Host smart-095f3f1d-f3c1-4de6-aeb5-993e0194caec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870422034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1870422034
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1981294195
Short name T257
Test name
Test status
Simulation time 99838505345 ps
CPU time 3497.87 seconds
Started Aug 16 04:36:51 PM PDT 24
Finished Aug 16 05:35:10 PM PDT 24
Peak memory 304580 kb
Host smart-e707841c-3cfc-4026-a2cd-672989b1333d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981294195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1981294195
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.803404623
Short name T316
Test name
Test status
Simulation time 124424713960 ps
CPU time 2740.84 seconds
Started Aug 16 04:37:11 PM PDT 24
Finished Aug 16 05:22:52 PM PDT 24
Peak memory 289684 kb
Host smart-7ea04b9a-03d2-4159-8517-754d03e68899
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803404623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.803404623
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3664698303
Short name T132
Test name
Test status
Simulation time 49285792785 ps
CPU time 1011.46 seconds
Started Aug 16 05:41:29 PM PDT 24
Finished Aug 16 05:58:21 PM PDT 24
Peak memory 273856 kb
Host smart-876d8c29-7ef5-498f-85ba-6f87b2c8ee22
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664698303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3664698303
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.702055973
Short name T171
Test name
Test status
Simulation time 1256288664 ps
CPU time 41.9 seconds
Started Aug 16 05:41:38 PM PDT 24
Finished Aug 16 05:42:20 PM PDT 24
Peak memory 240632 kb
Host smart-a6d635be-883a-49ec-bccf-06859b645fac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=702055973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.702055973
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3191298623
Short name T342
Test name
Test status
Simulation time 11507633 ps
CPU time 1.27 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 237760 kb
Host smart-d55ad4c6-bf04-47d3-a710-a3568c54e6ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3191298623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3191298623
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1072626851
Short name T305
Test name
Test status
Simulation time 10029357115 ps
CPU time 398.83 seconds
Started Aug 16 04:37:03 PM PDT 24
Finished Aug 16 04:43:42 PM PDT 24
Peak memory 248636 kb
Host smart-d9b6db2a-1a52-4c1c-b63b-92625699fac8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072626851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1072626851
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3082858729
Short name T276
Test name
Test status
Simulation time 220963309883 ps
CPU time 3544.53 seconds
Started Aug 16 04:37:18 PM PDT 24
Finished Aug 16 05:36:23 PM PDT 24
Peak memory 306060 kb
Host smart-495f5b25-1ad4-4e3e-b2aa-dedd77b0641f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082858729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3082858729
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2291298125
Short name T333
Test name
Test status
Simulation time 405459738402 ps
CPU time 2006.08 seconds
Started Aug 16 04:37:00 PM PDT 24
Finished Aug 16 05:10:26 PM PDT 24
Peak memory 288736 kb
Host smart-cb1fd513-9966-4301-bbe7-5ffe94e44295
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291298125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2291298125
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1800852643
Short name T308
Test name
Test status
Simulation time 11863041559 ps
CPU time 326.35 seconds
Started Aug 16 04:37:27 PM PDT 24
Finished Aug 16 04:42:54 PM PDT 24
Peak memory 247700 kb
Host smart-c9b0b80d-85c7-4a6a-9d24-58ce5788ec25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800852643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1800852643
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1870348609
Short name T140
Test name
Test status
Simulation time 1753068545 ps
CPU time 208.23 seconds
Started Aug 16 05:41:55 PM PDT 24
Finished Aug 16 05:45:24 PM PDT 24
Peak memory 265608 kb
Host smart-cd99db52-dab9-41c4-b7f7-10438316032b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1870348609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1870348609
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.204337300
Short name T290
Test name
Test status
Simulation time 83325516699 ps
CPU time 2446.92 seconds
Started Aug 16 04:36:20 PM PDT 24
Finished Aug 16 05:17:08 PM PDT 24
Peak memory 289232 kb
Host smart-7ece6a80-76e7-4859-bbeb-e8244e8417b1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204337300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.204337300
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3912173263
Short name T338
Test name
Test status
Simulation time 78113617388 ps
CPU time 2104.09 seconds
Started Aug 16 04:37:42 PM PDT 24
Finished Aug 16 05:12:46 PM PDT 24
Peak memory 273280 kb
Host smart-897d6432-c72d-4fec-80cc-84cb38eca0d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912173263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3912173263
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3606820228
Short name T159
Test name
Test status
Simulation time 13003453090 ps
CPU time 891.91 seconds
Started Aug 16 05:41:46 PM PDT 24
Finished Aug 16 05:56:38 PM PDT 24
Peak memory 265696 kb
Host smart-f44a8ece-074a-4db2-bdaa-c82914830891
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606820228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3606820228
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1832860552
Short name T312
Test name
Test status
Simulation time 177260043908 ps
CPU time 663.01 seconds
Started Aug 16 04:36:50 PM PDT 24
Finished Aug 16 04:47:53 PM PDT 24
Peak memory 247848 kb
Host smart-6069b915-1993-41af-9746-8d74d7b1eab9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832860552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1832860552
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3885606241
Short name T615
Test name
Test status
Simulation time 41639702735 ps
CPU time 2641.57 seconds
Started Aug 16 04:37:30 PM PDT 24
Finished Aug 16 05:21:33 PM PDT 24
Peak memory 289068 kb
Host smart-01b7a3ab-cc97-4a9f-938d-2b79df25dcb2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885606241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3885606241
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3395212947
Short name T85
Test name
Test status
Simulation time 41598019432 ps
CPU time 2261.77 seconds
Started Aug 16 04:37:39 PM PDT 24
Finished Aug 16 05:15:21 PM PDT 24
Peak memory 289268 kb
Host smart-b55282e6-ba3e-4b34-8e16-d8ddf9e33c72
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395212947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3395212947
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.551578312
Short name T42
Test name
Test status
Simulation time 89290867 ps
CPU time 3.47 seconds
Started Aug 16 04:37:09 PM PDT 24
Finished Aug 16 04:37:13 PM PDT 24
Peak memory 248972 kb
Host smart-7b87e5ce-d68f-4cea-9a19-4ec835a3f616
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=551578312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.551578312
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.4209552344
Short name T199
Test name
Test status
Simulation time 165431275 ps
CPU time 4.51 seconds
Started Aug 16 04:36:38 PM PDT 24
Finished Aug 16 04:36:42 PM PDT 24
Peak memory 248760 kb
Host smart-55b9e045-43f7-471f-93d8-ec42faaa5aa9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4209552344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.4209552344
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3280403463
Short name T195
Test name
Test status
Simulation time 74245098 ps
CPU time 2.49 seconds
Started Aug 16 04:36:47 PM PDT 24
Finished Aug 16 04:36:49 PM PDT 24
Peak memory 248860 kb
Host smart-331db5ff-73ee-4b89-9b62-eacbf6eee229
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3280403463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3280403463
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1652120918
Short name T212
Test name
Test status
Simulation time 89629599 ps
CPU time 2.51 seconds
Started Aug 16 04:36:44 PM PDT 24
Finished Aug 16 04:36:47 PM PDT 24
Peak memory 248864 kb
Host smart-8ddfd6cf-3940-49e8-9ab4-5ae74bb25aea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1652120918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1652120918
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.4117497469
Short name T288
Test name
Test status
Simulation time 2763199835 ps
CPU time 45.13 seconds
Started Aug 16 04:36:28 PM PDT 24
Finished Aug 16 04:37:13 PM PDT 24
Peak memory 256360 kb
Host smart-51957a29-e814-4cdd-9781-71a2dd32a9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41174
97469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.4117497469
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.370447164
Short name T250
Test name
Test status
Simulation time 14807592929 ps
CPU time 175.19 seconds
Started Aug 16 04:36:27 PM PDT 24
Finished Aug 16 04:39:22 PM PDT 24
Peak memory 266356 kb
Host smart-f5df80ab-3d94-488b-8a91-81f4894cec86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370447164 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.370447164
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1891214118
Short name T307
Test name
Test status
Simulation time 10254228365 ps
CPU time 419.92 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:44:04 PM PDT 24
Peak memory 248756 kb
Host smart-8721e218-d58c-4173-bf00-3295f7980005
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891214118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1891214118
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.317173807
Short name T501
Test name
Test status
Simulation time 42809467999 ps
CPU time 371.38 seconds
Started Aug 16 04:37:07 PM PDT 24
Finished Aug 16 04:43:24 PM PDT 24
Peak memory 248732 kb
Host smart-9db9b8a2-44b9-423c-8ece-ec96b804746c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317173807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.317173807
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.90560323
Short name T86
Test name
Test status
Simulation time 237703085448 ps
CPU time 3078.99 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 05:28:25 PM PDT 24
Peak memory 289700 kb
Host smart-0443f571-6960-40ab-89ea-db1987fdaf71
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90560323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_hand
ler_stress_all.90560323
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2584449787
Short name T332
Test name
Test status
Simulation time 146487514088 ps
CPU time 2066.4 seconds
Started Aug 16 04:37:26 PM PDT 24
Finished Aug 16 05:11:52 PM PDT 24
Peak memory 281740 kb
Host smart-d371c2d1-e9f0-49be-adf6-db6426fa2b71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584449787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2584449787
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3367875192
Short name T79
Test name
Test status
Simulation time 324652452 ps
CPU time 19.56 seconds
Started Aug 16 04:36:47 PM PDT 24
Finished Aug 16 04:37:07 PM PDT 24
Peak memory 248632 kb
Host smart-7a378c45-5632-4ea7-95b0-3cc9d7db4f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33678
75192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3367875192
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1605838604
Short name T40
Test name
Test status
Simulation time 739576435 ps
CPU time 17.7 seconds
Started Aug 16 04:37:33 PM PDT 24
Finished Aug 16 04:37:51 PM PDT 24
Peak memory 248924 kb
Host smart-410694f6-3771-4a27-a773-91d6ea2fbe05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16058
38604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1605838604
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.142594622
Short name T537
Test name
Test status
Simulation time 127493298286 ps
CPU time 1820.97 seconds
Started Aug 16 04:37:45 PM PDT 24
Finished Aug 16 05:08:06 PM PDT 24
Peak memory 273328 kb
Host smart-cb596c70-38d0-49a0-969d-3b06a58ec077
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142594622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.142594622
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.74804669
Short name T174
Test name
Test status
Simulation time 795312231 ps
CPU time 3.62 seconds
Started Aug 16 05:41:32 PM PDT 24
Finished Aug 16 05:41:41 PM PDT 24
Peak memory 238032 kb
Host smart-a9f3cc85-2c96-4baf-bce5-62af5a42e48a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=74804669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.74804669
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.802440071
Short name T105
Test name
Test status
Simulation time 26946251222 ps
CPU time 1440.02 seconds
Started Aug 16 04:37:28 PM PDT 24
Finished Aug 16 05:01:28 PM PDT 24
Peak memory 289304 kb
Host smart-e6f34a35-893f-4398-998d-75cb0246684f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802440071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.802440071
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3328524737
Short name T157
Test name
Test status
Simulation time 5457238825 ps
CPU time 137.19 seconds
Started Aug 16 05:41:47 PM PDT 24
Finished Aug 16 05:44:04 PM PDT 24
Peak memory 268148 kb
Host smart-40980091-f145-48e6-910e-3b4ffcf3ea6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3328524737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3328524737
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.404526216
Short name T165
Test name
Test status
Simulation time 56803281 ps
CPU time 4.85 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:18 PM PDT 24
Peak memory 248884 kb
Host smart-07449757-a974-426f-b416-a4bad7329648
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=404526216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.404526216
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2290775970
Short name T145
Test name
Test status
Simulation time 6532615065 ps
CPU time 214.37 seconds
Started Aug 16 05:41:26 PM PDT 24
Finished Aug 16 05:45:00 PM PDT 24
Peak memory 273232 kb
Host smart-da8215b9-1a09-4c9d-a5d2-3ab54ba6e3f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2290775970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2290775970
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4062834381
Short name T147
Test name
Test status
Simulation time 32636237934 ps
CPU time 1232.06 seconds
Started Aug 16 05:41:30 PM PDT 24
Finished Aug 16 06:02:02 PM PDT 24
Peak memory 265556 kb
Host smart-903f8575-debf-4a85-839e-f243bf31c278
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062834381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.4062834381
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2896241821
Short name T725
Test name
Test status
Simulation time 17482590 ps
CPU time 1.78 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 236868 kb
Host smart-b63d465e-4567-450a-81bb-43a5399697d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2896241821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2896241821
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1613275220
Short name T530
Test name
Test status
Simulation time 1456191075 ps
CPU time 116.76 seconds
Started Aug 16 04:36:07 PM PDT 24
Finished Aug 16 04:38:04 PM PDT 24
Peak memory 256864 kb
Host smart-16d3fdd4-0cbd-4fbc-b40c-45c61dd260f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16132
75220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1613275220
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2288367656
Short name T287
Test name
Test status
Simulation time 144773162617 ps
CPU time 4072.29 seconds
Started Aug 16 04:36:26 PM PDT 24
Finished Aug 16 05:44:19 PM PDT 24
Peak memory 297448 kb
Host smart-98356dad-ce7f-4e2c-816d-fc3f498f0dd2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288367656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2288367656
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.854675810
Short name T314
Test name
Test status
Simulation time 30573825548 ps
CPU time 312.54 seconds
Started Aug 16 04:36:48 PM PDT 24
Finished Aug 16 04:42:00 PM PDT 24
Peak memory 248764 kb
Host smart-a10f2246-af1f-40cb-a2e2-3272cc004553
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854675810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.854675810
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1040959543
Short name T45
Test name
Test status
Simulation time 853282283 ps
CPU time 48.15 seconds
Started Aug 16 04:36:53 PM PDT 24
Finished Aug 16 04:37:41 PM PDT 24
Peak memory 256244 kb
Host smart-84d0c4f4-db32-49bb-b798-1808bf8534cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10409
59543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1040959543
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3591860595
Short name T77
Test name
Test status
Simulation time 14249677438 ps
CPU time 50.26 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 04:37:51 PM PDT 24
Peak memory 256320 kb
Host smart-5df03e96-2ab3-4f12-b131-931ac7f974ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35918
60595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3591860595
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1031509822
Short name T271
Test name
Test status
Simulation time 906946996 ps
CPU time 59.95 seconds
Started Aug 16 04:36:52 PM PDT 24
Finished Aug 16 04:37:52 PM PDT 24
Peak memory 248716 kb
Host smart-42d7df17-dffd-4985-b032-4fff86e3521a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10315
09822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1031509822
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3972136133
Short name T293
Test name
Test status
Simulation time 215416675176 ps
CPU time 2670.7 seconds
Started Aug 16 04:37:13 PM PDT 24
Finished Aug 16 05:21:44 PM PDT 24
Peak memory 305940 kb
Host smart-98ab1e34-a653-4805-9c0a-8a200bc20f96
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972136133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3972136133
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3261345469
Short name T280
Test name
Test status
Simulation time 58925899244 ps
CPU time 3294.78 seconds
Started Aug 16 04:36:57 PM PDT 24
Finished Aug 16 05:31:55 PM PDT 24
Peak memory 297408 kb
Host smart-e791604e-6231-456d-a417-d25500ad4461
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261345469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3261345469
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3049588506
Short name T300
Test name
Test status
Simulation time 47302145682 ps
CPU time 880.49 seconds
Started Aug 16 04:37:13 PM PDT 24
Finished Aug 16 04:51:54 PM PDT 24
Peak memory 273208 kb
Host smart-9a9ea7ee-c112-4102-a529-e5caab7becc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049588506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3049588506
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1323340372
Short name T21
Test name
Test status
Simulation time 1785386333 ps
CPU time 52.13 seconds
Started Aug 16 04:37:09 PM PDT 24
Finished Aug 16 04:38:01 PM PDT 24
Peak memory 255972 kb
Host smart-2696ae94-0fb8-42b8-aedd-f4e3834ef3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13233
40372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1323340372
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3715447319
Short name T80
Test name
Test status
Simulation time 518024441 ps
CPU time 38.52 seconds
Started Aug 16 04:37:23 PM PDT 24
Finished Aug 16 04:38:01 PM PDT 24
Peak memory 249176 kb
Host smart-35eda8f8-fb61-4a5b-b96d-bdf0d4b5c5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37154
47319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3715447319
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.857374749
Short name T89
Test name
Test status
Simulation time 2758333249 ps
CPU time 320.38 seconds
Started Aug 16 04:36:45 PM PDT 24
Finished Aug 16 04:42:06 PM PDT 24
Peak memory 269144 kb
Host smart-3cca294e-3a0c-44ae-8e50-cf9e20513117
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857374749 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.857374749
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.59947066
Short name T158
Test name
Test status
Simulation time 4538579292 ps
CPU time 318.1 seconds
Started Aug 16 05:41:35 PM PDT 24
Finished Aug 16 05:46:53 PM PDT 24
Peak memory 266740 kb
Host smart-37596956-a1a0-40cc-a121-b8012fc442ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59947066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_error
s.59947066
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1814671129
Short name T170
Test name
Test status
Simulation time 298644973 ps
CPU time 2.43 seconds
Started Aug 16 05:41:45 PM PDT 24
Finished Aug 16 05:41:47 PM PDT 24
Peak memory 236788 kb
Host smart-98986083-9338-4b3b-a516-c5fc7c35b52f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1814671129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1814671129
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3117274520
Short name T177
Test name
Test status
Simulation time 2167248339 ps
CPU time 67.45 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:42:24 PM PDT 24
Peak memory 238084 kb
Host smart-d697d8d1-25f2-49c6-b319-826f1e1dc687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3117274520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3117274520
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1925879114
Short name T163
Test name
Test status
Simulation time 474744896 ps
CPU time 36.72 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:48 PM PDT 24
Peak memory 240712 kb
Host smart-dce377cc-614b-41f2-a788-c680a30e2e66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1925879114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1925879114
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3775424040
Short name T172
Test name
Test status
Simulation time 1252813141 ps
CPU time 44.56 seconds
Started Aug 16 05:41:17 PM PDT 24
Finished Aug 16 05:42:02 PM PDT 24
Peak memory 245964 kb
Host smart-4fb6dc3e-d4f5-4482-b8a4-777f931241bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3775424040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3775424040
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1332290857
Short name T173
Test name
Test status
Simulation time 8832025314 ps
CPU time 67.25 seconds
Started Aug 16 05:41:25 PM PDT 24
Finished Aug 16 05:42:32 PM PDT 24
Peak memory 240736 kb
Host smart-a305391c-7260-414d-9ed5-ef4ced213961
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1332290857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1332290857
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1226609184
Short name T154
Test name
Test status
Simulation time 6085690302 ps
CPU time 363.31 seconds
Started Aug 16 05:41:43 PM PDT 24
Finished Aug 16 05:47:47 PM PDT 24
Peak memory 265672 kb
Host smart-1ca46ce7-9147-4344-9366-9a98583e2272
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1226609184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1226609184
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1295996679
Short name T175
Test name
Test status
Simulation time 467779545 ps
CPU time 32.58 seconds
Started Aug 16 05:41:18 PM PDT 24
Finished Aug 16 05:41:51 PM PDT 24
Peak memory 240524 kb
Host smart-0ae07d4e-1249-4010-8a9d-1b9264c46f24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1295996679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1295996679
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3887487300
Short name T183
Test name
Test status
Simulation time 586818058 ps
CPU time 21.72 seconds
Started Aug 16 05:41:47 PM PDT 24
Finished Aug 16 05:42:09 PM PDT 24
Peak memory 237892 kb
Host smart-485ceac6-7f68-438e-8837-e8ffe7f342b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3887487300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3887487300
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2980706823
Short name T169
Test name
Test status
Simulation time 845319247 ps
CPU time 3.71 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:19 PM PDT 24
Peak memory 237620 kb
Host smart-ad6f86fc-e5f1-458a-93c1-5e7cc08594a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2980706823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2980706823
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2332163951
Short name T168
Test name
Test status
Simulation time 24485263 ps
CPU time 2.41 seconds
Started Aug 16 05:41:27 PM PDT 24
Finished Aug 16 05:41:30 PM PDT 24
Peak memory 236880 kb
Host smart-f42e6283-029a-4679-8e8a-7192a06226e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2332163951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2332163951
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3306579742
Short name T176
Test name
Test status
Simulation time 116106140 ps
CPU time 2.75 seconds
Started Aug 16 05:42:00 PM PDT 24
Finished Aug 16 05:42:03 PM PDT 24
Peak memory 237760 kb
Host smart-835badb4-139c-4f4f-98d9-c414adbc8a62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3306579742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3306579742
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2896082522
Short name T771
Test name
Test status
Simulation time 8473101899 ps
CPU time 297.95 seconds
Started Aug 16 05:41:19 PM PDT 24
Finished Aug 16 05:46:17 PM PDT 24
Peak memory 241304 kb
Host smart-443af7c5-806c-4bac-a241-720f90f3f552
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2896082522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2896082522
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1990257565
Short name T791
Test name
Test status
Simulation time 1704606951 ps
CPU time 244.8 seconds
Started Aug 16 05:41:39 PM PDT 24
Finished Aug 16 05:45:44 PM PDT 24
Peak memory 237740 kb
Host smart-31ae307a-2c0f-4e33-a285-0ca570e4b9f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1990257565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1990257565
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.18168224
Short name T822
Test name
Test status
Simulation time 247000441 ps
CPU time 4.34 seconds
Started Aug 16 05:41:43 PM PDT 24
Finished Aug 16 05:41:47 PM PDT 24
Peak memory 240476 kb
Host smart-44bef76e-66bf-40cf-9c87-77e41745ddee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18168224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.alert_handler_csr_mem_rw_with_rand_reset.18168224
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.304867321
Short name T787
Test name
Test status
Simulation time 34914913 ps
CPU time 4.8 seconds
Started Aug 16 05:41:39 PM PDT 24
Finished Aug 16 05:41:44 PM PDT 24
Peak memory 236828 kb
Host smart-222e8e8e-cd33-4c91-a3b5-e5f418ec2200
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=304867321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.304867321
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1211570701
Short name T752
Test name
Test status
Simulation time 10183843 ps
CPU time 1.31 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 235784 kb
Host smart-e97b2fd3-9aae-4c87-abde-4cc059bd48ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1211570701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1211570701
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3175991633
Short name T801
Test name
Test status
Simulation time 539125245 ps
CPU time 39.69 seconds
Started Aug 16 05:41:28 PM PDT 24
Finished Aug 16 05:42:08 PM PDT 24
Peak memory 245872 kb
Host smart-b0009a38-7659-4adc-b54b-be13dc3bc5bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3175991633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3175991633
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1921232645
Short name T814
Test name
Test status
Simulation time 7048140812 ps
CPU time 88.12 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:42:42 PM PDT 24
Peak memory 265588 kb
Host smart-79924f44-488d-4437-b0e9-c6fa43c94b1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1921232645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1921232645
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1978896299
Short name T126
Test name
Test status
Simulation time 14250914394 ps
CPU time 487.93 seconds
Started Aug 16 05:41:30 PM PDT 24
Finished Aug 16 05:49:38 PM PDT 24
Peak memory 265632 kb
Host smart-ad41fb0e-f20d-4ba9-b134-8615bb855c27
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978896299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1978896299
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1666246731
Short name T716
Test name
Test status
Simulation time 122132014 ps
CPU time 8.59 seconds
Started Aug 16 05:41:17 PM PDT 24
Finished Aug 16 05:41:26 PM PDT 24
Peak memory 249000 kb
Host smart-9a0049ff-4352-42c5-b99d-cbca299a81d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1666246731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1666246731
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.340483180
Short name T728
Test name
Test status
Simulation time 7984995384 ps
CPU time 143.19 seconds
Started Aug 16 05:41:21 PM PDT 24
Finished Aug 16 05:43:44 PM PDT 24
Peak memory 236724 kb
Host smart-dbf7a0bc-fb7b-4332-93e5-82af78c4aa7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=340483180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.340483180
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1097021127
Short name T755
Test name
Test status
Simulation time 2638271819 ps
CPU time 94.36 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:42:48 PM PDT 24
Peak memory 240768 kb
Host smart-20753d8d-4117-4d9d-8914-caa08bd9a498
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1097021127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1097021127
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.912282390
Short name T820
Test name
Test status
Simulation time 118986779 ps
CPU time 9.55 seconds
Started Aug 16 05:41:30 PM PDT 24
Finished Aug 16 05:41:39 PM PDT 24
Peak memory 248812 kb
Host smart-652a676f-188d-4621-8502-5a803f974076
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=912282390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.912282390
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1596377002
Short name T817
Test name
Test status
Simulation time 205965254 ps
CPU time 8.33 seconds
Started Aug 16 05:41:02 PM PDT 24
Finished Aug 16 05:41:10 PM PDT 24
Peak memory 251792 kb
Host smart-5bd7c29d-81ae-400b-bfca-9f1fb8a72ac2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596377002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1596377002
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2475168587
Short name T185
Test name
Test status
Simulation time 125361223 ps
CPU time 4.99 seconds
Started Aug 16 05:41:17 PM PDT 24
Finished Aug 16 05:41:22 PM PDT 24
Peak memory 237620 kb
Host smart-984a157d-52cd-4855-8d9b-7687bb742e02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2475168587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2475168587
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1162819461
Short name T784
Test name
Test status
Simulation time 6449251 ps
CPU time 1.39 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 236872 kb
Host smart-40ef020a-4f61-4e0e-8136-ac8cfefbdd08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1162819461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1162819461
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3552248291
Short name T789
Test name
Test status
Simulation time 368417592 ps
CPU time 11.88 seconds
Started Aug 16 05:41:26 PM PDT 24
Finished Aug 16 05:41:38 PM PDT 24
Peak memory 240736 kb
Host smart-bddb2c91-31a5-4914-be12-1b575b9ca2ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3552248291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3552248291
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2871758580
Short name T148
Test name
Test status
Simulation time 907733707 ps
CPU time 103.48 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:42:57 PM PDT 24
Peak memory 257408 kb
Host smart-edd96505-87c7-444d-913c-06d09536f116
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2871758580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2871758580
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3172613629
Short name T156
Test name
Test status
Simulation time 11521953787 ps
CPU time 568.01 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:50:42 PM PDT 24
Peak memory 265636 kb
Host smart-df830478-55cb-4af4-92d2-78ead0cda1a9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172613629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3172613629
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1243017977
Short name T738
Test name
Test status
Simulation time 624465611 ps
CPU time 8.42 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:22 PM PDT 24
Peak memory 248876 kb
Host smart-f8183d77-044b-4d5c-8770-ba36ed382154
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1243017977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1243017977
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3794478585
Short name T180
Test name
Test status
Simulation time 53730133 ps
CPU time 2.59 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:41:23 PM PDT 24
Peak memory 237764 kb
Host smart-18cbf7d7-f8ed-47a1-a5c4-17f6fce8c2b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3794478585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3794478585
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1317401751
Short name T779
Test name
Test status
Simulation time 158395023 ps
CPU time 11.25 seconds
Started Aug 16 05:41:41 PM PDT 24
Finished Aug 16 05:41:52 PM PDT 24
Peak memory 241976 kb
Host smart-e51cbf28-bac3-484f-be13-7f75907b7b12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317401751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1317401751
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2648278539
Short name T776
Test name
Test status
Simulation time 218105496 ps
CPU time 7.83 seconds
Started Aug 16 05:41:19 PM PDT 24
Finished Aug 16 05:41:27 PM PDT 24
Peak memory 236752 kb
Host smart-7727d87e-52cc-498c-916e-df1c61c0f3fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2648278539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2648278539
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2334063862
Short name T775
Test name
Test status
Simulation time 20241364 ps
CPU time 1.8 seconds
Started Aug 16 05:41:17 PM PDT 24
Finished Aug 16 05:41:19 PM PDT 24
Peak memory 236884 kb
Host smart-0b629641-d7d8-4f65-af4d-eb10b4cbb052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2334063862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2334063862
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3447461027
Short name T762
Test name
Test status
Simulation time 82963298 ps
CPU time 11.18 seconds
Started Aug 16 05:41:18 PM PDT 24
Finished Aug 16 05:41:29 PM PDT 24
Peak memory 240660 kb
Host smart-d43cdcad-2d22-4337-8853-8bf0dae878c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3447461027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3447461027
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3347993469
Short name T138
Test name
Test status
Simulation time 2459621903 ps
CPU time 162.06 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:43:58 PM PDT 24
Peak memory 265520 kb
Host smart-b854c1c9-b8d0-4165-8de3-615dc2d41cb4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3347993469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3347993469
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1348403671
Short name T758
Test name
Test status
Simulation time 121209762 ps
CPU time 4.28 seconds
Started Aug 16 05:41:27 PM PDT 24
Finished Aug 16 05:41:31 PM PDT 24
Peak memory 248876 kb
Host smart-30a1dd60-a77d-4571-973f-4b097ba255c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1348403671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1348403671
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.665080107
Short name T246
Test name
Test status
Simulation time 632223592 ps
CPU time 37.92 seconds
Started Aug 16 05:41:59 PM PDT 24
Finished Aug 16 05:42:37 PM PDT 24
Peak memory 237904 kb
Host smart-25343039-4753-45c1-9061-847a0ee2d1b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=665080107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.665080107
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.409892678
Short name T805
Test name
Test status
Simulation time 474340440 ps
CPU time 5.51 seconds
Started Aug 16 05:41:44 PM PDT 24
Finished Aug 16 05:41:49 PM PDT 24
Peak memory 248976 kb
Host smart-8f15aa6c-dc96-4a7c-9f80-f352af6c9317
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409892678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.409892678
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3928700039
Short name T178
Test name
Test status
Simulation time 145344391 ps
CPU time 2.92 seconds
Started Aug 16 05:41:26 PM PDT 24
Finished Aug 16 05:41:29 PM PDT 24
Peak memory 236748 kb
Host smart-6e8ee528-3ad7-432d-a05c-14c6bb5350d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3928700039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3928700039
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.209274588
Short name T730
Test name
Test status
Simulation time 358946903 ps
CPU time 25.14 seconds
Started Aug 16 05:41:39 PM PDT 24
Finished Aug 16 05:42:04 PM PDT 24
Peak memory 245940 kb
Host smart-fbd7023e-0616-412c-9290-fcc2a8307faa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=209274588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.209274588
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2531544832
Short name T826
Test name
Test status
Simulation time 1084989783 ps
CPU time 104.71 seconds
Started Aug 16 05:41:21 PM PDT 24
Finished Aug 16 05:43:06 PM PDT 24
Peak memory 257356 kb
Host smart-d3fd3d99-d192-447e-a2d2-376c0089b1e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2531544832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2531544832
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3941505905
Short name T735
Test name
Test status
Simulation time 1055288569 ps
CPU time 19.9 seconds
Started Aug 16 05:41:37 PM PDT 24
Finished Aug 16 05:41:57 PM PDT 24
Peak memory 254296 kb
Host smart-84091021-cd94-4d29-a336-df2cc82f8ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3941505905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3941505905
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1451170329
Short name T194
Test name
Test status
Simulation time 738022117 ps
CPU time 12.14 seconds
Started Aug 16 05:41:41 PM PDT 24
Finished Aug 16 05:41:53 PM PDT 24
Peak memory 248972 kb
Host smart-5d6d185a-09c2-4c33-a583-458f1d7ce4fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451170329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1451170329
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2721091747
Short name T799
Test name
Test status
Simulation time 50945702 ps
CPU time 4.62 seconds
Started Aug 16 05:41:47 PM PDT 24
Finished Aug 16 05:41:52 PM PDT 24
Peak memory 237760 kb
Host smart-033c9526-a6b3-4786-b5d0-9021ac0022e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2721091747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2721091747
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2392403211
Short name T223
Test name
Test status
Simulation time 10641147 ps
CPU time 1.27 seconds
Started Aug 16 05:41:51 PM PDT 24
Finished Aug 16 05:41:53 PM PDT 24
Peak memory 236892 kb
Host smart-c70af282-9850-47ff-8a62-45fcb7f6bf66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2392403211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2392403211
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1347134164
Short name T189
Test name
Test status
Simulation time 3151586828 ps
CPU time 37.85 seconds
Started Aug 16 05:41:52 PM PDT 24
Finished Aug 16 05:42:30 PM PDT 24
Peak memory 248968 kb
Host smart-faa3750d-0bf3-4f4f-847e-28337af018a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1347134164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1347134164
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3659184220
Short name T241
Test name
Test status
Simulation time 763637844 ps
CPU time 26.11 seconds
Started Aug 16 05:41:41 PM PDT 24
Finished Aug 16 05:42:07 PM PDT 24
Peak memory 255292 kb
Host smart-6ab7798f-a580-4bee-84da-ea852d615112
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3659184220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3659184220
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.787446162
Short name T744
Test name
Test status
Simulation time 164503382 ps
CPU time 11.88 seconds
Started Aug 16 05:41:40 PM PDT 24
Finished Aug 16 05:41:52 PM PDT 24
Peak memory 252000 kb
Host smart-1d2429b5-75d5-43be-aa28-4e911605ca6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787446162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.787446162
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.584767551
Short name T723
Test name
Test status
Simulation time 95294592 ps
CPU time 4.27 seconds
Started Aug 16 05:41:34 PM PDT 24
Finished Aug 16 05:41:38 PM PDT 24
Peak memory 240708 kb
Host smart-2c9a00fd-0d35-4d7e-b5aa-58237bd88c77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=584767551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.584767551
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3106362577
Short name T745
Test name
Test status
Simulation time 11378368 ps
CPU time 1.55 seconds
Started Aug 16 05:41:47 PM PDT 24
Finished Aug 16 05:41:49 PM PDT 24
Peak memory 236764 kb
Host smart-c3746ac9-d4f6-4eb2-975d-04d710ac1bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3106362577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3106362577
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.860235275
Short name T807
Test name
Test status
Simulation time 685338828 ps
CPU time 21.88 seconds
Started Aug 16 05:42:00 PM PDT 24
Finished Aug 16 05:42:22 PM PDT 24
Peak memory 245984 kb
Host smart-eb4957c1-f864-4f79-8ee4-c3f36a9fc56f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=860235275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.860235275
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1065746346
Short name T151
Test name
Test status
Simulation time 46088410935 ps
CPU time 416.11 seconds
Started Aug 16 05:41:56 PM PDT 24
Finished Aug 16 05:48:52 PM PDT 24
Peak memory 265724 kb
Host smart-c8dc124c-f5ed-4605-94aa-2804f5b1c5e2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065746346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1065746346
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2179093277
Short name T798
Test name
Test status
Simulation time 955344035 ps
CPU time 17.79 seconds
Started Aug 16 05:41:40 PM PDT 24
Finished Aug 16 05:41:58 PM PDT 24
Peak memory 247456 kb
Host smart-ef2a9bd8-8e68-461a-b4fe-63ce465a1498
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2179093277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2179093277
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1664695651
Short name T781
Test name
Test status
Simulation time 103228032 ps
CPU time 7.2 seconds
Started Aug 16 05:41:21 PM PDT 24
Finished Aug 16 05:41:29 PM PDT 24
Peak memory 240520 kb
Host smart-f423f43d-9717-4f7a-9f3b-679854a77668
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664695651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1664695651
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3194285861
Short name T724
Test name
Test status
Simulation time 101399080 ps
CPU time 7.73 seconds
Started Aug 16 05:41:41 PM PDT 24
Finished Aug 16 05:41:49 PM PDT 24
Peak memory 240680 kb
Host smart-e188d8e6-e1e5-4b04-9a47-3e2e13063da3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3194285861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3194285861
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.286108593
Short name T768
Test name
Test status
Simulation time 10438329 ps
CPU time 1.45 seconds
Started Aug 16 05:41:22 PM PDT 24
Finished Aug 16 05:41:23 PM PDT 24
Peak memory 235808 kb
Host smart-cd710d52-afc7-47fd-a724-80a52f70f55f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=286108593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.286108593
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2307423579
Short name T795
Test name
Test status
Simulation time 957018418 ps
CPU time 18.4 seconds
Started Aug 16 05:41:19 PM PDT 24
Finished Aug 16 05:41:37 PM PDT 24
Peak memory 245020 kb
Host smart-51ac2ec8-b1e7-4e1b-a27b-7eaff1d191ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2307423579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2307423579
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.177920248
Short name T139
Test name
Test status
Simulation time 54308234700 ps
CPU time 514.36 seconds
Started Aug 16 05:41:45 PM PDT 24
Finished Aug 16 05:50:20 PM PDT 24
Peak memory 265720 kb
Host smart-f23c5259-6aea-4e33-9cdf-48ee31d7eb7f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177920248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.177920248
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1275598436
Short name T746
Test name
Test status
Simulation time 98204793 ps
CPU time 7.15 seconds
Started Aug 16 05:41:39 PM PDT 24
Finished Aug 16 05:41:47 PM PDT 24
Peak memory 252596 kb
Host smart-279be23e-bce1-423f-833b-bb470e3eabd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1275598436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1275598436
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2339413858
Short name T162
Test name
Test status
Simulation time 106558735 ps
CPU time 2.56 seconds
Started Aug 16 05:41:57 PM PDT 24
Finished Aug 16 05:42:00 PM PDT 24
Peak memory 238172 kb
Host smart-496e6c16-5e17-4277-8f3d-d1182521b489
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2339413858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2339413858
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3786574295
Short name T179
Test name
Test status
Simulation time 235288059 ps
CPU time 9.43 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:26 PM PDT 24
Peak memory 252928 kb
Host smart-a3d03bc3-14b5-4c26-a1dc-af27d5d51940
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786574295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3786574295
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1279791846
Short name T759
Test name
Test status
Simulation time 806823159 ps
CPU time 7.61 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:22 PM PDT 24
Peak memory 240656 kb
Host smart-86d18d6c-1baf-4cb1-a822-3764141e18f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1279791846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1279791846
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2614504160
Short name T727
Test name
Test status
Simulation time 13266908 ps
CPU time 1.28 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:15 PM PDT 24
Peak memory 237756 kb
Host smart-3d4f8340-5b21-4250-bdd1-349240b8bd43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2614504160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2614504160
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1889147892
Short name T193
Test name
Test status
Simulation time 342811482 ps
CPU time 21.29 seconds
Started Aug 16 05:41:26 PM PDT 24
Finished Aug 16 05:41:47 PM PDT 24
Peak memory 245908 kb
Host smart-5a7ee0a1-f7ed-4d88-b86d-9e50be35a8e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1889147892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1889147892
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2032535018
Short name T152
Test name
Test status
Simulation time 2026779128 ps
CPU time 112.01 seconds
Started Aug 16 05:41:46 PM PDT 24
Finished Aug 16 05:43:38 PM PDT 24
Peak memory 265504 kb
Host smart-de16347e-b6bc-401c-a385-8b96e0c59864
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2032535018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2032535018
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1277151388
Short name T160
Test name
Test status
Simulation time 2349539924 ps
CPU time 279.32 seconds
Started Aug 16 05:41:45 PM PDT 24
Finished Aug 16 05:46:24 PM PDT 24
Peak memory 265692 kb
Host smart-e1946f3b-0bec-4384-b553-b3edbfcf5608
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277151388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1277151388
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.153453113
Short name T711
Test name
Test status
Simulation time 630121043 ps
CPU time 22.33 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:39 PM PDT 24
Peak memory 257100 kb
Host smart-00e19283-62aa-4c9f-a193-232633ba24ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=153453113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.153453113
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.181773510
Short name T747
Test name
Test status
Simulation time 57961933 ps
CPU time 4.96 seconds
Started Aug 16 05:41:47 PM PDT 24
Finished Aug 16 05:41:56 PM PDT 24
Peak memory 240760 kb
Host smart-a820f42f-b6aa-4ba5-8d1d-920d719b93db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181773510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.181773510
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3477654384
Short name T717
Test name
Test status
Simulation time 568664004 ps
CPU time 9.06 seconds
Started Aug 16 05:41:53 PM PDT 24
Finished Aug 16 05:42:02 PM PDT 24
Peak memory 237756 kb
Host smart-f9c34aac-de88-4315-ae3f-01721e34fde8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3477654384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3477654384
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.331067105
Short name T712
Test name
Test status
Simulation time 20875537 ps
CPU time 1.36 seconds
Started Aug 16 05:41:41 PM PDT 24
Finished Aug 16 05:41:42 PM PDT 24
Peak memory 236892 kb
Host smart-26526bf7-512a-4660-bb60-1e6cfe593aa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=331067105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.331067105
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.4063469241
Short name T783
Test name
Test status
Simulation time 2695317074 ps
CPU time 22.37 seconds
Started Aug 16 05:41:29 PM PDT 24
Finished Aug 16 05:41:51 PM PDT 24
Peak memory 245888 kb
Host smart-a65f3ed3-ade8-454e-9770-4d52b15cdd94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4063469241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.4063469241
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3104668472
Short name T802
Test name
Test status
Simulation time 60249563 ps
CPU time 4.33 seconds
Started Aug 16 05:41:38 PM PDT 24
Finished Aug 16 05:41:42 PM PDT 24
Peak memory 247244 kb
Host smart-e4a29943-8edb-4785-9e93-59beff778445
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3104668472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3104668472
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3348458064
Short name T739
Test name
Test status
Simulation time 58652993 ps
CPU time 9.37 seconds
Started Aug 16 05:41:38 PM PDT 24
Finished Aug 16 05:41:47 PM PDT 24
Peak memory 254440 kb
Host smart-a0ddb20c-6216-46c4-b26d-637e994364c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348458064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3348458064
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3524321928
Short name T829
Test name
Test status
Simulation time 62347646 ps
CPU time 5.24 seconds
Started Aug 16 05:41:43 PM PDT 24
Finished Aug 16 05:41:54 PM PDT 24
Peak memory 236900 kb
Host smart-fa5f39ba-89bb-4ff5-bd18-d45e35246e43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3524321928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3524321928
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2084348138
Short name T797
Test name
Test status
Simulation time 9657306 ps
CPU time 1.26 seconds
Started Aug 16 05:41:20 PM PDT 24
Finished Aug 16 05:41:22 PM PDT 24
Peak memory 235744 kb
Host smart-19c3afea-014a-4192-874f-f484d9139305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2084348138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2084348138
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.568272261
Short name T756
Test name
Test status
Simulation time 1042294797 ps
CPU time 19.26 seconds
Started Aug 16 05:41:35 PM PDT 24
Finished Aug 16 05:41:54 PM PDT 24
Peak memory 245952 kb
Host smart-3ba80981-92f7-4ac6-91b7-a3dcbb337fc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=568272261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.568272261
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1237183166
Short name T161
Test name
Test status
Simulation time 2385610436 ps
CPU time 158.53 seconds
Started Aug 16 05:41:44 PM PDT 24
Finished Aug 16 05:44:23 PM PDT 24
Peak memory 265668 kb
Host smart-c4578f83-8622-48ca-868a-d1a592a6ace1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1237183166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1237183166
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3118705430
Short name T135
Test name
Test status
Simulation time 4055848737 ps
CPU time 267.74 seconds
Started Aug 16 05:41:29 PM PDT 24
Finished Aug 16 05:45:57 PM PDT 24
Peak memory 265632 kb
Host smart-baf42121-9957-456f-83a2-af90204deafa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118705430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3118705430
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2398388941
Short name T737
Test name
Test status
Simulation time 236531954 ps
CPU time 14.9 seconds
Started Aug 16 05:41:55 PM PDT 24
Finished Aug 16 05:42:11 PM PDT 24
Peak memory 254512 kb
Host smart-ce557b37-789d-4fbd-b050-e583ba9126b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2398388941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2398388941
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3444766426
Short name T182
Test name
Test status
Simulation time 668086716 ps
CPU time 36.19 seconds
Started Aug 16 05:41:42 PM PDT 24
Finished Aug 16 05:42:18 PM PDT 24
Peak memory 240680 kb
Host smart-423807c6-3fbf-4fcb-885f-d2a80777f9b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3444766426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3444766426
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4131956064
Short name T344
Test name
Test status
Simulation time 76009147 ps
CPU time 7.47 seconds
Started Aug 16 05:41:57 PM PDT 24
Finished Aug 16 05:42:04 PM PDT 24
Peak memory 240788 kb
Host smart-0d2e3f86-2b64-42a7-82d6-7af2317b59d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131956064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4131956064
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.357299043
Short name T804
Test name
Test status
Simulation time 259971012 ps
CPU time 9.29 seconds
Started Aug 16 05:41:34 PM PDT 24
Finished Aug 16 05:41:43 PM PDT 24
Peak memory 237772 kb
Host smart-2bba7e27-b191-4451-b65f-78af42ff575a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=357299043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.357299043
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1741579438
Short name T763
Test name
Test status
Simulation time 11749326 ps
CPU time 1.43 seconds
Started Aug 16 05:42:01 PM PDT 24
Finished Aug 16 05:42:03 PM PDT 24
Peak memory 236768 kb
Host smart-134313c4-b985-4ff4-8d85-63634b4872fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1741579438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1741579438
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.738382572
Short name T780
Test name
Test status
Simulation time 2091834185 ps
CPU time 35.16 seconds
Started Aug 16 05:41:32 PM PDT 24
Finished Aug 16 05:42:07 PM PDT 24
Peak memory 245084 kb
Host smart-beacd92d-772e-4dbb-944c-0d13de88ee02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=738382572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.738382572
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.914576265
Short name T345
Test name
Test status
Simulation time 4470799876 ps
CPU time 307.87 seconds
Started Aug 16 05:42:03 PM PDT 24
Finished Aug 16 05:47:11 PM PDT 24
Peak memory 265664 kb
Host smart-5619e6cd-219a-4b52-b779-3e2d13fcda31
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914576265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.914576265
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.603732064
Short name T812
Test name
Test status
Simulation time 104984584 ps
CPU time 12.68 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:27 PM PDT 24
Peak memory 248960 kb
Host smart-a37f07a8-b619-4b87-bd99-2d3d3b207880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=603732064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.603732064
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2914907231
Short name T243
Test name
Test status
Simulation time 1706499856 ps
CPU time 7.14 seconds
Started Aug 16 05:41:50 PM PDT 24
Finished Aug 16 05:41:57 PM PDT 24
Peak memory 240556 kb
Host smart-1cda82f6-823a-4dfb-b2e8-733db8a804aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914907231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2914907231
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3156124759
Short name T827
Test name
Test status
Simulation time 270061871 ps
CPU time 5.4 seconds
Started Aug 16 05:41:29 PM PDT 24
Finished Aug 16 05:41:34 PM PDT 24
Peak memory 237760 kb
Host smart-e42b23a7-fcfa-4905-b13a-8c0573d48fdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3156124759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3156124759
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3724300202
Short name T821
Test name
Test status
Simulation time 13193346 ps
CPU time 1.29 seconds
Started Aug 16 05:41:34 PM PDT 24
Finished Aug 16 05:41:35 PM PDT 24
Peak memory 236832 kb
Host smart-79ed1cca-acd4-45db-b14b-2567711ebf47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3724300202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3724300202
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3896855617
Short name T796
Test name
Test status
Simulation time 257427744 ps
CPU time 17.8 seconds
Started Aug 16 05:41:55 PM PDT 24
Finished Aug 16 05:42:13 PM PDT 24
Peak memory 245060 kb
Host smart-65693d39-f7c1-4fdb-8595-c8fcbb168a53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3896855617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3896855617
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3016925745
Short name T825
Test name
Test status
Simulation time 8642284542 ps
CPU time 316.72 seconds
Started Aug 16 05:41:37 PM PDT 24
Finished Aug 16 05:46:54 PM PDT 24
Peak memory 269060 kb
Host smart-421373af-6123-4e47-ba5c-b7aeb6e0dd57
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016925745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3016925745
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4293666316
Short name T707
Test name
Test status
Simulation time 284090796 ps
CPU time 5.55 seconds
Started Aug 16 05:41:38 PM PDT 24
Finished Aug 16 05:41:43 PM PDT 24
Peak memory 248916 kb
Host smart-8bc7f9d7-c74d-4d80-a349-9808213e93f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4293666316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4293666316
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1396356036
Short name T809
Test name
Test status
Simulation time 2145033358 ps
CPU time 42.01 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:58 PM PDT 24
Peak memory 240684 kb
Host smart-85e8d376-98f4-491e-8d3e-ac555f54c8dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1396356036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1396356036
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4036820851
Short name T733
Test name
Test status
Simulation time 7490168061 ps
CPU time 111.21 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:43:06 PM PDT 24
Peak memory 240768 kb
Host smart-8d9131e3-4f04-4d8b-92e6-8decbbfaa747
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4036820851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.4036820851
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3018228915
Short name T811
Test name
Test status
Simulation time 7752515016 ps
CPU time 404.08 seconds
Started Aug 16 05:41:17 PM PDT 24
Finished Aug 16 05:48:01 PM PDT 24
Peak memory 236940 kb
Host smart-495e0559-e008-4c97-bd34-5c5e88d11e74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3018228915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3018228915
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.919421576
Short name T188
Test name
Test status
Simulation time 141529733 ps
CPU time 6.26 seconds
Started Aug 16 05:41:43 PM PDT 24
Finished Aug 16 05:41:49 PM PDT 24
Peak memory 247816 kb
Host smart-29ac59d3-c592-45e4-8eda-dea40943aac7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=919421576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.919421576
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.13875475
Short name T772
Test name
Test status
Simulation time 60504285 ps
CPU time 8.67 seconds
Started Aug 16 05:41:19 PM PDT 24
Finished Aug 16 05:41:28 PM PDT 24
Peak memory 251644 kb
Host smart-38f7f41c-2443-491d-9a48-aedc128e298a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13875475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.alert_handler_csr_mem_rw_with_rand_reset.13875475
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1826567536
Short name T720
Test name
Test status
Simulation time 112003416 ps
CPU time 3 seconds
Started Aug 16 05:41:12 PM PDT 24
Finished Aug 16 05:41:15 PM PDT 24
Peak memory 237740 kb
Host smart-c09815b2-ff00-43b0-b765-0860b7e6c532
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1826567536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1826567536
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2352664815
Short name T187
Test name
Test status
Simulation time 2307848698 ps
CPU time 41.58 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:57 PM PDT 24
Peak memory 245116 kb
Host smart-f705c4d2-b5d4-4c4f-829b-45247d5983dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2352664815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2352664815
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.335780427
Short name T143
Test name
Test status
Simulation time 4914989810 ps
CPU time 168.41 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:44:05 PM PDT 24
Peak memory 265632 kb
Host smart-fe6644f9-bd48-4216-b471-44b912b3d66c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=335780427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.335780427
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1118252153
Short name T794
Test name
Test status
Simulation time 150579018 ps
CPU time 10.68 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:27 PM PDT 24
Peak memory 248900 kb
Host smart-d87b0a4f-3dfb-45b7-804f-0b570c3394bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1118252153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1118252153
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1274563239
Short name T774
Test name
Test status
Simulation time 10058658 ps
CPU time 1.58 seconds
Started Aug 16 05:41:51 PM PDT 24
Finished Aug 16 05:41:52 PM PDT 24
Peak memory 236796 kb
Host smart-5e169523-3bf3-4e1e-9513-1ad3187660a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1274563239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1274563239
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3804865745
Short name T767
Test name
Test status
Simulation time 10356978 ps
CPU time 1.68 seconds
Started Aug 16 05:41:41 PM PDT 24
Finished Aug 16 05:41:43 PM PDT 24
Peak memory 237724 kb
Host smart-c0ff2e66-ba98-444a-9ec3-f09f02368259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3804865745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3804865745
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.480233161
Short name T819
Test name
Test status
Simulation time 8540118 ps
CPU time 1.33 seconds
Started Aug 16 05:41:27 PM PDT 24
Finished Aug 16 05:41:28 PM PDT 24
Peak memory 236828 kb
Host smart-5142e2ca-30d2-4b47-879a-a730dea8d829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=480233161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.480233161
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.950726005
Short name T815
Test name
Test status
Simulation time 8012728 ps
CPU time 1.53 seconds
Started Aug 16 05:41:12 PM PDT 24
Finished Aug 16 05:41:14 PM PDT 24
Peak memory 237724 kb
Host smart-aed649cd-e699-4172-a932-c1ffd62174eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=950726005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.950726005
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2489373433
Short name T765
Test name
Test status
Simulation time 8317622 ps
CPU time 1.46 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 235780 kb
Host smart-b0db0867-726b-4e35-a4d5-f78a7c1a6881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2489373433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2489373433
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2020209348
Short name T736
Test name
Test status
Simulation time 8112566 ps
CPU time 1.32 seconds
Started Aug 16 05:41:51 PM PDT 24
Finished Aug 16 05:42:03 PM PDT 24
Peak memory 236876 kb
Host smart-6533602d-559b-4176-b5bc-e0ea9c3f0b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2020209348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2020209348
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1440368436
Short name T766
Test name
Test status
Simulation time 8524676 ps
CPU time 1.52 seconds
Started Aug 16 05:41:44 PM PDT 24
Finished Aug 16 05:41:45 PM PDT 24
Peak memory 236840 kb
Host smart-206a9421-de2c-463b-92d9-ffe835fa5436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1440368436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1440368436
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.765973600
Short name T828
Test name
Test status
Simulation time 15005463 ps
CPU time 1.31 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 237724 kb
Host smart-4007c27b-3d0f-4833-bd6a-81b4dcdf9b06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=765973600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.765973600
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.702885689
Short name T729
Test name
Test status
Simulation time 21070349 ps
CPU time 1.34 seconds
Started Aug 16 05:41:28 PM PDT 24
Finished Aug 16 05:41:29 PM PDT 24
Peak memory 235752 kb
Host smart-306e1cfb-31b7-42fc-b356-8b1e37dd988c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=702885689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.702885689
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.590628807
Short name T750
Test name
Test status
Simulation time 4282936726 ps
CPU time 159.78 seconds
Started Aug 16 05:41:31 PM PDT 24
Finished Aug 16 05:44:11 PM PDT 24
Peak memory 240752 kb
Host smart-8c864379-ad96-47e2-80fb-acafcb0c9b4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=590628807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.590628807
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3007346110
Short name T823
Test name
Test status
Simulation time 3876637893 ps
CPU time 189.95 seconds
Started Aug 16 05:41:21 PM PDT 24
Finished Aug 16 05:44:31 PM PDT 24
Peak memory 236944 kb
Host smart-4ddc5a1e-d07d-4a94-8adb-3879585e00d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3007346110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3007346110
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1599165259
Short name T808
Test name
Test status
Simulation time 1817639940 ps
CPU time 9.29 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:24 PM PDT 24
Peak memory 248908 kb
Host smart-cfdd2f4f-1f9c-44f5-83fd-c4b9a89870af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1599165259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1599165259
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1043869311
Short name T722
Test name
Test status
Simulation time 36460647 ps
CPU time 5.45 seconds
Started Aug 16 05:41:17 PM PDT 24
Finished Aug 16 05:41:23 PM PDT 24
Peak memory 254212 kb
Host smart-626ac242-de8a-48d2-8b34-6658e88e73d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043869311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1043869311
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.74613276
Short name T734
Test name
Test status
Simulation time 362758497 ps
CPU time 7.44 seconds
Started Aug 16 05:41:31 PM PDT 24
Finished Aug 16 05:41:39 PM PDT 24
Peak memory 237784 kb
Host smart-d1c90377-aba6-407c-b091-901c595927e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=74613276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.74613276
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2248105235
Short name T754
Test name
Test status
Simulation time 20970097 ps
CPU time 1.38 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 237004 kb
Host smart-0ad62f54-9343-4849-9fd6-6da106d96a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2248105235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2248105235
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.989109524
Short name T803
Test name
Test status
Simulation time 706891062 ps
CPU time 45.84 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:42:00 PM PDT 24
Peak memory 246076 kb
Host smart-71303d77-d108-4d91-8d73-c753d26229c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=989109524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.989109524
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3207109352
Short name T137
Test name
Test status
Simulation time 32027837608 ps
CPU time 476.35 seconds
Started Aug 16 05:41:26 PM PDT 24
Finished Aug 16 05:49:22 PM PDT 24
Peak memory 265556 kb
Host smart-fbd958b5-59b9-4a48-87fa-0126cdcb3049
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207109352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3207109352
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2527669930
Short name T713
Test name
Test status
Simulation time 3674994046 ps
CPU time 23.93 seconds
Started Aug 16 05:41:27 PM PDT 24
Finished Aug 16 05:41:52 PM PDT 24
Peak memory 248328 kb
Host smart-74b2be87-a9a2-49d2-ba2a-2234c830fd22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2527669930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2527669930
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.170175267
Short name T770
Test name
Test status
Simulation time 21826511 ps
CPU time 1.91 seconds
Started Aug 16 05:41:17 PM PDT 24
Finished Aug 16 05:41:19 PM PDT 24
Peak memory 237724 kb
Host smart-2f540c66-2dbb-4311-929b-d1e98735b418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=170175267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.170175267
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2305946418
Short name T709
Test name
Test status
Simulation time 23231228 ps
CPU time 1.26 seconds
Started Aug 16 05:41:31 PM PDT 24
Finished Aug 16 05:41:32 PM PDT 24
Peak memory 237780 kb
Host smart-021c57eb-43d5-4b0c-94fb-fc1e0e70df93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2305946418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2305946418
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1653764051
Short name T751
Test name
Test status
Simulation time 12428193 ps
CPU time 1.6 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:23 PM PDT 24
Peak memory 236876 kb
Host smart-d456651c-0be8-441a-b8fb-db9672dba181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1653764051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1653764051
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.209893671
Short name T810
Test name
Test status
Simulation time 14763894 ps
CPU time 1.29 seconds
Started Aug 16 05:41:37 PM PDT 24
Finished Aug 16 05:41:39 PM PDT 24
Peak memory 237760 kb
Host smart-c877f794-75d9-410a-9796-bb6006b7d04a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=209893671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.209893671
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.774597308
Short name T710
Test name
Test status
Simulation time 30632787 ps
CPU time 1.29 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 237588 kb
Host smart-9b8e5fd1-74fd-4479-bcab-6e09e0d626d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=774597308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.774597308
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3025649880
Short name T782
Test name
Test status
Simulation time 12846743 ps
CPU time 1.48 seconds
Started Aug 16 05:41:52 PM PDT 24
Finished Aug 16 05:41:53 PM PDT 24
Peak memory 237776 kb
Host smart-464d4108-f354-4094-837c-6b7d94fe0d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3025649880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3025649880
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.619659726
Short name T721
Test name
Test status
Simulation time 14884698 ps
CPU time 1.43 seconds
Started Aug 16 05:41:35 PM PDT 24
Finished Aug 16 05:41:36 PM PDT 24
Peak memory 236860 kb
Host smart-7323f2e1-7f7d-45d6-bfb1-059edc494f52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=619659726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.619659726
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1496768877
Short name T714
Test name
Test status
Simulation time 13329837 ps
CPU time 1.36 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 236804 kb
Host smart-9a69c12d-dcfc-405b-9e1a-9f231ad51f90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1496768877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1496768877
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.376182425
Short name T167
Test name
Test status
Simulation time 19482013 ps
CPU time 1.26 seconds
Started Aug 16 05:41:50 PM PDT 24
Finished Aug 16 05:41:51 PM PDT 24
Peak memory 236888 kb
Host smart-3ae3bfe7-eb55-4001-8739-a3e56222b979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=376182425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.376182425
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2468784382
Short name T731
Test name
Test status
Simulation time 25887479 ps
CPU time 1.52 seconds
Started Aug 16 05:41:58 PM PDT 24
Finished Aug 16 05:41:59 PM PDT 24
Peak memory 237748 kb
Host smart-da519b7c-77cd-4e41-b10f-1588e030b067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2468784382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2468784382
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2109112688
Short name T786
Test name
Test status
Simulation time 596310601 ps
CPU time 73.11 seconds
Started Aug 16 05:41:32 PM PDT 24
Finished Aug 16 05:42:45 PM PDT 24
Peak memory 237888 kb
Host smart-6e8d42d9-b18b-4cf5-8fc7-d1197106325b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2109112688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2109112688
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.243141671
Short name T769
Test name
Test status
Simulation time 23817603609 ps
CPU time 419.26 seconds
Started Aug 16 05:41:47 PM PDT 24
Finished Aug 16 05:48:47 PM PDT 24
Peak memory 237796 kb
Host smart-ef90b779-498c-4ee6-a18f-c66b1050c5b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=243141671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.243141671
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2013230083
Short name T719
Test name
Test status
Simulation time 38873395 ps
CPU time 6.15 seconds
Started Aug 16 05:41:34 PM PDT 24
Finished Aug 16 05:41:40 PM PDT 24
Peak memory 240624 kb
Host smart-9b8fe249-4029-4929-8dc7-0f98140accc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2013230083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2013230083
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2007992995
Short name T788
Test name
Test status
Simulation time 33530666 ps
CPU time 4.92 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:41:15 PM PDT 24
Peak memory 248960 kb
Host smart-68858c11-0c10-492b-a23f-da036811aece
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007992995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2007992995
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2573844433
Short name T347
Test name
Test status
Simulation time 946467736 ps
CPU time 8.82 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:22 PM PDT 24
Peak memory 237656 kb
Host smart-2de8c494-8cc9-4d62-ad1d-e74693fb0d76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2573844433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2573844433
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1202741412
Short name T816
Test name
Test status
Simulation time 26425689 ps
CPU time 1.31 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 237604 kb
Host smart-d9261fb9-3309-402c-8588-186c237172fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1202741412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1202741412
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1286167860
Short name T806
Test name
Test status
Simulation time 358286926 ps
CPU time 10.89 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:26 PM PDT 24
Peak memory 244916 kb
Host smart-3c93ed0d-3a34-4258-be84-ae2cb0e013a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1286167860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1286167860
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3081044935
Short name T144
Test name
Test status
Simulation time 3713551592 ps
CPU time 295.83 seconds
Started Aug 16 05:41:36 PM PDT 24
Finished Aug 16 05:46:32 PM PDT 24
Peak memory 265676 kb
Host smart-0b318407-fe26-439a-b05c-fe8da96f7949
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3081044935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3081044935
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.4235282747
Short name T134
Test name
Test status
Simulation time 60316907183 ps
CPU time 640.36 seconds
Started Aug 16 05:41:18 PM PDT 24
Finished Aug 16 05:52:03 PM PDT 24
Peak memory 265640 kb
Host smart-3aba6784-6403-4be7-a3d8-253b3ff99c59
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235282747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.4235282747
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3409435605
Short name T715
Test name
Test status
Simulation time 1147738549 ps
CPU time 9.81 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:24 PM PDT 24
Peak memory 248944 kb
Host smart-9bf60b6c-91fc-49ff-91ec-2acc3343a9c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3409435605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3409435605
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.80436506
Short name T800
Test name
Test status
Simulation time 7469223 ps
CPU time 1.31 seconds
Started Aug 16 05:41:50 PM PDT 24
Finished Aug 16 05:41:51 PM PDT 24
Peak memory 235864 kb
Host smart-41052a39-268d-4b95-bd96-7765d21fa06f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=80436506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.80436506
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1436322868
Short name T718
Test name
Test status
Simulation time 26816882 ps
CPU time 1.25 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:21 PM PDT 24
Peak memory 236876 kb
Host smart-08f7f004-9b12-4506-a952-d87552998138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1436322868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1436322868
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1891366262
Short name T166
Test name
Test status
Simulation time 12707604 ps
CPU time 1.73 seconds
Started Aug 16 05:41:58 PM PDT 24
Finished Aug 16 05:41:59 PM PDT 24
Peak memory 236836 kb
Host smart-040c083e-b234-4df8-9328-32e3f3ce10d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1891366262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1891366262
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2282156481
Short name T761
Test name
Test status
Simulation time 14943021 ps
CPU time 1.44 seconds
Started Aug 16 05:41:31 PM PDT 24
Finished Aug 16 05:41:33 PM PDT 24
Peak memory 236816 kb
Host smart-b33b75f7-bde3-459c-9e9d-7f854b54ba3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2282156481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2282156481
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2642135672
Short name T244
Test name
Test status
Simulation time 30832039 ps
CPU time 1.25 seconds
Started Aug 16 05:41:29 PM PDT 24
Finished Aug 16 05:41:30 PM PDT 24
Peak memory 235756 kb
Host smart-3d5291ff-ab9c-45a5-90c5-9c5574f48879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2642135672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2642135672
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3953163096
Short name T740
Test name
Test status
Simulation time 11608705 ps
CPU time 1.36 seconds
Started Aug 16 05:42:01 PM PDT 24
Finished Aug 16 05:42:02 PM PDT 24
Peak memory 237684 kb
Host smart-c3938f45-d977-416b-bfc8-e8b2af457beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3953163096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3953163096
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1863791301
Short name T792
Test name
Test status
Simulation time 14739663 ps
CPU time 1.22 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:18 PM PDT 24
Peak memory 237636 kb
Host smart-7b42159d-e9e9-4003-a5c6-10e98cfba3ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1863791301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1863791301
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4036547872
Short name T343
Test name
Test status
Simulation time 6770525 ps
CPU time 1.46 seconds
Started Aug 16 05:41:46 PM PDT 24
Finished Aug 16 05:41:48 PM PDT 24
Peak memory 236740 kb
Host smart-6e7983e3-9419-4801-9633-e3c4ee071211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4036547872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4036547872
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2539134356
Short name T341
Test name
Test status
Simulation time 7903338 ps
CPU time 1.46 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:28 PM PDT 24
Peak memory 237760 kb
Host smart-810a7dfd-39e1-4cc6-8be6-1b6e4b2ec360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2539134356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2539134356
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2288947982
Short name T749
Test name
Test status
Simulation time 11915186 ps
CPU time 1.43 seconds
Started Aug 16 05:41:51 PM PDT 24
Finished Aug 16 05:41:53 PM PDT 24
Peak memory 236764 kb
Host smart-b0b5e849-9e7c-4022-ac53-90452e0cff52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2288947982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2288947982
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.4229568335
Short name T760
Test name
Test status
Simulation time 395676744 ps
CPU time 7.3 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:25 PM PDT 24
Peak memory 240720 kb
Host smart-8d947a01-1f00-410c-a277-1dec665bf335
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229568335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.4229568335
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3376045227
Short name T726
Test name
Test status
Simulation time 24946731 ps
CPU time 3.41 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:20 PM PDT 24
Peak memory 237656 kb
Host smart-eb60ff10-afca-4bd6-abf1-aabe93ad95b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3376045227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3376045227
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3541793106
Short name T818
Test name
Test status
Simulation time 8466337 ps
CPU time 1.43 seconds
Started Aug 16 05:41:18 PM PDT 24
Finished Aug 16 05:41:20 PM PDT 24
Peak memory 237760 kb
Host smart-38c862d3-0c40-4852-bff3-50d70626e17c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3541793106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3541793106
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2337543028
Short name T192
Test name
Test status
Simulation time 597412285 ps
CPU time 34.44 seconds
Started Aug 16 05:41:24 PM PDT 24
Finished Aug 16 05:41:58 PM PDT 24
Peak memory 244904 kb
Host smart-bfebc92d-0dfa-492c-a21a-c2f1f24dfdb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2337543028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2337543028
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1559603725
Short name T142
Test name
Test status
Simulation time 13196644080 ps
CPU time 460.03 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:48:54 PM PDT 24
Peak memory 265536 kb
Host smart-9eb7d871-4327-446b-a679-2971c3a62da3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559603725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1559603725
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2822868396
Short name T242
Test name
Test status
Simulation time 810246580 ps
CPU time 13.91 seconds
Started Aug 16 05:41:40 PM PDT 24
Finished Aug 16 05:41:54 PM PDT 24
Peak memory 248916 kb
Host smart-5cdc29ea-3b0f-4bdd-ba64-d60251d163b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2822868396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2822868396
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3651411787
Short name T346
Test name
Test status
Simulation time 1053981668 ps
CPU time 13.65 seconds
Started Aug 16 05:41:52 PM PDT 24
Finished Aug 16 05:42:05 PM PDT 24
Peak memory 242820 kb
Host smart-bd83c5a9-1f3e-46b0-980f-25d5430700de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651411787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3651411787
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.778763982
Short name T186
Test name
Test status
Simulation time 59965244 ps
CPU time 2.87 seconds
Started Aug 16 05:41:23 PM PDT 24
Finished Aug 16 05:41:26 PM PDT 24
Peak memory 236776 kb
Host smart-48a635a3-966b-459e-b99b-8030869330c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=778763982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.778763982
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3726428654
Short name T732
Test name
Test status
Simulation time 12267116 ps
CPU time 1.56 seconds
Started Aug 16 05:41:12 PM PDT 24
Finished Aug 16 05:41:13 PM PDT 24
Peak memory 237672 kb
Host smart-202dcaeb-f111-473d-bb29-dad5d30869cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3726428654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3726428654
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.4048732626
Short name T773
Test name
Test status
Simulation time 525233044 ps
CPU time 34.06 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:49 PM PDT 24
Peak memory 245940 kb
Host smart-34315302-59bf-41e2-88e7-b3421ae7aa16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4048732626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.4048732626
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3930080351
Short name T146
Test name
Test status
Simulation time 2114935755 ps
CPU time 245.66 seconds
Started Aug 16 05:41:49 PM PDT 24
Finished Aug 16 05:45:55 PM PDT 24
Peak memory 265592 kb
Host smart-3325d908-2e90-4a18-a94f-5313b401f2c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3930080351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3930080351
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1637884705
Short name T130
Test name
Test status
Simulation time 2693793087 ps
CPU time 314.72 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:46:29 PM PDT 24
Peak memory 265628 kb
Host smart-7f4aa01f-c72a-49a6-8ff4-d4192e1f8868
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637884705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1637884705
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3986781851
Short name T708
Test name
Test status
Simulation time 1861726760 ps
CPU time 22.17 seconds
Started Aug 16 05:41:33 PM PDT 24
Finished Aug 16 05:41:55 PM PDT 24
Peak memory 256900 kb
Host smart-14c6871d-de6a-42b2-9581-1f5342567abe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3986781851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3986781851
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2524165319
Short name T181
Test name
Test status
Simulation time 40600047 ps
CPU time 3.3 seconds
Started Aug 16 05:41:27 PM PDT 24
Finished Aug 16 05:41:30 PM PDT 24
Peak memory 236844 kb
Host smart-b6b48d3d-8a7e-49df-8cb9-5a07f5e0d908
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2524165319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2524165319
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1255815544
Short name T793
Test name
Test status
Simulation time 131826779 ps
CPU time 11.34 seconds
Started Aug 16 05:41:39 PM PDT 24
Finished Aug 16 05:41:50 PM PDT 24
Peak memory 256000 kb
Host smart-8d682761-4349-4571-9524-d7da4ae53f3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255815544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1255815544
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3392620006
Short name T743
Test name
Test status
Simulation time 91205466 ps
CPU time 8.34 seconds
Started Aug 16 05:41:49 PM PDT 24
Finished Aug 16 05:41:57 PM PDT 24
Peak memory 237748 kb
Host smart-1508a0c3-79c5-4b17-b44b-9dc319fdb0f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3392620006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3392620006
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1794289235
Short name T777
Test name
Test status
Simulation time 7474813 ps
CPU time 1.4 seconds
Started Aug 16 05:41:34 PM PDT 24
Finished Aug 16 05:41:36 PM PDT 24
Peak memory 237756 kb
Host smart-bd1c43cf-00d9-4f9e-bc28-ee28d794dea2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1794289235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1794289235
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1638892373
Short name T190
Test name
Test status
Simulation time 89588267 ps
CPU time 12.17 seconds
Started Aug 16 05:41:34 PM PDT 24
Finished Aug 16 05:41:46 PM PDT 24
Peak memory 248772 kb
Host smart-12825a25-7ad1-490a-ae4b-09c63e48da27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1638892373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1638892373
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.818916313
Short name T133
Test name
Test status
Simulation time 5433296250 ps
CPU time 302.98 seconds
Started Aug 16 05:41:30 PM PDT 24
Finished Aug 16 05:46:33 PM PDT 24
Peak memory 265684 kb
Host smart-dc40fe47-d6de-4cb8-82ff-7a831dca93a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=818916313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.818916313
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.711239304
Short name T149
Test name
Test status
Simulation time 19210670889 ps
CPU time 313.48 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:46:27 PM PDT 24
Peak memory 269792 kb
Host smart-28b3a3f1-ec72-4114-9028-0ab03d3df494
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711239304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.711239304
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3793029783
Short name T757
Test name
Test status
Simulation time 921806439 ps
CPU time 31.42 seconds
Started Aug 16 05:41:18 PM PDT 24
Finished Aug 16 05:41:49 PM PDT 24
Peak memory 249008 kb
Host smart-3fc93e86-9d91-498f-bbff-de3a10cf78d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3793029783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3793029783
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2765161804
Short name T824
Test name
Test status
Simulation time 449639550 ps
CPU time 31.38 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:47 PM PDT 24
Peak memory 248884 kb
Host smart-2e675300-9fdb-4e99-87d8-aa2cab647a48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2765161804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2765161804
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3804137704
Short name T742
Test name
Test status
Simulation time 74368819 ps
CPU time 6.76 seconds
Started Aug 16 05:41:47 PM PDT 24
Finished Aug 16 05:41:54 PM PDT 24
Peak memory 248888 kb
Host smart-f5aee067-77ef-4df7-97ec-8c8b61bdc597
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804137704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3804137704
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1495476687
Short name T785
Test name
Test status
Simulation time 445886151 ps
CPU time 8.36 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:25 PM PDT 24
Peak memory 236844 kb
Host smart-0982d449-d28a-4e00-b37f-d273dad9a9a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1495476687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1495476687
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1535490728
Short name T764
Test name
Test status
Simulation time 58048341 ps
CPU time 1.39 seconds
Started Aug 16 05:41:20 PM PDT 24
Finished Aug 16 05:41:21 PM PDT 24
Peak memory 236772 kb
Host smart-238f924c-9ead-4358-82e9-35e3fefbfa6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1535490728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1535490728
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2774403236
Short name T813
Test name
Test status
Simulation time 729073503 ps
CPU time 45.26 seconds
Started Aug 16 05:41:32 PM PDT 24
Finished Aug 16 05:42:17 PM PDT 24
Peak memory 245972 kb
Host smart-28ce5b2d-0776-4653-8492-3ddb1c73e511
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2774403236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2774403236
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1529712114
Short name T778
Test name
Test status
Simulation time 453484028 ps
CPU time 16.16 seconds
Started Aug 16 05:41:55 PM PDT 24
Finished Aug 16 05:42:11 PM PDT 24
Peak memory 247148 kb
Host smart-6db20512-f0a8-490e-8992-cfbf5b9be207
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1529712114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1529712114
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.730035275
Short name T748
Test name
Test status
Simulation time 399224861 ps
CPU time 7.68 seconds
Started Aug 16 05:41:18 PM PDT 24
Finished Aug 16 05:41:26 PM PDT 24
Peak memory 241168 kb
Host smart-5a65f7f3-3073-4886-9b72-6bcfde779975
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730035275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.730035275
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3598979079
Short name T191
Test name
Test status
Simulation time 592298608 ps
CPU time 6.49 seconds
Started Aug 16 05:41:52 PM PDT 24
Finished Aug 16 05:41:59 PM PDT 24
Peak memory 237564 kb
Host smart-8fe62831-366d-4e60-b828-492f57c581eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3598979079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3598979079
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4070642080
Short name T753
Test name
Test status
Simulation time 6575951 ps
CPU time 1.46 seconds
Started Aug 16 05:41:47 PM PDT 24
Finished Aug 16 05:41:49 PM PDT 24
Peak memory 237776 kb
Host smart-cbf63a65-e5b3-4d22-bbd7-f88765785949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4070642080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.4070642080
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2309695569
Short name T741
Test name
Test status
Simulation time 3068900231 ps
CPU time 47.18 seconds
Started Aug 16 05:41:39 PM PDT 24
Finished Aug 16 05:42:26 PM PDT 24
Peak memory 246020 kb
Host smart-30aac647-2c1a-42b5-876d-1f19b898f627
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2309695569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2309695569
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.989200671
Short name T136
Test name
Test status
Simulation time 7614888903 ps
CPU time 133.6 seconds
Started Aug 16 05:41:55 PM PDT 24
Finished Aug 16 05:44:09 PM PDT 24
Peak memory 266796 kb
Host smart-1de7c9cf-1f02-4f1e-b753-0e16fe3b2b4a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=989200671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.989200671
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.858006462
Short name T155
Test name
Test status
Simulation time 11888892873 ps
CPU time 524.14 seconds
Started Aug 16 05:41:20 PM PDT 24
Finished Aug 16 05:50:04 PM PDT 24
Peak memory 265660 kb
Host smart-6eaadc15-edd2-4ca2-b68b-2016e0d52bff
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858006462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.858006462
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.447032821
Short name T790
Test name
Test status
Simulation time 104002559 ps
CPU time 7.72 seconds
Started Aug 16 05:41:41 PM PDT 24
Finished Aug 16 05:41:49 PM PDT 24
Peak memory 249040 kb
Host smart-4b4b83aa-8de8-4031-85e0-bee8fa60f195
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=447032821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.447032821
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3559252764
Short name T600
Test name
Test status
Simulation time 25297631258 ps
CPU time 1157.13 seconds
Started Aug 16 04:36:25 PM PDT 24
Finished Aug 16 04:55:42 PM PDT 24
Peak memory 281544 kb
Host smart-dd65addc-9f0b-4e53-b7aa-81906c4242b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559252764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3559252764
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3238577037
Short name T440
Test name
Test status
Simulation time 1508749450 ps
CPU time 18.33 seconds
Started Aug 16 04:36:13 PM PDT 24
Finished Aug 16 04:36:32 PM PDT 24
Peak memory 248612 kb
Host smart-0a47664c-7f63-44c5-b200-ad073602844e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3238577037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3238577037
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2017166184
Short name T467
Test name
Test status
Simulation time 1652887644 ps
CPU time 14.06 seconds
Started Aug 16 04:36:37 PM PDT 24
Finished Aug 16 04:36:51 PM PDT 24
Peak memory 256472 kb
Host smart-4c36ef26-93b5-42f9-a94e-f4df71f5ba51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20171
66184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2017166184
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2842226625
Short name T328
Test name
Test status
Simulation time 21531085413 ps
CPU time 1280.69 seconds
Started Aug 16 04:36:24 PM PDT 24
Finished Aug 16 04:57:45 PM PDT 24
Peak memory 289692 kb
Host smart-dea8e0d0-5e56-49f8-981c-585cd92bcf39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842226625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2842226625
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2860300571
Short name T540
Test name
Test status
Simulation time 79328487557 ps
CPU time 2484.4 seconds
Started Aug 16 04:36:10 PM PDT 24
Finished Aug 16 05:17:34 PM PDT 24
Peak memory 283924 kb
Host smart-dad60bc2-7a58-4e04-bbc3-47e0b44d3306
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860300571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2860300571
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3454719959
Short name T598
Test name
Test status
Simulation time 24413237118 ps
CPU time 500.02 seconds
Started Aug 16 04:36:43 PM PDT 24
Finished Aug 16 04:45:03 PM PDT 24
Peak memory 248684 kb
Host smart-8d332c26-5d3f-4d16-a1ba-19ab8f3bd076
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454719959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3454719959
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.346026408
Short name T382
Test name
Test status
Simulation time 864010580 ps
CPU time 42.45 seconds
Started Aug 16 04:36:36 PM PDT 24
Finished Aug 16 04:37:19 PM PDT 24
Peak memory 256060 kb
Host smart-582f4891-7457-48cf-bdc1-761efb49e15c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34602
6408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.346026408
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3093469771
Short name T474
Test name
Test status
Simulation time 520518584 ps
CPU time 34.6 seconds
Started Aug 16 04:36:08 PM PDT 24
Finished Aug 16 04:36:43 PM PDT 24
Peak memory 256840 kb
Host smart-078b801b-0a94-4660-bb1e-620ee3f1a108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30934
69771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3093469771
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2252430526
Short name T32
Test name
Test status
Simulation time 1146482578 ps
CPU time 10.9 seconds
Started Aug 16 04:36:32 PM PDT 24
Finished Aug 16 04:36:43 PM PDT 24
Peak memory 270428 kb
Host smart-c2f8da5c-345b-49ec-8727-57dad90080c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2252430526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2252430526
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.600002229
Short name T430
Test name
Test status
Simulation time 2861230735 ps
CPU time 44.24 seconds
Started Aug 16 04:36:16 PM PDT 24
Finished Aug 16 04:37:00 PM PDT 24
Peak memory 256904 kb
Host smart-784aa365-8f03-4b70-9315-b014213b7f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60000
2229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.600002229
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3925547570
Short name T650
Test name
Test status
Simulation time 62439705066 ps
CPU time 1391.53 seconds
Started Aug 16 04:36:29 PM PDT 24
Finished Aug 16 04:59:40 PM PDT 24
Peak memory 289388 kb
Host smart-2b226b1c-a4fb-4cee-b52a-c9a254371e88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925547570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3925547570
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3119092757
Short name T616
Test name
Test status
Simulation time 1191844003 ps
CPU time 25.76 seconds
Started Aug 16 04:36:31 PM PDT 24
Finished Aug 16 04:36:57 PM PDT 24
Peak memory 248544 kb
Host smart-1fec3712-2b69-411c-b0cc-78630e9074d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3119092757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3119092757
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3127336934
Short name T388
Test name
Test status
Simulation time 5454736743 ps
CPU time 153.27 seconds
Started Aug 16 04:36:51 PM PDT 24
Finished Aug 16 04:39:24 PM PDT 24
Peak memory 256264 kb
Host smart-44c7f524-6ce0-4726-b2de-794928228307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31273
36934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3127336934
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1495630570
Short name T704
Test name
Test status
Simulation time 4434507725 ps
CPU time 62.75 seconds
Started Aug 16 04:36:23 PM PDT 24
Finished Aug 16 04:37:25 PM PDT 24
Peak memory 248344 kb
Host smart-e6c94ec1-2b26-4e17-83b5-973fc454d7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14956
30570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1495630570
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3473640769
Short name T336
Test name
Test status
Simulation time 112936507960 ps
CPU time 1875.39 seconds
Started Aug 16 04:36:43 PM PDT 24
Finished Aug 16 05:07:59 PM PDT 24
Peak memory 282624 kb
Host smart-ca7d9b5e-9752-48dd-8344-7a67535fb527
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473640769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3473640769
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3509098122
Short name T628
Test name
Test status
Simulation time 12944369553 ps
CPU time 1166.08 seconds
Started Aug 16 04:36:50 PM PDT 24
Finished Aug 16 04:56:16 PM PDT 24
Peak memory 289140 kb
Host smart-08e0f297-cd4d-4e04-804b-e83595089e9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509098122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3509098122
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.861217095
Short name T439
Test name
Test status
Simulation time 2181599893 ps
CPU time 84.57 seconds
Started Aug 16 04:36:14 PM PDT 24
Finished Aug 16 04:37:39 PM PDT 24
Peak memory 248464 kb
Host smart-e60846e1-513f-423f-8883-52136eaf722c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861217095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.861217095
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1242875503
Short name T383
Test name
Test status
Simulation time 3734176633 ps
CPU time 54.75 seconds
Started Aug 16 04:36:33 PM PDT 24
Finished Aug 16 04:37:28 PM PDT 24
Peak memory 256312 kb
Host smart-74a17d95-782c-4bdd-b857-e76a0c193ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12428
75503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1242875503
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1337315629
Short name T604
Test name
Test status
Simulation time 125904382 ps
CPU time 10 seconds
Started Aug 16 04:36:22 PM PDT 24
Finished Aug 16 04:36:33 PM PDT 24
Peak memory 255364 kb
Host smart-ef6eed44-1751-45cf-a91a-4a3ef36c9615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13373
15629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1337315629
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2269027092
Short name T296
Test name
Test status
Simulation time 3257503236 ps
CPU time 25.63 seconds
Started Aug 16 04:36:34 PM PDT 24
Finished Aug 16 04:36:59 PM PDT 24
Peak memory 255668 kb
Host smart-0eaba77e-ba95-40f8-9ec1-90a68984ba2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22690
27092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2269027092
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2496863201
Short name T533
Test name
Test status
Simulation time 169682188 ps
CPU time 11.68 seconds
Started Aug 16 04:36:13 PM PDT 24
Finished Aug 16 04:36:25 PM PDT 24
Peak memory 254648 kb
Host smart-ab000dc1-ed5a-4af7-b103-6e3dac2bc2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24968
63201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2496863201
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2174603261
Short name T499
Test name
Test status
Simulation time 29226427288 ps
CPU time 1812.47 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 05:07:18 PM PDT 24
Peak memory 282932 kb
Host smart-eb313227-2724-43de-a440-f473fc7a70eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174603261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2174603261
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1915048230
Short name T494
Test name
Test status
Simulation time 112064329 ps
CPU time 7.63 seconds
Started Aug 16 04:36:50 PM PDT 24
Finished Aug 16 04:36:58 PM PDT 24
Peak memory 248628 kb
Host smart-48f2781b-5026-4e37-a0b3-c318a51530c7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1915048230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1915048230
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.281203640
Short name T267
Test name
Test status
Simulation time 4212429789 ps
CPU time 210.46 seconds
Started Aug 16 04:36:57 PM PDT 24
Finished Aug 16 04:40:28 PM PDT 24
Peak memory 250860 kb
Host smart-b8b3e72d-6c37-4fd1-87db-3df92045f661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28120
3640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.281203640
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3234882626
Short name T281
Test name
Test status
Simulation time 2466967224 ps
CPU time 33.19 seconds
Started Aug 16 04:36:57 PM PDT 24
Finished Aug 16 04:37:30 PM PDT 24
Peak memory 256848 kb
Host smart-b54f3ebf-06af-4b0a-a19b-229ffc8ea5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32348
82626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3234882626
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1772172379
Short name T331
Test name
Test status
Simulation time 177641837061 ps
CPU time 2524.15 seconds
Started Aug 16 04:37:02 PM PDT 24
Finished Aug 16 05:19:07 PM PDT 24
Peak memory 289048 kb
Host smart-73e19dcd-0b4a-4029-a43e-81aec8baff89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772172379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1772172379
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1578622456
Short name T667
Test name
Test status
Simulation time 40329155274 ps
CPU time 2486.02 seconds
Started Aug 16 04:36:48 PM PDT 24
Finished Aug 16 05:18:15 PM PDT 24
Peak memory 289476 kb
Host smart-41b62b6f-6131-47f9-ae9a-ff9511602e28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578622456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1578622456
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.273058821
Short name T26
Test name
Test status
Simulation time 166166973 ps
CPU time 7.71 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:37:03 PM PDT 24
Peak memory 248712 kb
Host smart-2edba2a6-0f4b-46a0-b13c-ed3e3af3d19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27305
8821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.273058821
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2294993242
Short name T268
Test name
Test status
Simulation time 714454271 ps
CPU time 16.83 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:37:11 PM PDT 24
Peak memory 248388 kb
Host smart-4e4785d0-57db-41a3-80ba-85b8f846668c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22949
93242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2294993242
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.358560927
Short name T292
Test name
Test status
Simulation time 1094888025 ps
CPU time 20.03 seconds
Started Aug 16 04:36:57 PM PDT 24
Finished Aug 16 04:37:18 PM PDT 24
Peak memory 248244 kb
Host smart-f3cfb786-eefd-4452-ae10-8eeedd48e449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35856
0927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.358560927
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3059483835
Short name T398
Test name
Test status
Simulation time 5194045525 ps
CPU time 39.88 seconds
Started Aug 16 04:36:57 PM PDT 24
Finished Aug 16 04:37:37 PM PDT 24
Peak memory 256916 kb
Host smart-8995a2f9-7fd9-45ee-8e14-ec63944e5f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30594
83835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3059483835
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2311154841
Short name T81
Test name
Test status
Simulation time 133783047872 ps
CPU time 2033.84 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 05:10:50 PM PDT 24
Peak memory 282316 kb
Host smart-9a1ecd39-8fef-4a5d-aabd-e48471c12d58
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311154841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2311154841
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1583919442
Short name T184
Test name
Test status
Simulation time 8452622122 ps
CPU time 156.65 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:39:32 PM PDT 24
Peak memory 265244 kb
Host smart-52c34de0-be78-49e4-9d21-a1a25c23c1f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583919442 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1583919442
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2251287468
Short name T204
Test name
Test status
Simulation time 374524585 ps
CPU time 3.18 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 04:37:14 PM PDT 24
Peak memory 248872 kb
Host smart-599289c5-9d62-4dcc-ae9e-6d7629a9cea7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2251287468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2251287468
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.473099896
Short name T225
Test name
Test status
Simulation time 34812775546 ps
CPU time 987.07 seconds
Started Aug 16 04:36:52 PM PDT 24
Finished Aug 16 04:53:20 PM PDT 24
Peak memory 282876 kb
Host smart-9311082f-6d85-4c84-832a-883905b5bf96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473099896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.473099896
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.40492021
Short name T214
Test name
Test status
Simulation time 281876481 ps
CPU time 14.51 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:37:09 PM PDT 24
Peak memory 248764 kb
Host smart-118277b9-76bc-4654-b57a-3f979c3e30b9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=40492021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.40492021
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3257189542
Short name T456
Test name
Test status
Simulation time 293954028 ps
CPU time 22.56 seconds
Started Aug 16 04:36:45 PM PDT 24
Finished Aug 16 04:37:08 PM PDT 24
Peak memory 256132 kb
Host smart-4e983e20-cd34-4222-b340-ca85a932cc52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32571
89542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3257189542
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2685810793
Short name T480
Test name
Test status
Simulation time 97396569 ps
CPU time 10.19 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:37:10 PM PDT 24
Peak memory 255000 kb
Host smart-c0bd5887-04bb-4326-bd63-7fed402ed1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26858
10793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2685810793
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2594772760
Short name T535
Test name
Test status
Simulation time 283200248868 ps
CPU time 1430.23 seconds
Started Aug 16 04:37:00 PM PDT 24
Finished Aug 16 05:00:51 PM PDT 24
Peak memory 270184 kb
Host smart-e35bb979-ec2a-4f6f-b00b-f5e911537387
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594772760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2594772760
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.841464730
Short name T566
Test name
Test status
Simulation time 208458358 ps
CPU time 17.04 seconds
Started Aug 16 04:36:52 PM PDT 24
Finished Aug 16 04:37:09 PM PDT 24
Peak memory 248724 kb
Host smart-7978f4ec-d583-492c-bb30-fc9268137eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84146
4730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.841464730
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2251145722
Short name T12
Test name
Test status
Simulation time 5096990707 ps
CPU time 71.75 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:38:16 PM PDT 24
Peak memory 256108 kb
Host smart-f2f7c6bd-1ddd-41a8-aa17-7a2b75e97f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22511
45722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2251145722
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1292428162
Short name T230
Test name
Test status
Simulation time 754117875 ps
CPU time 50.89 seconds
Started Aug 16 04:36:51 PM PDT 24
Finished Aug 16 04:37:43 PM PDT 24
Peak memory 256356 kb
Host smart-da33e7bb-da75-4dac-8acc-25b48c051089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12924
28162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1292428162
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.306899187
Short name T473
Test name
Test status
Simulation time 2150378983 ps
CPU time 59.28 seconds
Started Aug 16 04:36:48 PM PDT 24
Finished Aug 16 04:37:47 PM PDT 24
Peak memory 256904 kb
Host smart-46674d78-7728-4edd-bbfa-36919929dc59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30689
9187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.306899187
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3370640169
Short name T23
Test name
Test status
Simulation time 8314779675 ps
CPU time 240.93 seconds
Started Aug 16 04:36:56 PM PDT 24
Finished Aug 16 04:40:57 PM PDT 24
Peak memory 267616 kb
Host smart-bfaaadd4-3980-4ad1-9560-46f21bfb2fd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370640169 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3370640169
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2031233901
Short name T200
Test name
Test status
Simulation time 99508294 ps
CPU time 2.98 seconds
Started Aug 16 04:36:56 PM PDT 24
Finished Aug 16 04:36:59 PM PDT 24
Peak memory 248824 kb
Host smart-ec0d93c6-4014-401b-b4e5-90aa1df01781
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2031233901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2031233901
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3035472385
Short name T115
Test name
Test status
Simulation time 77734913539 ps
CPU time 2095.79 seconds
Started Aug 16 04:37:09 PM PDT 24
Finished Aug 16 05:12:05 PM PDT 24
Peak memory 273224 kb
Host smart-ac6a3095-1c2d-473c-bd90-ae854b423b6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035472385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3035472385
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2986534796
Short name T609
Test name
Test status
Simulation time 602798039 ps
CPU time 9.41 seconds
Started Aug 16 04:36:51 PM PDT 24
Finished Aug 16 04:37:00 PM PDT 24
Peak memory 248620 kb
Host smart-d725dead-ad2e-4b94-b869-240d5de62247
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2986534796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2986534796
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.283349916
Short name T614
Test name
Test status
Simulation time 6969998666 ps
CPU time 172.45 seconds
Started Aug 16 04:36:53 PM PDT 24
Finished Aug 16 04:39:46 PM PDT 24
Peak memory 257048 kb
Host smart-2603ff47-2c62-4ba8-95d4-58c9f55f425d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28334
9916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.283349916
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2352920906
Short name T282
Test name
Test status
Simulation time 710150299 ps
CPU time 10.7 seconds
Started Aug 16 04:36:57 PM PDT 24
Finished Aug 16 04:37:08 PM PDT 24
Peak memory 254820 kb
Host smart-8b5925a2-e7a9-49ae-8fd6-fc87caf66c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23529
20906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2352920906
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2442932628
Short name T258
Test name
Test status
Simulation time 82823553173 ps
CPU time 1344.98 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:59:19 PM PDT 24
Peak memory 281536 kb
Host smart-15f289dc-c47f-477a-a483-24ca657cacd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442932628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2442932628
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.342517019
Short name T475
Test name
Test status
Simulation time 3027302422 ps
CPU time 43.57 seconds
Started Aug 16 04:36:57 PM PDT 24
Finished Aug 16 04:37:41 PM PDT 24
Peak memory 256936 kb
Host smart-9c0e3ec9-9388-4492-81c4-138ab7ab8533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34251
7019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.342517019
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.991903860
Short name T423
Test name
Test status
Simulation time 372434764 ps
CPU time 27.83 seconds
Started Aug 16 04:37:13 PM PDT 24
Finished Aug 16 04:37:46 PM PDT 24
Peak memory 248328 kb
Host smart-00878bb7-8294-4447-9cb8-ff4656c8ba90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99190
3860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.991903860
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.4115310092
Short name T699
Test name
Test status
Simulation time 93237523 ps
CPU time 5.8 seconds
Started Aug 16 04:36:52 PM PDT 24
Finished Aug 16 04:36:58 PM PDT 24
Peak memory 254684 kb
Host smart-17e02942-f427-4a61-a7f3-c63f6f1c5288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41153
10092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.4115310092
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1592105524
Short name T656
Test name
Test status
Simulation time 5358102786 ps
CPU time 45.46 seconds
Started Aug 16 04:36:48 PM PDT 24
Finished Aug 16 04:37:34 PM PDT 24
Peak memory 256892 kb
Host smart-2791a80f-e628-4939-a837-e91a15fbfa6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15921
05524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1592105524
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2885254062
Short name T621
Test name
Test status
Simulation time 4622651733 ps
CPU time 133.61 seconds
Started Aug 16 04:36:42 PM PDT 24
Finished Aug 16 04:38:56 PM PDT 24
Peak memory 251908 kb
Host smart-67670b5e-5ad6-4ca5-8d83-61d9be8e06ab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885254062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2885254062
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.4055536232
Short name T207
Test name
Test status
Simulation time 163925100 ps
CPU time 3.3 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:37:08 PM PDT 24
Peak memory 248744 kb
Host smart-aa87784f-f32b-45d0-ad0d-7cfd9a989c71
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4055536232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.4055536232
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3445679339
Short name T689
Test name
Test status
Simulation time 38077743665 ps
CPU time 1091.61 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:55:16 PM PDT 24
Peak memory 289668 kb
Host smart-62089aed-5c10-4fd9-9fa9-fa52d2dc8d10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445679339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3445679339
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3811002099
Short name T427
Test name
Test status
Simulation time 738626465 ps
CPU time 10.57 seconds
Started Aug 16 04:36:50 PM PDT 24
Finished Aug 16 04:37:01 PM PDT 24
Peak memory 248628 kb
Host smart-61507267-be7f-41ff-8ab1-eef53c7a2849
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3811002099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3811002099
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2661065840
Short name T584
Test name
Test status
Simulation time 733171872 ps
CPU time 42.57 seconds
Started Aug 16 04:36:58 PM PDT 24
Finished Aug 16 04:37:41 PM PDT 24
Peak memory 256384 kb
Host smart-e3591ae2-022b-4ebe-ab2d-df02e9095659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26610
65840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2661065840
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1422960805
Short name T618
Test name
Test status
Simulation time 823033518 ps
CPU time 26.97 seconds
Started Aug 16 04:36:58 PM PDT 24
Finished Aug 16 04:37:25 PM PDT 24
Peak memory 248736 kb
Host smart-5ee38f82-1153-43d4-ba64-ca967b628518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14229
60805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1422960805
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.754058160
Short name T117
Test name
Test status
Simulation time 97444378682 ps
CPU time 644.61 seconds
Started Aug 16 04:37:02 PM PDT 24
Finished Aug 16 04:47:47 PM PDT 24
Peak memory 273296 kb
Host smart-acf2f210-1c98-4440-b738-646322724f27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754058160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.754058160
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2230755033
Short name T470
Test name
Test status
Simulation time 1676920236 ps
CPU time 31.16 seconds
Started Aug 16 04:36:50 PM PDT 24
Finished Aug 16 04:37:21 PM PDT 24
Peak memory 255944 kb
Host smart-aca6eb12-56af-466c-96c5-6cee4e5f9fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22307
55033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2230755033
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2181209815
Short name T544
Test name
Test status
Simulation time 70565802 ps
CPU time 6.82 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:37:03 PM PDT 24
Peak memory 247968 kb
Host smart-ddf799ec-4726-4659-847f-59b0172b3a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21812
09815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2181209815
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.952538329
Short name T83
Test name
Test status
Simulation time 235482658 ps
CPU time 23.8 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:37:19 PM PDT 24
Peak memory 256132 kb
Host smart-167206c9-90ee-4e6e-bdde-9fb8f01bba8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95253
8329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.952538329
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2793184309
Short name T697
Test name
Test status
Simulation time 4191438545 ps
CPU time 27.63 seconds
Started Aug 16 04:37:20 PM PDT 24
Finished Aug 16 04:37:47 PM PDT 24
Peak memory 256724 kb
Host smart-f8126a19-746c-4837-ada4-a79f7ecdb1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27931
84309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2793184309
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.4065280904
Short name T249
Test name
Test status
Simulation time 4528336322 ps
CPU time 261.29 seconds
Started Aug 16 04:37:11 PM PDT 24
Finished Aug 16 04:41:33 PM PDT 24
Peak memory 267256 kb
Host smart-1b9aaa3e-2cb6-456e-a061-4e4f5a2925dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065280904 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.4065280904
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1064500603
Short name T197
Test name
Test status
Simulation time 52704335 ps
CPU time 2.23 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:36:57 PM PDT 24
Peak memory 248960 kb
Host smart-7e4d3a97-40c4-48a7-b5c3-a624819bfa64
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1064500603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1064500603
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3080134828
Short name T458
Test name
Test status
Simulation time 5244824066 ps
CPU time 577.96 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:46:34 PM PDT 24
Peak memory 272312 kb
Host smart-b12b5569-ae3c-47f9-af4e-8544948a8cce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080134828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3080134828
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3365281076
Short name T434
Test name
Test status
Simulation time 695980570 ps
CPU time 10.8 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:37:06 PM PDT 24
Peak memory 248752 kb
Host smart-a9a04f9f-d571-476c-874a-420073452dcc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3365281076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3365281076
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3966644241
Short name T678
Test name
Test status
Simulation time 16217032 ps
CPU time 2.69 seconds
Started Aug 16 04:36:57 PM PDT 24
Finished Aug 16 04:37:00 PM PDT 24
Peak memory 239716 kb
Host smart-c97053c7-8c3b-410b-be68-93c7d437dc4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39666
44241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3966644241
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.921268333
Short name T577
Test name
Test status
Simulation time 518013541 ps
CPU time 28.57 seconds
Started Aug 16 04:36:53 PM PDT 24
Finished Aug 16 04:37:22 PM PDT 24
Peak memory 256096 kb
Host smart-f1b2896e-fefd-4df4-8cca-6c2c7ab276e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92126
8333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.921268333
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.443574826
Short name T2
Test name
Test status
Simulation time 15840965781 ps
CPU time 1316.83 seconds
Started Aug 16 04:36:56 PM PDT 24
Finished Aug 16 04:58:54 PM PDT 24
Peak memory 284308 kb
Host smart-1d683338-f907-41bc-96a0-9098540d9ed9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443574826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.443574826
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3877386795
Short name T220
Test name
Test status
Simulation time 42392035452 ps
CPU time 2727.58 seconds
Started Aug 16 04:37:07 PM PDT 24
Finished Aug 16 05:22:35 PM PDT 24
Peak memory 289124 kb
Host smart-cb8a2f2d-a390-4f8c-9838-9540ae5ac0aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877386795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3877386795
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2071295217
Short name T61
Test name
Test status
Simulation time 207627784 ps
CPU time 11.42 seconds
Started Aug 16 04:36:57 PM PDT 24
Finished Aug 16 04:37:09 PM PDT 24
Peak memory 248200 kb
Host smart-2d00e74a-ffc1-4521-aace-e9ab3040ef5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20712
95217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2071295217
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.386741240
Short name T365
Test name
Test status
Simulation time 176973795 ps
CPU time 17.21 seconds
Started Aug 16 04:37:06 PM PDT 24
Finished Aug 16 04:37:23 PM PDT 24
Peak memory 256852 kb
Host smart-f2dd0aa3-75db-468e-a7f0-4ef6c4b68d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38674
1240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.386741240
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1939317076
Short name T110
Test name
Test status
Simulation time 40082287839 ps
CPU time 1251.86 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:57:47 PM PDT 24
Peak memory 273176 kb
Host smart-301ba22d-ccec-4240-9d4a-8d30a7d2005b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939317076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1939317076
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.902409844
Short name T107
Test name
Test status
Simulation time 18906490402 ps
CPU time 480.43 seconds
Started Aug 16 04:36:53 PM PDT 24
Finished Aug 16 04:44:54 PM PDT 24
Peak memory 272160 kb
Host smart-355c7728-0609-4c11-9ea7-67dc12bff085
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902409844 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.902409844
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.4103327541
Short name T211
Test name
Test status
Simulation time 44224860 ps
CPU time 3.25 seconds
Started Aug 16 04:37:15 PM PDT 24
Finished Aug 16 04:37:19 PM PDT 24
Peak memory 248760 kb
Host smart-de04ebdc-138f-4fc1-b787-31cd239ead47
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4103327541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.4103327541
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.124736697
Short name T385
Test name
Test status
Simulation time 810875541 ps
CPU time 20.87 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:37:17 PM PDT 24
Peak memory 248652 kb
Host smart-decc72d4-99f9-42a0-9bfa-82c212093df6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=124736697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.124736697
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2475662200
Short name T418
Test name
Test status
Simulation time 121047888 ps
CPU time 7.31 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:37:12 PM PDT 24
Peak memory 251156 kb
Host smart-0e99feab-7f95-44ad-b953-af58422cc26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24756
62200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2475662200
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2278021246
Short name T543
Test name
Test status
Simulation time 172169070 ps
CPU time 13.66 seconds
Started Aug 16 04:37:35 PM PDT 24
Finished Aug 16 04:37:48 PM PDT 24
Peak memory 256660 kb
Host smart-1ed5f973-ba65-41d5-89eb-3708e4dc3d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22780
21246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2278021246
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1609235420
Short name T518
Test name
Test status
Simulation time 30617592442 ps
CPU time 1531.33 seconds
Started Aug 16 04:36:56 PM PDT 24
Finished Aug 16 05:02:28 PM PDT 24
Peak memory 288548 kb
Host smart-7ce13b3c-a7ec-4e27-9044-1a3f82726de4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609235420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1609235420
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2798167105
Short name T664
Test name
Test status
Simulation time 8182081324 ps
CPU time 743.22 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:49:18 PM PDT 24
Peak memory 269232 kb
Host smart-6e3037ab-e640-4f4d-8285-24808f6a9c0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798167105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2798167105
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.473622528
Short name T552
Test name
Test status
Simulation time 15322242636 ps
CPU time 301.44 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:42:06 PM PDT 24
Peak memory 248784 kb
Host smart-cad4a3d1-db3f-46f1-b0ad-786e9a92ca16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473622528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.473622528
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2842810108
Short name T483
Test name
Test status
Simulation time 3107243046 ps
CPU time 56.45 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:38:01 PM PDT 24
Peak memory 255984 kb
Host smart-b1703ad1-aced-4a67-8d3c-7ee75551efec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28428
10108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2842810108
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2890685461
Short name T43
Test name
Test status
Simulation time 1245401621 ps
CPU time 21.84 seconds
Started Aug 16 04:37:06 PM PDT 24
Finished Aug 16 04:37:28 PM PDT 24
Peak memory 248248 kb
Host smart-7a29f1c0-6061-4ffc-8386-2e433df2f573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28906
85461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2890685461
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2937198978
Short name T419
Test name
Test status
Simulation time 464513598 ps
CPU time 23.61 seconds
Started Aug 16 04:37:31 PM PDT 24
Finished Aug 16 04:37:55 PM PDT 24
Peak memory 248628 kb
Host smart-6d1af37e-d791-4f9d-8001-e765c30785b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29371
98978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2937198978
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1335950405
Short name T462
Test name
Test status
Simulation time 310187073 ps
CPU time 12.3 seconds
Started Aug 16 04:37:03 PM PDT 24
Finished Aug 16 04:37:26 PM PDT 24
Peak memory 255352 kb
Host smart-2a1fd120-ace8-4761-b999-dfb79a0f9be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13359
50405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1335950405
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1917520815
Short name T201
Test name
Test status
Simulation time 31692186 ps
CPU time 3.59 seconds
Started Aug 16 04:37:24 PM PDT 24
Finished Aug 16 04:37:27 PM PDT 24
Peak memory 248696 kb
Host smart-90e9e597-5864-4267-a5de-29112e68a290
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1917520815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1917520815
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2411183349
Short name T432
Test name
Test status
Simulation time 131932286892 ps
CPU time 2468.6 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 05:18:04 PM PDT 24
Peak memory 289492 kb
Host smart-b735daf2-19d9-403e-ab6a-525f97b206e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411183349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2411183349
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3321739748
Short name T370
Test name
Test status
Simulation time 2686968986 ps
CPU time 60.9 seconds
Started Aug 16 04:37:32 PM PDT 24
Finished Aug 16 04:38:33 PM PDT 24
Peak memory 248848 kb
Host smart-a2670556-b5bd-4077-af18-dc25cdc0b7d4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3321739748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3321739748
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.4250687725
Short name T446
Test name
Test status
Simulation time 1680981188 ps
CPU time 124.07 seconds
Started Aug 16 04:37:09 PM PDT 24
Finished Aug 16 04:39:14 PM PDT 24
Peak memory 256428 kb
Host smart-5aa9d944-e9af-4213-833f-e68c614ad2e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42506
87725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.4250687725
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.164797763
Short name T422
Test name
Test status
Simulation time 630559377 ps
CPU time 27.44 seconds
Started Aug 16 04:37:17 PM PDT 24
Finished Aug 16 04:37:45 PM PDT 24
Peak memory 256844 kb
Host smart-72a6fbb0-698c-4309-bd39-75e549b20846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16479
7763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.164797763
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3315630970
Short name T329
Test name
Test status
Simulation time 30829389596 ps
CPU time 1169.96 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:56:39 PM PDT 24
Peak memory 272228 kb
Host smart-ba19cc83-6d39-4510-873d-38caa875d71b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315630970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3315630970
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2931901080
Short name T503
Test name
Test status
Simulation time 37246326704 ps
CPU time 2212.16 seconds
Started Aug 16 04:36:56 PM PDT 24
Finished Aug 16 05:13:49 PM PDT 24
Peak memory 273280 kb
Host smart-99e7e6d2-0347-4024-b28b-867709162fcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931901080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2931901080
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1096810365
Short name T313
Test name
Test status
Simulation time 30756683367 ps
CPU time 341.47 seconds
Started Aug 16 04:37:00 PM PDT 24
Finished Aug 16 04:42:42 PM PDT 24
Peak memory 247752 kb
Host smart-7f7d7ba8-83b0-46cb-8983-eebba402df32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096810365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1096810365
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1631003998
Short name T94
Test name
Test status
Simulation time 737546303 ps
CPU time 17 seconds
Started Aug 16 04:36:52 PM PDT 24
Finished Aug 16 04:37:10 PM PDT 24
Peak memory 256120 kb
Host smart-c87fee34-a55b-4903-9490-2a0d51bd378b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16310
03998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1631003998
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.4055015603
Short name T687
Test name
Test status
Simulation time 318973992 ps
CPU time 20.43 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:37:24 PM PDT 24
Peak memory 256880 kb
Host smart-e77b3119-7995-492e-99f2-87a02087aa87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40550
15603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.4055015603
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.670908883
Short name T579
Test name
Test status
Simulation time 257455555 ps
CPU time 17.93 seconds
Started Aug 16 04:37:17 PM PDT 24
Finished Aug 16 04:37:35 PM PDT 24
Peak memory 256228 kb
Host smart-3fb59317-b81f-447a-9faa-43bcc92e0c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67090
8883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.670908883
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1680793633
Short name T348
Test name
Test status
Simulation time 44020373 ps
CPU time 4.43 seconds
Started Aug 16 04:37:16 PM PDT 24
Finished Aug 16 04:37:21 PM PDT 24
Peak memory 248632 kb
Host smart-4e77f73b-7d28-40ea-955b-d00b8cf0a87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16807
93633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1680793633
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1831774490
Short name T500
Test name
Test status
Simulation time 199274263188 ps
CPU time 2847.64 seconds
Started Aug 16 04:37:13 PM PDT 24
Finished Aug 16 05:24:41 PM PDT 24
Peak memory 287420 kb
Host smart-4e284052-cbce-487c-931c-c773a954e671
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831774490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1831774490
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3762002612
Short name T619
Test name
Test status
Simulation time 2852957313 ps
CPU time 86.84 seconds
Started Aug 16 04:37:24 PM PDT 24
Finished Aug 16 04:38:50 PM PDT 24
Peak memory 265444 kb
Host smart-99b5dc54-357e-4d63-bf17-747a3b102f48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762002612 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3762002612
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.287120849
Short name T206
Test name
Test status
Simulation time 16659710 ps
CPU time 2.55 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:36:58 PM PDT 24
Peak memory 248876 kb
Host smart-cd835ffa-1118-4385-9ac5-27fbd4a3cb00
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=287120849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.287120849
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3152191768
Short name T457
Test name
Test status
Simulation time 102897788738 ps
CPU time 1683.65 seconds
Started Aug 16 04:37:03 PM PDT 24
Finished Aug 16 05:05:07 PM PDT 24
Peak memory 273324 kb
Host smart-2da23e7e-10d1-41d9-8e21-441808617bc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152191768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3152191768
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1101494940
Short name T668
Test name
Test status
Simulation time 968261329 ps
CPU time 41.61 seconds
Started Aug 16 04:37:30 PM PDT 24
Finished Aug 16 04:38:11 PM PDT 24
Peak memory 248620 kb
Host smart-2de997f7-89b6-4e28-86c1-2bb70f37935b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1101494940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1101494940
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2799606537
Short name T450
Test name
Test status
Simulation time 5348335334 ps
CPU time 66.98 seconds
Started Aug 16 04:36:56 PM PDT 24
Finished Aug 16 04:38:03 PM PDT 24
Peak memory 256588 kb
Host smart-cfcd87a0-e8c4-4574-b207-e3e60feda373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27996
06537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2799606537
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2333079855
Short name T620
Test name
Test status
Simulation time 288805292 ps
CPU time 4.81 seconds
Started Aug 16 04:37:12 PM PDT 24
Finished Aug 16 04:37:17 PM PDT 24
Peak memory 254600 kb
Host smart-a864d40d-f171-4add-9d3c-4ec1dc4110d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23330
79855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2333079855
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.557894845
Short name T463
Test name
Test status
Simulation time 27844017726 ps
CPU time 1253.05 seconds
Started Aug 16 04:37:02 PM PDT 24
Finished Aug 16 04:57:55 PM PDT 24
Peak memory 289136 kb
Host smart-839371eb-f9b5-49a7-97a4-b384e62aba04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557894845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.557894845
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2009729285
Short name T361
Test name
Test status
Simulation time 12591196843 ps
CPU time 734.47 seconds
Started Aug 16 04:37:07 PM PDT 24
Finished Aug 16 04:49:22 PM PDT 24
Peak memory 269676 kb
Host smart-aa8c39d9-c543-4234-b1ad-5394c4829350
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009729285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2009729285
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.509047734
Short name T691
Test name
Test status
Simulation time 794486889 ps
CPU time 17.3 seconds
Started Aug 16 04:37:03 PM PDT 24
Finished Aug 16 04:37:20 PM PDT 24
Peak memory 256016 kb
Host smart-9557d2f5-9e21-4d40-93a1-a6ffac9c1371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50904
7734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.509047734
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1731046267
Short name T623
Test name
Test status
Simulation time 1615687002 ps
CPU time 34.14 seconds
Started Aug 16 04:37:20 PM PDT 24
Finished Aug 16 04:37:55 PM PDT 24
Peak memory 248536 kb
Host smart-b20d2c13-27d7-44dd-a8a4-1f951091948f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17310
46267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1731046267
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3593411199
Short name T629
Test name
Test status
Simulation time 86406238 ps
CPU time 8.66 seconds
Started Aug 16 04:36:59 PM PDT 24
Finished Aug 16 04:37:08 PM PDT 24
Peak memory 254296 kb
Host smart-94b5dc2c-1c17-488f-99f1-528361160f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35934
11199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3593411199
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1020678262
Short name T561
Test name
Test status
Simulation time 889810777 ps
CPU time 49.54 seconds
Started Aug 16 04:37:21 PM PDT 24
Finished Aug 16 04:38:11 PM PDT 24
Peak memory 256812 kb
Host smart-aadf7b7b-3b3b-4be3-9c06-0da111f0b3f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10206
78262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1020678262
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2802606728
Short name T285
Test name
Test status
Simulation time 106009939124 ps
CPU time 1219.41 seconds
Started Aug 16 04:37:02 PM PDT 24
Finished Aug 16 04:57:21 PM PDT 24
Peak memory 289040 kb
Host smart-b70a876c-e6a8-41c3-9edb-3e8290db3fb3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802606728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2802606728
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1529105276
Short name T209
Test name
Test status
Simulation time 16897641 ps
CPU time 2.59 seconds
Started Aug 16 04:37:17 PM PDT 24
Finished Aug 16 04:37:20 PM PDT 24
Peak memory 248872 kb
Host smart-ebb7c90d-a302-429b-bec7-c46be48a79b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1529105276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1529105276
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1753843581
Short name T270
Test name
Test status
Simulation time 59769140941 ps
CPU time 1278.7 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:58:19 PM PDT 24
Peak memory 281448 kb
Host smart-57d7827b-2bf5-4229-8590-daf19af360e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753843581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1753843581
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2634205602
Short name T538
Test name
Test status
Simulation time 950527968 ps
CPU time 23.82 seconds
Started Aug 16 04:36:53 PM PDT 24
Finished Aug 16 04:37:17 PM PDT 24
Peak memory 248848 kb
Host smart-33707b02-25c9-4b6c-87cc-0d400b39a5fa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2634205602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2634205602
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1439378693
Short name T539
Test name
Test status
Simulation time 1072462572 ps
CPU time 61.72 seconds
Started Aug 16 04:36:59 PM PDT 24
Finished Aug 16 04:38:01 PM PDT 24
Peak memory 249632 kb
Host smart-c6adf022-e864-419d-b44b-e743dfc6bf63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14393
78693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1439378693
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.219238072
Short name T642
Test name
Test status
Simulation time 4561546384 ps
CPU time 62.7 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:37:58 PM PDT 24
Peak memory 248456 kb
Host smart-f3b15eac-8061-42a4-9667-139b3e29320b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21923
8072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.219238072
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1610494311
Short name T112
Test name
Test status
Simulation time 135696372427 ps
CPU time 1677.67 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 05:04:59 PM PDT 24
Peak memory 273080 kb
Host smart-5bfc1995-054a-4960-8e37-3f39efde6e4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610494311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1610494311
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1535901618
Short name T359
Test name
Test status
Simulation time 30168553894 ps
CPU time 1799.15 seconds
Started Aug 16 04:37:17 PM PDT 24
Finished Aug 16 05:07:21 PM PDT 24
Peak memory 272776 kb
Host smart-da1c7fdf-171b-4cf9-8ccd-29cd0c8cfd1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535901618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1535901618
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.550087196
Short name T16
Test name
Test status
Simulation time 8256572541 ps
CPU time 355.59 seconds
Started Aug 16 04:36:49 PM PDT 24
Finished Aug 16 04:42:45 PM PDT 24
Peak memory 248628 kb
Host smart-8a71a8ae-b1e9-46f5-bb16-d6a3d1646c32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550087196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.550087196
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.4112867876
Short name T550
Test name
Test status
Simulation time 2899841996 ps
CPU time 52.3 seconds
Started Aug 16 04:36:56 PM PDT 24
Finished Aug 16 04:37:48 PM PDT 24
Peak memory 256932 kb
Host smart-80527121-e4de-4457-b595-99938c05d2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41128
67876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.4112867876
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.612373235
Short name T218
Test name
Test status
Simulation time 57710118 ps
CPU time 6.91 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:37:01 PM PDT 24
Peak memory 248664 kb
Host smart-e4da6ec9-10e6-4ba4-a98d-1f57ef268e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61237
3235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.612373235
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3123721006
Short name T62
Test name
Test status
Simulation time 443702388 ps
CPU time 7.83 seconds
Started Aug 16 04:37:10 PM PDT 24
Finished Aug 16 04:37:18 PM PDT 24
Peak memory 251488 kb
Host smart-1d9cf0b0-a745-44be-973e-c99d58f2be05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31237
21006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3123721006
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2497489379
Short name T587
Test name
Test status
Simulation time 126443891399 ps
CPU time 2827.81 seconds
Started Aug 16 04:37:11 PM PDT 24
Finished Aug 16 05:24:19 PM PDT 24
Peak memory 297760 kb
Host smart-31620feb-8c1f-4e48-9823-9bb7f6b94e4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497489379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2497489379
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2282275409
Short name T251
Test name
Test status
Simulation time 9848831157 ps
CPU time 1190.75 seconds
Started Aug 16 04:37:31 PM PDT 24
Finished Aug 16 04:57:22 PM PDT 24
Peak memory 286404 kb
Host smart-a1ca7e45-f58f-44ce-97b9-b2a6a49998b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282275409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2282275409
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3222245645
Short name T373
Test name
Test status
Simulation time 8258417059 ps
CPU time 88.67 seconds
Started Aug 16 04:36:58 PM PDT 24
Finished Aug 16 04:38:27 PM PDT 24
Peak memory 248684 kb
Host smart-a4404036-285a-48cc-8937-98ce2d5fe762
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3222245645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3222245645
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2942042297
Short name T403
Test name
Test status
Simulation time 682232337 ps
CPU time 59.6 seconds
Started Aug 16 04:37:21 PM PDT 24
Finished Aug 16 04:38:21 PM PDT 24
Peak memory 256464 kb
Host smart-1ff4ff35-db5d-499f-947a-4e7783ca6c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29420
42297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2942042297
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1283695044
Short name T111
Test name
Test status
Simulation time 1399430829 ps
CPU time 49.76 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 04:37:51 PM PDT 24
Peak memory 256040 kb
Host smart-34165bff-c3fe-41dc-ab85-5b57d7df9ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12836
95044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1283695044
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2588306637
Short name T608
Test name
Test status
Simulation time 93538034120 ps
CPU time 1470.48 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 05:01:36 PM PDT 24
Peak memory 272916 kb
Host smart-9036b77e-b90a-46e2-b46d-e8295f0f5838
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588306637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2588306637
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2893555744
Short name T508
Test name
Test status
Simulation time 6107826687 ps
CPU time 243.78 seconds
Started Aug 16 04:37:13 PM PDT 24
Finished Aug 16 04:41:17 PM PDT 24
Peak memory 248724 kb
Host smart-824f3698-9ff6-4fe4-8376-cca581051bd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893555744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2893555744
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.722302740
Short name T381
Test name
Test status
Simulation time 528030724 ps
CPU time 32.54 seconds
Started Aug 16 04:37:08 PM PDT 24
Finished Aug 16 04:37:41 PM PDT 24
Peak memory 255984 kb
Host smart-7f1b6dbd-c694-46aa-b453-0e4b50a0199e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72230
2740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.722302740
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1812755124
Short name T44
Test name
Test status
Simulation time 1335901413 ps
CPU time 69.47 seconds
Started Aug 16 04:37:25 PM PDT 24
Finished Aug 16 04:38:34 PM PDT 24
Peak memory 256340 kb
Host smart-e2cb7063-50cc-4ec8-93f7-b1f985c869fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18127
55124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1812755124
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1480952692
Short name T13
Test name
Test status
Simulation time 531049167 ps
CPU time 39.8 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:37:45 PM PDT 24
Peak memory 248980 kb
Host smart-09c0d0ee-82ae-4e53-a850-0a70e6bcc2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14809
52692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1480952692
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3302222990
Short name T438
Test name
Test status
Simulation time 1540477065 ps
CPU time 47.45 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:37:51 PM PDT 24
Peak memory 256732 kb
Host smart-5aff3d37-4b97-4e7e-a742-528651d1e3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33022
22990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3302222990
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3351858
Short name T526
Test name
Test status
Simulation time 12789695847 ps
CPU time 177.19 seconds
Started Aug 16 04:36:56 PM PDT 24
Finished Aug 16 04:39:57 PM PDT 24
Peak memory 256860 kb
Host smart-1e08e975-b311-419a-93a3-07bcef65a852
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handl
er_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handl
er_stress_all.3351858
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.611253809
Short name T675
Test name
Test status
Simulation time 5990824873 ps
CPU time 221.7 seconds
Started Aug 16 04:37:21 PM PDT 24
Finished Aug 16 04:41:03 PM PDT 24
Peak memory 264876 kb
Host smart-340b4f14-07ad-492a-aae9-959f7ceb984a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611253809 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.611253809
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1947236385
Short name T208
Test name
Test status
Simulation time 20923878 ps
CPU time 2.68 seconds
Started Aug 16 04:36:51 PM PDT 24
Finished Aug 16 04:36:54 PM PDT 24
Peak memory 248856 kb
Host smart-2ef84118-548f-4f9e-80e9-841b728743e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1947236385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1947236385
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2854249923
Short name T633
Test name
Test status
Simulation time 104511827244 ps
CPU time 1435.16 seconds
Started Aug 16 04:36:39 PM PDT 24
Finished Aug 16 05:00:34 PM PDT 24
Peak memory 273104 kb
Host smart-39c2a3e2-8eb3-4965-af5d-8139377d359a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854249923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2854249923
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2222122143
Short name T673
Test name
Test status
Simulation time 135283840 ps
CPU time 8.87 seconds
Started Aug 16 04:36:44 PM PDT 24
Finished Aug 16 04:36:53 PM PDT 24
Peak memory 248580 kb
Host smart-7013e0c1-56c4-4c2d-833a-cd3c197eba84
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2222122143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2222122143
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.144215662
Short name T516
Test name
Test status
Simulation time 527522931 ps
CPU time 19.59 seconds
Started Aug 16 04:36:33 PM PDT 24
Finished Aug 16 04:36:52 PM PDT 24
Peak memory 248352 kb
Host smart-0a575630-d18d-4d40-ae83-9a9f67d03ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14421
5662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.144215662
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.859140508
Short name T491
Test name
Test status
Simulation time 989533440 ps
CPU time 18.42 seconds
Started Aug 16 04:36:50 PM PDT 24
Finished Aug 16 04:37:09 PM PDT 24
Peak memory 256840 kb
Host smart-d961f55b-b4e2-4c5c-9571-fc11417ad33f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85914
0508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.859140508
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2590740925
Short name T464
Test name
Test status
Simulation time 104809013357 ps
CPU time 1732.56 seconds
Started Aug 16 04:36:50 PM PDT 24
Finished Aug 16 05:05:43 PM PDT 24
Peak memory 272400 kb
Host smart-6ff60f3e-ade4-41c2-9cef-14fedb908fe9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590740925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2590740925
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2865658626
Short name T496
Test name
Test status
Simulation time 63864895204 ps
CPU time 2084.61 seconds
Started Aug 16 04:36:43 PM PDT 24
Finished Aug 16 05:11:28 PM PDT 24
Peak memory 288368 kb
Host smart-4449c72d-4efa-40f5-92dc-a78d0d1de01c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865658626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2865658626
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.356539327
Short name T310
Test name
Test status
Simulation time 46479059348 ps
CPU time 463.34 seconds
Started Aug 16 04:36:42 PM PDT 24
Finished Aug 16 04:44:26 PM PDT 24
Peak memory 256804 kb
Host smart-bfb61ab9-0ed8-4c7a-89ef-b0dd65459229
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356539327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.356539327
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2078296668
Short name T583
Test name
Test status
Simulation time 165222776 ps
CPU time 13.78 seconds
Started Aug 16 04:36:26 PM PDT 24
Finished Aug 16 04:36:40 PM PDT 24
Peak memory 256756 kb
Host smart-3fda343e-092c-4506-b883-e49a60632f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20782
96668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2078296668
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2188492750
Short name T52
Test name
Test status
Simulation time 946339743 ps
CPU time 15.61 seconds
Started Aug 16 04:36:43 PM PDT 24
Finished Aug 16 04:36:59 PM PDT 24
Peak memory 248172 kb
Host smart-220b57db-2823-4865-8042-ff81eb96a729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21884
92750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2188492750
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2598980037
Short name T10
Test name
Test status
Simulation time 683805621 ps
CPU time 12.91 seconds
Started Aug 16 04:36:29 PM PDT 24
Finished Aug 16 04:36:42 PM PDT 24
Peak memory 269772 kb
Host smart-a1916d51-f0dd-406d-ba90-996e8ff2c8a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2598980037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2598980037
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2551439280
Short name T284
Test name
Test status
Simulation time 359974400 ps
CPU time 9.39 seconds
Started Aug 16 04:37:03 PM PDT 24
Finished Aug 16 04:37:12 PM PDT 24
Peak memory 248064 kb
Host smart-51bf96e5-60f4-4bf2-9a36-365e594dfc11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25514
39280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2551439280
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1614298293
Short name T459
Test name
Test status
Simulation time 134368076 ps
CPU time 12.85 seconds
Started Aug 16 04:36:39 PM PDT 24
Finished Aug 16 04:36:52 PM PDT 24
Peak memory 256812 kb
Host smart-7c057570-2236-468e-a0ad-d2dbf17780fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16142
98293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1614298293
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2658300752
Short name T396
Test name
Test status
Simulation time 1647064809 ps
CPU time 48 seconds
Started Aug 16 04:36:42 PM PDT 24
Finished Aug 16 04:37:30 PM PDT 24
Peak memory 257128 kb
Host smart-fc8fd6c6-45fe-4da0-8ddf-1da2b5d94015
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658300752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2658300752
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2484664471
Short name T624
Test name
Test status
Simulation time 40666981656 ps
CPU time 2215.11 seconds
Started Aug 16 04:37:21 PM PDT 24
Finished Aug 16 05:14:16 PM PDT 24
Peak memory 289644 kb
Host smart-090e87dc-5e1f-4552-83c2-6a315ff4dbaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484664471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2484664471
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.4134056246
Short name T452
Test name
Test status
Simulation time 6168827839 ps
CPU time 346.33 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:42:42 PM PDT 24
Peak memory 256896 kb
Host smart-ea0d57e2-b8a1-488b-bff8-5d46cbf4d227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41340
56246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.4134056246
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1294087507
Short name T394
Test name
Test status
Simulation time 355613796 ps
CPU time 31.75 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 04:37:37 PM PDT 24
Peak memory 248380 kb
Host smart-ccc6a9bb-7bac-4188-9a06-dcdab84ca4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12940
87507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1294087507
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.113374736
Short name T352
Test name
Test status
Simulation time 25769666049 ps
CPU time 1182.37 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:56:47 PM PDT 24
Peak memory 288900 kb
Host smart-c2b56479-e869-476b-bb22-e84d0825bb53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113374736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.113374736
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.775836728
Short name T320
Test name
Test status
Simulation time 26113848254 ps
CPU time 519.9 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 04:45:41 PM PDT 24
Peak memory 248692 kb
Host smart-c868ef97-fd08-41c7-bf56-f431eabcac8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775836728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.775836728
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1997305561
Short name T240
Test name
Test status
Simulation time 37319794 ps
CPU time 4.95 seconds
Started Aug 16 04:37:20 PM PDT 24
Finished Aug 16 04:37:25 PM PDT 24
Peak memory 248588 kb
Host smart-6f00ee84-b3ae-4965-b30e-edba3c3a2f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19973
05561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1997305561
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2900413067
Short name T357
Test name
Test status
Simulation time 638601915 ps
CPU time 37.76 seconds
Started Aug 16 04:37:15 PM PDT 24
Finished Aug 16 04:38:03 PM PDT 24
Peak memory 248696 kb
Host smart-eaf4b002-603c-4cfd-b053-3f9e32826c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29004
13067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2900413067
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2603298606
Short name T680
Test name
Test status
Simulation time 687512225 ps
CPU time 44.89 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:37:40 PM PDT 24
Peak memory 256024 kb
Host smart-99b6bcbb-a158-44d6-8eed-de02ba8762d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26032
98606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2603298606
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.4142881035
Short name T65
Test name
Test status
Simulation time 983865016 ps
CPU time 60.4 seconds
Started Aug 16 04:37:13 PM PDT 24
Finished Aug 16 04:38:14 PM PDT 24
Peak memory 256820 kb
Host smart-c21c1c5d-23cb-4044-a8ec-b12f74fe4b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41428
81035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.4142881035
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1962844491
Short name T645
Test name
Test status
Simulation time 4407379851 ps
CPU time 100.34 seconds
Started Aug 16 04:37:13 PM PDT 24
Finished Aug 16 04:38:54 PM PDT 24
Peak memory 256952 kb
Host smart-9bd94807-65dc-4787-bbcb-bc50af5e2700
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962844491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1962844491
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2845463051
Short name T585
Test name
Test status
Simulation time 12248030481 ps
CPU time 235.59 seconds
Started Aug 16 04:36:56 PM PDT 24
Finished Aug 16 04:40:52 PM PDT 24
Peak memory 265552 kb
Host smart-d051cbc0-6117-4705-ac74-29eb8c818e8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845463051 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2845463051
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.6067153
Short name T11
Test name
Test status
Simulation time 20407443254 ps
CPU time 193.84 seconds
Started Aug 16 04:37:13 PM PDT 24
Finished Aug 16 04:40:27 PM PDT 24
Peak memory 256556 kb
Host smart-92264ce9-0da9-4be7-a1d4-3b5e7cabe79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60671
53 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.6067153
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3034056105
Short name T706
Test name
Test status
Simulation time 422255785 ps
CPU time 34.42 seconds
Started Aug 16 04:37:12 PM PDT 24
Finished Aug 16 04:37:46 PM PDT 24
Peak memory 248644 kb
Host smart-c8809bff-2e88-47e3-b2af-406b2f73faf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30340
56105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3034056105
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.704274231
Short name T676
Test name
Test status
Simulation time 74016028072 ps
CPU time 1182.32 seconds
Started Aug 16 04:37:17 PM PDT 24
Finished Aug 16 04:57:00 PM PDT 24
Peak memory 273300 kb
Host smart-1885c872-513a-48cc-9ea2-9c45e3c55af3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704274231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.704274231
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2606059061
Short name T603
Test name
Test status
Simulation time 27458310778 ps
CPU time 1713.16 seconds
Started Aug 16 04:37:13 PM PDT 24
Finished Aug 16 05:05:47 PM PDT 24
Peak memory 281484 kb
Host smart-dcefd51f-1920-44a0-852e-37af8bda9de0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606059061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2606059061
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1535552434
Short name T498
Test name
Test status
Simulation time 5126305618 ps
CPU time 214.17 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:40:34 PM PDT 24
Peak memory 247528 kb
Host smart-a85918c9-cf76-4c45-8e36-35cfddd0cac3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535552434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1535552434
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2555558115
Short name T528
Test name
Test status
Simulation time 11693734761 ps
CPU time 41.6 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:37:45 PM PDT 24
Peak memory 256896 kb
Host smart-5946ec32-3a86-4166-b9ec-0874ba730322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25555
58115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2555558115
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1565276548
Short name T670
Test name
Test status
Simulation time 6464180122 ps
CPU time 19.76 seconds
Started Aug 16 04:37:15 PM PDT 24
Finished Aug 16 04:37:34 PM PDT 24
Peak memory 255900 kb
Host smart-e90dc79b-e717-4080-9e92-985d2658ed01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15652
76548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1565276548
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.716672187
Short name T685
Test name
Test status
Simulation time 105881494 ps
CPU time 12.15 seconds
Started Aug 16 04:37:30 PM PDT 24
Finished Aug 16 04:37:42 PM PDT 24
Peak memory 248032 kb
Host smart-49b569c9-6bd4-4f5b-9e27-b72af099bd5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71667
2187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.716672187
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.211718254
Short name T448
Test name
Test status
Simulation time 412607986 ps
CPU time 9.61 seconds
Started Aug 16 04:36:58 PM PDT 24
Finished Aug 16 04:37:08 PM PDT 24
Peak memory 256880 kb
Host smart-beddf142-3bf1-4fb1-9545-0e705830643c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21171
8254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.211718254
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3437039938
Short name T269
Test name
Test status
Simulation time 15965705230 ps
CPU time 1083.76 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 04:55:05 PM PDT 24
Peak memory 289428 kb
Host smart-f00887d6-01ea-4aee-a615-329e3b791e75
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437039938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3437039938
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1942416147
Short name T575
Test name
Test status
Simulation time 18892808632 ps
CPU time 1098.35 seconds
Started Aug 16 04:37:28 PM PDT 24
Finished Aug 16 04:55:47 PM PDT 24
Peak memory 273244 kb
Host smart-95c4e93d-baf3-48cb-a34f-433889b27ead
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942416147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1942416147
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3839658028
Short name T215
Test name
Test status
Simulation time 7205330165 ps
CPU time 93.15 seconds
Started Aug 16 04:37:09 PM PDT 24
Finished Aug 16 04:38:42 PM PDT 24
Peak memory 256964 kb
Host smart-cb982735-088d-4338-aecf-392cd376b5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38396
58028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3839658028
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.556403228
Short name T684
Test name
Test status
Simulation time 187918569 ps
CPU time 16.93 seconds
Started Aug 16 04:37:18 PM PDT 24
Finished Aug 16 04:37:35 PM PDT 24
Peak memory 248636 kb
Host smart-8f9e0874-bf8c-41c6-96d5-aa27875ea6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55640
3228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.556403228
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1608952074
Short name T335
Test name
Test status
Simulation time 156454794284 ps
CPU time 1913.47 seconds
Started Aug 16 04:37:29 PM PDT 24
Finished Aug 16 05:09:23 PM PDT 24
Peak memory 273252 kb
Host smart-92f808b1-d0a0-4b3a-9ed2-a4f6101996a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608952074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1608952074
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.4083526673
Short name T525
Test name
Test status
Simulation time 192972017933 ps
CPU time 2662.44 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 05:21:18 PM PDT 24
Peak memory 286368 kb
Host smart-72f2f7cf-d62f-4b75-ad0b-71a66db3e05c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083526673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.4083526673
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.613808360
Short name T304
Test name
Test status
Simulation time 25602426564 ps
CPU time 557.37 seconds
Started Aug 16 04:37:08 PM PDT 24
Finished Aug 16 04:46:26 PM PDT 24
Peak memory 255716 kb
Host smart-82fd608b-34ec-41b7-9bd1-9de5afdbbc4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613808360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.613808360
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3431433364
Short name T570
Test name
Test status
Simulation time 1831796182 ps
CPU time 59.53 seconds
Started Aug 16 04:37:34 PM PDT 24
Finished Aug 16 04:38:34 PM PDT 24
Peak memory 256860 kb
Host smart-c0aad395-78bd-43a4-ab5d-ba87e2579c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34314
33364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3431433364
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.579429178
Short name T524
Test name
Test status
Simulation time 1552081514 ps
CPU time 47.44 seconds
Started Aug 16 04:37:28 PM PDT 24
Finished Aug 16 04:38:16 PM PDT 24
Peak memory 248060 kb
Host smart-a95c5595-6db9-4a7a-b1ba-0d7ca880c99d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57942
9178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.579429178
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2645251230
Short name T553
Test name
Test status
Simulation time 392129365 ps
CPU time 5.84 seconds
Started Aug 16 04:37:21 PM PDT 24
Finished Aug 16 04:37:27 PM PDT 24
Peak memory 248692 kb
Host smart-6b8314de-a26d-427b-89a5-6cf624904b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26452
51230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2645251230
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1082302225
Short name T511
Test name
Test status
Simulation time 2630095581 ps
CPU time 45.36 seconds
Started Aug 16 04:36:58 PM PDT 24
Finished Aug 16 04:37:44 PM PDT 24
Peak memory 256784 kb
Host smart-4e96e772-9d4d-4ab7-b596-6c9e4c1eb80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10823
02225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1082302225
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1807121867
Short name T643
Test name
Test status
Simulation time 54095440077 ps
CPU time 1810.05 seconds
Started Aug 16 04:37:11 PM PDT 24
Finished Aug 16 05:07:21 PM PDT 24
Peak memory 283068 kb
Host smart-f49274fd-db2f-4d37-9f64-911e7052e670
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807121867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1807121867
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2306613375
Short name T278
Test name
Test status
Simulation time 15831605750 ps
CPU time 523.01 seconds
Started Aug 16 04:37:25 PM PDT 24
Finished Aug 16 04:46:08 PM PDT 24
Peak memory 272128 kb
Host smart-7992fced-790d-495a-9007-9d0fc42bcb6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306613375 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2306613375
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2073790696
Short name T506
Test name
Test status
Simulation time 16265493363 ps
CPU time 797.47 seconds
Started Aug 16 04:36:58 PM PDT 24
Finished Aug 16 04:50:17 PM PDT 24
Peak memory 269232 kb
Host smart-a0957bcf-9e38-4173-8724-5c7d142755ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073790696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2073790696
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2387116259
Short name T238
Test name
Test status
Simulation time 33393755470 ps
CPU time 147.32 seconds
Started Aug 16 04:36:59 PM PDT 24
Finished Aug 16 04:39:26 PM PDT 24
Peak memory 256452 kb
Host smart-bbd6b464-fbc2-4627-9158-11433ef719a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23871
16259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2387116259
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2820109247
Short name T384
Test name
Test status
Simulation time 969671795 ps
CPU time 21.57 seconds
Started Aug 16 04:36:53 PM PDT 24
Finished Aug 16 04:37:15 PM PDT 24
Peak memory 256444 kb
Host smart-8c2308c0-204d-4240-b537-511dedc2a930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28201
09247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2820109247
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3549584130
Short name T545
Test name
Test status
Simulation time 24176013425 ps
CPU time 1421.53 seconds
Started Aug 16 04:37:09 PM PDT 24
Finished Aug 16 05:00:51 PM PDT 24
Peak memory 273188 kb
Host smart-9eaccc0c-6be0-4ac7-94d1-5c1f35f38934
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549584130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3549584130
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1992767301
Short name T625
Test name
Test status
Simulation time 82249311594 ps
CPU time 1269.43 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:58:04 PM PDT 24
Peak memory 289160 kb
Host smart-c756b97a-85fd-4427-9f09-a2e097440de7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992767301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1992767301
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3769091246
Short name T493
Test name
Test status
Simulation time 24739016873 ps
CPU time 529.18 seconds
Started Aug 16 04:37:20 PM PDT 24
Finished Aug 16 04:46:10 PM PDT 24
Peak memory 248644 kb
Host smart-cda3983e-2405-49aa-9a85-6dc9d691c4b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769091246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3769091246
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.20724120
Short name T50
Test name
Test status
Simulation time 1748704490 ps
CPU time 28.8 seconds
Started Aug 16 04:37:00 PM PDT 24
Finished Aug 16 04:37:29 PM PDT 24
Peak memory 255984 kb
Host smart-628b41c3-ffef-4fb3-b6e6-00ac5bb0e022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20724
120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.20724120
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.94858249
Short name T54
Test name
Test status
Simulation time 889952434 ps
CPU time 17.36 seconds
Started Aug 16 04:36:56 PM PDT 24
Finished Aug 16 04:37:14 PM PDT 24
Peak memory 248092 kb
Host smart-6e36a361-d58d-4e58-9023-974894e0aff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94858
249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.94858249
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2893377489
Short name T449
Test name
Test status
Simulation time 215412454 ps
CPU time 22.99 seconds
Started Aug 16 04:37:32 PM PDT 24
Finished Aug 16 04:37:55 PM PDT 24
Peak memory 249104 kb
Host smart-2a360c88-45d5-4991-aa43-9c3c86c910fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28933
77489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2893377489
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1413963709
Short name T391
Test name
Test status
Simulation time 581364505 ps
CPU time 15.29 seconds
Started Aug 16 04:37:28 PM PDT 24
Finished Aug 16 04:37:43 PM PDT 24
Peak memory 256784 kb
Host smart-406d390a-8a25-497e-aa3a-d41a99e321d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14139
63709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1413963709
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1819719494
Short name T73
Test name
Test status
Simulation time 42501299376 ps
CPU time 2432.88 seconds
Started Aug 16 04:37:15 PM PDT 24
Finished Aug 16 05:17:48 PM PDT 24
Peak memory 289368 kb
Host smart-08519775-573b-4dc5-bbf9-6681da8485aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819719494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1819719494
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2600525607
Short name T489
Test name
Test status
Simulation time 3439955302 ps
CPU time 154.03 seconds
Started Aug 16 04:37:07 PM PDT 24
Finished Aug 16 04:39:41 PM PDT 24
Peak memory 256432 kb
Host smart-81774716-9349-45ce-9826-222577d8b615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26005
25607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2600525607
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3756430462
Short name T367
Test name
Test status
Simulation time 303430541 ps
CPU time 19.57 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 04:37:25 PM PDT 24
Peak memory 256368 kb
Host smart-52064b6c-f551-4a42-bc26-357739cffdc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37564
30462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3756430462
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3356615359
Short name T340
Test name
Test status
Simulation time 276801780662 ps
CPU time 1975.72 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 05:10:00 PM PDT 24
Peak memory 281396 kb
Host smart-7cb06af1-b0e7-4acd-945b-11b96a5f8017
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356615359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3356615359
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.952873865
Short name T567
Test name
Test status
Simulation time 10318305093 ps
CPU time 823.1 seconds
Started Aug 16 04:36:57 PM PDT 24
Finished Aug 16 04:50:40 PM PDT 24
Peak memory 272784 kb
Host smart-bba5f936-a5f9-4bf0-9b9d-a5509af9e57e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952873865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.952873865
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1879993889
Short name T408
Test name
Test status
Simulation time 63694161 ps
CPU time 4.59 seconds
Started Aug 16 04:36:59 PM PDT 24
Finished Aug 16 04:37:04 PM PDT 24
Peak memory 248656 kb
Host smart-6d2bf2b2-23e5-4a91-91ff-36d29ea4a53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18799
93889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1879993889
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.4087326241
Short name T72
Test name
Test status
Simulation time 201726784 ps
CPU time 17.89 seconds
Started Aug 16 04:36:56 PM PDT 24
Finished Aug 16 04:37:15 PM PDT 24
Peak memory 248292 kb
Host smart-fb49ed35-ee5c-48cf-8fde-bf8289e2da47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40873
26241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.4087326241
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2286220050
Short name T75
Test name
Test status
Simulation time 769627794 ps
CPU time 12.79 seconds
Started Aug 16 04:37:14 PM PDT 24
Finished Aug 16 04:37:27 PM PDT 24
Peak memory 248116 kb
Host smart-74643a06-d7d4-4c25-a8f0-8965bf646153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22862
20050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2286220050
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.934755990
Short name T639
Test name
Test status
Simulation time 423598301 ps
CPU time 28.54 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 04:37:30 PM PDT 24
Peak memory 256452 kb
Host smart-7fe715df-3f41-46f8-83de-9697c6b3b489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93475
5990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.934755990
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3170425559
Short name T402
Test name
Test status
Simulation time 157006233254 ps
CPU time 1204.24 seconds
Started Aug 16 04:37:00 PM PDT 24
Finished Aug 16 04:57:05 PM PDT 24
Peak memory 289560 kb
Host smart-901168a5-cc59-4b21-a2e8-6117c7c95914
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170425559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3170425559
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.993836605
Short name T465
Test name
Test status
Simulation time 1804377145 ps
CPU time 55.82 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:38:00 PM PDT 24
Peak memory 256432 kb
Host smart-4060b38f-1963-422e-be0f-e06424acea56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99383
6605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.993836605
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2957493871
Short name T264
Test name
Test status
Simulation time 5016250974 ps
CPU time 78.83 seconds
Started Aug 16 04:37:03 PM PDT 24
Finished Aug 16 04:38:22 PM PDT 24
Peak memory 248704 kb
Host smart-d86129e3-9220-47f7-93ae-a4ba2a0a923a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29574
93871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2957493871
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2508098661
Short name T478
Test name
Test status
Simulation time 46538215632 ps
CPU time 1092.86 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:55:18 PM PDT 24
Peak memory 288984 kb
Host smart-a096b42c-9d81-4978-b119-89776df3008d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508098661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2508098661
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.405749800
Short name T306
Test name
Test status
Simulation time 29661259697 ps
CPU time 574.44 seconds
Started Aug 16 04:36:57 PM PDT 24
Finished Aug 16 04:46:31 PM PDT 24
Peak memory 247840 kb
Host smart-f48a6ee1-104b-47d7-a5e3-3808bbcb6731
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405749800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.405749800
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1821045009
Short name T596
Test name
Test status
Simulation time 344128362 ps
CPU time 33.06 seconds
Started Aug 16 04:37:17 PM PDT 24
Finished Aug 16 04:37:50 PM PDT 24
Peak memory 255888 kb
Host smart-3f56b7b6-3bc7-40a6-a7f3-37987019f4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18210
45009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1821045009
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1408301665
Short name T482
Test name
Test status
Simulation time 221276801 ps
CPU time 10.09 seconds
Started Aug 16 04:37:13 PM PDT 24
Finished Aug 16 04:37:24 PM PDT 24
Peak memory 255136 kb
Host smart-512c05dc-8ce4-47b8-83ae-16d6d8ec40b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14083
01665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1408301665
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.489124000
Short name T99
Test name
Test status
Simulation time 782417261 ps
CPU time 42.27 seconds
Started Aug 16 04:36:52 PM PDT 24
Finished Aug 16 04:37:35 PM PDT 24
Peak memory 248188 kb
Host smart-3fa8caee-f786-4282-b067-06c7643c1b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48912
4000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.489124000
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.881636942
Short name T377
Test name
Test status
Simulation time 1558444057 ps
CPU time 54.68 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:38:00 PM PDT 24
Peak memory 256864 kb
Host smart-3f0bc9ac-7a16-4820-9e91-38a9db66925d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88163
6942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.881636942
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2887356086
Short name T554
Test name
Test status
Simulation time 98025629560 ps
CPU time 1021.08 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 04:54:07 PM PDT 24
Peak memory 288824 kb
Host smart-dc43560c-024a-4bbc-a9e2-c741cdae43c8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887356086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2887356086
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1572340793
Short name T660
Test name
Test status
Simulation time 9859364641 ps
CPU time 1373.34 seconds
Started Aug 16 04:37:32 PM PDT 24
Finished Aug 16 05:00:25 PM PDT 24
Peak memory 289632 kb
Host smart-ac37c2ab-8f82-457b-b7b2-366acc51e56e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572340793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1572340793
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.620932639
Short name T523
Test name
Test status
Simulation time 453599208 ps
CPU time 51.37 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 04:37:56 PM PDT 24
Peak memory 256428 kb
Host smart-7d4bda95-6ba4-4928-bfe1-30217f41d80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62093
2639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.620932639
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3055472819
Short name T666
Test name
Test status
Simulation time 1482041396 ps
CPU time 9.62 seconds
Started Aug 16 04:37:24 PM PDT 24
Finished Aug 16 04:37:33 PM PDT 24
Peak memory 253236 kb
Host smart-9f8be4c7-327a-429e-98ae-f7661800c2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30554
72819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3055472819
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.329840749
Short name T677
Test name
Test status
Simulation time 156266387190 ps
CPU time 2023.41 seconds
Started Aug 16 04:37:09 PM PDT 24
Finished Aug 16 05:10:53 PM PDT 24
Peak memory 273088 kb
Host smart-7e7a779f-02e0-49bb-9d36-8b1f1a62c1ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329840749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.329840749
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1368009792
Short name T428
Test name
Test status
Simulation time 55211164206 ps
CPU time 3165.83 seconds
Started Aug 16 04:37:12 PM PDT 24
Finished Aug 16 05:29:58 PM PDT 24
Peak memory 289528 kb
Host smart-9a06563d-8167-4a3d-8862-1612028d33e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368009792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1368009792
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3200800923
Short name T324
Test name
Test status
Simulation time 18574699423 ps
CPU time 375.49 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 04:43:17 PM PDT 24
Peak memory 248724 kb
Host smart-d37a5065-7f42-4482-9066-c4a834e7bf1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200800923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3200800923
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1016450514
Short name T460
Test name
Test status
Simulation time 4745420492 ps
CPU time 41.76 seconds
Started Aug 16 04:37:12 PM PDT 24
Finished Aug 16 04:37:54 PM PDT 24
Peak memory 256060 kb
Host smart-01a881a1-a223-4d39-982f-4f135ec44d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10164
50514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1016450514
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1108017835
Short name T104
Test name
Test status
Simulation time 1650181955 ps
CPU time 54.04 seconds
Started Aug 16 04:37:31 PM PDT 24
Finished Aug 16 04:38:25 PM PDT 24
Peak memory 255924 kb
Host smart-984fb653-4cbd-4623-9e3c-e6ad61c8d309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11080
17835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1108017835
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.4238981829
Short name T245
Test name
Test status
Simulation time 266416755 ps
CPU time 41.84 seconds
Started Aug 16 04:37:36 PM PDT 24
Finished Aug 16 04:38:18 PM PDT 24
Peak memory 247816 kb
Host smart-1f3013af-6900-40dc-a00f-5fb167169fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42389
81829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.4238981829
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.273678386
Short name T595
Test name
Test status
Simulation time 2633207603 ps
CPU time 29.82 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 04:37:31 PM PDT 24
Peak memory 256872 kb
Host smart-447b9450-bbbd-4420-8e2b-8d4fd6d72be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27367
8386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.273678386
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1568123479
Short name T66
Test name
Test status
Simulation time 34499533537 ps
CPU time 1982.75 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 05:10:07 PM PDT 24
Peak memory 289324 kb
Host smart-8505a863-6957-447a-9cc5-caa5198d1644
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568123479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1568123479
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.462114069
Short name T100
Test name
Test status
Simulation time 45486427589 ps
CPU time 1272.81 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:58:18 PM PDT 24
Peak memory 289612 kb
Host smart-e1e56dd0-bbc2-4183-914d-705202810164
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462114069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.462114069
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3997423220
Short name T560
Test name
Test status
Simulation time 1440296102 ps
CPU time 89.58 seconds
Started Aug 16 04:37:10 PM PDT 24
Finished Aug 16 04:38:40 PM PDT 24
Peak memory 256492 kb
Host smart-69cefe37-f551-4944-aea0-b64947066d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39974
23220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3997423220
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2509996033
Short name T410
Test name
Test status
Simulation time 233939206 ps
CPU time 18.81 seconds
Started Aug 16 04:37:22 PM PDT 24
Finished Aug 16 04:37:41 PM PDT 24
Peak memory 248208 kb
Host smart-865817ca-e8af-4b24-93a5-0bc6308a6ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25099
96033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2509996033
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.49821485
Short name T28
Test name
Test status
Simulation time 180882142035 ps
CPU time 1398.59 seconds
Started Aug 16 04:37:13 PM PDT 24
Finished Aug 16 05:00:32 PM PDT 24
Peak memory 273272 kb
Host smart-672f0d4d-0bdb-4e95-9036-99256da1e11a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49821485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.49821485
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.761928526
Short name T605
Test name
Test status
Simulation time 8083808469 ps
CPU time 348.43 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 04:42:50 PM PDT 24
Peak memory 248668 kb
Host smart-309f4aff-081a-4d7f-bd68-bfad7e1b9fa6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761928526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.761928526
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.419968168
Short name T360
Test name
Test status
Simulation time 2649434184 ps
CPU time 45.34 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 04:37:46 PM PDT 24
Peak memory 248688 kb
Host smart-4a33d2c0-64e3-4700-a0a0-b4cf748d24e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41996
8168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.419968168
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.227526452
Short name T657
Test name
Test status
Simulation time 170640684 ps
CPU time 7.17 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:37:03 PM PDT 24
Peak memory 250856 kb
Host smart-8c6eb5ba-8a48-4a78-ba54-c99b63d58fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22752
6452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.227526452
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2652506054
Short name T298
Test name
Test status
Simulation time 1961044573 ps
CPU time 34.28 seconds
Started Aug 16 04:37:14 PM PDT 24
Finished Aug 16 04:37:48 PM PDT 24
Peak memory 248704 kb
Host smart-87ada864-4252-4d1e-b48d-030c74714be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26525
06054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2652506054
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1315841434
Short name T68
Test name
Test status
Simulation time 248308758 ps
CPU time 12.37 seconds
Started Aug 16 04:37:03 PM PDT 24
Finished Aug 16 04:37:16 PM PDT 24
Peak memory 254864 kb
Host smart-cc819029-a99b-4383-ae43-38297e1b7d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13158
41434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1315841434
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2065840031
Short name T22
Test name
Test status
Simulation time 1400012723 ps
CPU time 75.66 seconds
Started Aug 16 04:37:22 PM PDT 24
Finished Aug 16 04:38:38 PM PDT 24
Peak memory 265068 kb
Host smart-aea1ff99-5f4f-4adf-bf40-20714bd541ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065840031 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2065840031
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1916109030
Short name T477
Test name
Test status
Simulation time 67819586830 ps
CPU time 926.65 seconds
Started Aug 16 04:37:11 PM PDT 24
Finished Aug 16 04:52:38 PM PDT 24
Peak memory 289432 kb
Host smart-e02b6b46-eca9-4a74-ac61-a27a918897c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916109030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1916109030
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1075822223
Short name T261
Test name
Test status
Simulation time 1188661556 ps
CPU time 110.15 seconds
Started Aug 16 04:37:00 PM PDT 24
Finished Aug 16 04:38:55 PM PDT 24
Peak memory 256520 kb
Host smart-0f0f98f9-af89-4cff-b979-4a6269d8816d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10758
22223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1075822223
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.946947006
Short name T454
Test name
Test status
Simulation time 506366213 ps
CPU time 20.06 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 04:37:21 PM PDT 24
Peak memory 256944 kb
Host smart-dcd8b6e0-7ae6-4d1f-a474-7c7349c145cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94694
7006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.946947006
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.975874702
Short name T247
Test name
Test status
Simulation time 137473197742 ps
CPU time 2048.98 seconds
Started Aug 16 04:37:06 PM PDT 24
Finished Aug 16 05:11:16 PM PDT 24
Peak memory 286212 kb
Host smart-47d2a3dc-e35a-4b04-961b-43d911bd4346
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975874702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.975874702
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.898476488
Short name T91
Test name
Test status
Simulation time 51680123230 ps
CPU time 573.44 seconds
Started Aug 16 04:36:58 PM PDT 24
Finished Aug 16 04:46:31 PM PDT 24
Peak memory 248752 kb
Host smart-e6df37fb-5b15-4f7d-9fce-0eaff109f412
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898476488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.898476488
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3366619638
Short name T378
Test name
Test status
Simulation time 331010677 ps
CPU time 10.15 seconds
Started Aug 16 04:37:00 PM PDT 24
Finished Aug 16 04:37:11 PM PDT 24
Peak memory 248768 kb
Host smart-b5aab298-35cd-4f2f-aa77-58a721fddf59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33666
19638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3366619638
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.6704220
Short name T481
Test name
Test status
Simulation time 303294670 ps
CPU time 6.21 seconds
Started Aug 16 04:37:27 PM PDT 24
Finished Aug 16 04:37:33 PM PDT 24
Peak memory 249108 kb
Host smart-7e9a1987-2e37-4f9b-8b07-baa869aa883a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67042
20 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.6704220
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2051021917
Short name T425
Test name
Test status
Simulation time 1232802191 ps
CPU time 35.91 seconds
Started Aug 16 04:37:25 PM PDT 24
Finished Aug 16 04:38:01 PM PDT 24
Peak memory 256888 kb
Host smart-93228045-5770-4606-bbe4-5541d7ff7ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20510
21917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2051021917
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2159221671
Short name T69
Test name
Test status
Simulation time 252519356981 ps
CPU time 2389.3 seconds
Started Aug 16 04:37:23 PM PDT 24
Finished Aug 16 05:17:13 PM PDT 24
Peak memory 289712 kb
Host smart-b0641734-7d2d-4b21-9dcc-1b3842d70e90
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159221671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2159221671
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2536205253
Short name T443
Test name
Test status
Simulation time 64744652490 ps
CPU time 2516.23 seconds
Started Aug 16 04:37:21 PM PDT 24
Finished Aug 16 05:19:17 PM PDT 24
Peak memory 289368 kb
Host smart-d58677d6-660a-4a90-9ec0-20938c621b60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536205253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2536205253
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3756715260
Short name T353
Test name
Test status
Simulation time 330984952 ps
CPU time 25.44 seconds
Started Aug 16 04:37:22 PM PDT 24
Finished Aug 16 04:37:48 PM PDT 24
Peak memory 256012 kb
Host smart-46d42cb7-d089-4537-927b-1aa5a2fe99c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37567
15260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3756715260
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3431251962
Short name T354
Test name
Test status
Simulation time 300927854 ps
CPU time 31.94 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:37:32 PM PDT 24
Peak memory 248588 kb
Host smart-9fdcf524-a0fd-41c2-a9a4-23d5b2319783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34312
51962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3431251962
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.4111510326
Short name T327
Test name
Test status
Simulation time 42133464911 ps
CPU time 2463.13 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 05:17:58 PM PDT 24
Peak memory 283168 kb
Host smart-78e5ad40-1cc9-49cd-98b5-3f16707556f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111510326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.4111510326
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3123565105
Short name T647
Test name
Test status
Simulation time 20371715397 ps
CPU time 883.84 seconds
Started Aug 16 04:37:03 PM PDT 24
Finished Aug 16 04:51:47 PM PDT 24
Peak memory 284308 kb
Host smart-0c14643a-0c4d-4234-acec-e4bb8f8526d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123565105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3123565105
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3259010673
Short name T555
Test name
Test status
Simulation time 1469862389 ps
CPU time 28.21 seconds
Started Aug 16 04:37:12 PM PDT 24
Finished Aug 16 04:37:40 PM PDT 24
Peak memory 248596 kb
Host smart-a35c0425-d5db-4965-b900-401422bb5c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32590
10673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3259010673
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1859502450
Short name T559
Test name
Test status
Simulation time 430658706 ps
CPU time 25.15 seconds
Started Aug 16 04:36:59 PM PDT 24
Finished Aug 16 04:37:24 PM PDT 24
Peak memory 256528 kb
Host smart-a83faac6-1f78-4b69-a3a3-48d0753eca82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18595
02450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1859502450
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3180342035
Short name T279
Test name
Test status
Simulation time 991435589 ps
CPU time 62.87 seconds
Started Aug 16 04:37:33 PM PDT 24
Finished Aug 16 04:38:36 PM PDT 24
Peak memory 248640 kb
Host smart-1120768b-9a98-48f4-9208-e008a74701c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31803
42035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3180342035
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1586417286
Short name T253
Test name
Test status
Simulation time 672041610 ps
CPU time 37.94 seconds
Started Aug 16 04:37:22 PM PDT 24
Finished Aug 16 04:38:00 PM PDT 24
Peak memory 256868 kb
Host smart-eddac1ff-8081-463a-8b7d-2b3bc61a1d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15864
17286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1586417286
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.225707778
Short name T696
Test name
Test status
Simulation time 20052339458 ps
CPU time 1228.15 seconds
Started Aug 16 04:37:23 PM PDT 24
Finished Aug 16 04:57:51 PM PDT 24
Peak memory 273192 kb
Host smart-d0346e7f-cf66-44bf-8531-a2ef40e14aa1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225707778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.225707778
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.524427321
Short name T210
Test name
Test status
Simulation time 19782089 ps
CPU time 3 seconds
Started Aug 16 04:36:42 PM PDT 24
Finished Aug 16 04:36:45 PM PDT 24
Peak memory 248840 kb
Host smart-e1882cd2-c33e-4d7e-82dc-72346cc1d9c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=524427321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.524427321
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2693508572
Short name T121
Test name
Test status
Simulation time 148780754259 ps
CPU time 2149.55 seconds
Started Aug 16 04:36:48 PM PDT 24
Finished Aug 16 05:12:38 PM PDT 24
Peak memory 289716 kb
Host smart-598286a4-8ecd-4b8a-9fff-43c11a2661dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693508572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2693508572
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2077835247
Short name T227
Test name
Test status
Simulation time 1581957357 ps
CPU time 26.27 seconds
Started Aug 16 04:36:33 PM PDT 24
Finished Aug 16 04:37:00 PM PDT 24
Peak memory 248684 kb
Host smart-dab64907-a092-431e-96c3-01bde5840d9a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2077835247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2077835247
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3770594764
Short name T588
Test name
Test status
Simulation time 4272687704 ps
CPU time 94.63 seconds
Started Aug 16 04:36:41 PM PDT 24
Finished Aug 16 04:38:20 PM PDT 24
Peak memory 257008 kb
Host smart-ea0068bd-9fdc-412b-88ca-c5b8ad1fc2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37705
94764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3770594764
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2084478631
Short name T519
Test name
Test status
Simulation time 1430404631 ps
CPU time 41.79 seconds
Started Aug 16 04:36:29 PM PDT 24
Finished Aug 16 04:37:11 PM PDT 24
Peak memory 248624 kb
Host smart-587f4bf0-97c3-4616-a06d-6f75543dbdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20844
78631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2084478631
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1658849350
Short name T229
Test name
Test status
Simulation time 27146308256 ps
CPU time 1616.91 seconds
Started Aug 16 04:36:41 PM PDT 24
Finished Aug 16 05:03:38 PM PDT 24
Peak memory 282632 kb
Host smart-90dede62-6bdf-464c-b41c-de021c3050d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658849350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1658849350
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.656149624
Short name T397
Test name
Test status
Simulation time 51386726297 ps
CPU time 3026.16 seconds
Started Aug 16 04:36:39 PM PDT 24
Finished Aug 16 05:27:05 PM PDT 24
Peak memory 289348 kb
Host smart-f2e8487b-5dc5-4482-9c97-f93eeed29afd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656149624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.656149624
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2205379240
Short name T315
Test name
Test status
Simulation time 26250110050 ps
CPU time 276.68 seconds
Started Aug 16 04:36:39 PM PDT 24
Finished Aug 16 04:41:15 PM PDT 24
Peak memory 248536 kb
Host smart-f80ce7c8-8ef4-4428-8ecc-9a79d468cf86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205379240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2205379240
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.376441817
Short name T536
Test name
Test status
Simulation time 37646935 ps
CPU time 3.42 seconds
Started Aug 16 04:36:36 PM PDT 24
Finished Aug 16 04:36:40 PM PDT 24
Peak memory 248644 kb
Host smart-9bdd9305-a9fc-446b-8b9f-1e47c5202bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37644
1817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.376441817
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.711020799
Short name T236
Test name
Test status
Simulation time 201265624 ps
CPU time 5.2 seconds
Started Aug 16 04:36:33 PM PDT 24
Finished Aug 16 04:36:38 PM PDT 24
Peak memory 253004 kb
Host smart-07a8c173-8fa5-41b6-b914-ceef38012354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71102
0799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.711020799
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1719462820
Short name T31
Test name
Test status
Simulation time 421319751 ps
CPU time 23 seconds
Started Aug 16 04:36:36 PM PDT 24
Finished Aug 16 04:36:59 PM PDT 24
Peak memory 272720 kb
Host smart-280a67dd-4e10-4f82-924b-b392627e1850
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1719462820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1719462820
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3355486049
Short name T495
Test name
Test status
Simulation time 402009431 ps
CPU time 27.71 seconds
Started Aug 16 04:36:33 PM PDT 24
Finished Aug 16 04:37:01 PM PDT 24
Peak memory 256904 kb
Host smart-3d130a6e-aebd-47fd-befa-7da757bd5d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33554
86049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3355486049
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2658020669
Short name T574
Test name
Test status
Simulation time 30247717208 ps
CPU time 1863.75 seconds
Started Aug 16 04:36:29 PM PDT 24
Finished Aug 16 05:07:33 PM PDT 24
Peak memory 289528 kb
Host smart-722019af-858b-4ff6-b665-67dbb7a6dab9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658020669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2658020669
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.959409813
Short name T116
Test name
Test status
Simulation time 18132838434 ps
CPU time 255.32 seconds
Started Aug 16 04:36:39 PM PDT 24
Finished Aug 16 04:40:55 PM PDT 24
Peak memory 273432 kb
Host smart-f6865f86-9a97-4c73-ad6c-27270c29fc3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959409813 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.959409813
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2363767346
Short name T514
Test name
Test status
Simulation time 22556819743 ps
CPU time 1450.19 seconds
Started Aug 16 04:37:31 PM PDT 24
Finished Aug 16 05:01:41 PM PDT 24
Peak memory 273288 kb
Host smart-911400f7-64b9-4123-8b39-eda4e4fd88e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363767346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2363767346
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2533360998
Short name T406
Test name
Test status
Simulation time 3577023034 ps
CPU time 94.95 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 04:38:36 PM PDT 24
Peak memory 256592 kb
Host smart-3a180fcd-7911-45e7-8d97-281f9091d58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25333
60998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2533360998
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1043755541
Short name T70
Test name
Test status
Simulation time 2682227784 ps
CPU time 26.38 seconds
Started Aug 16 04:37:00 PM PDT 24
Finished Aug 16 04:37:27 PM PDT 24
Peak memory 248792 kb
Host smart-0ec97d37-7c2d-4226-bad2-5f3f6b8f55e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10437
55541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1043755541
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.571212877
Short name T231
Test name
Test status
Simulation time 39232494244 ps
CPU time 2333.2 seconds
Started Aug 16 04:37:00 PM PDT 24
Finished Aug 16 05:15:54 PM PDT 24
Peak memory 289628 kb
Host smart-b85c1dc8-0dcb-4971-8fe4-016d3b011aea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571212877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.571212877
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3083895881
Short name T548
Test name
Test status
Simulation time 855123865 ps
CPU time 47.01 seconds
Started Aug 16 04:37:20 PM PDT 24
Finished Aug 16 04:38:07 PM PDT 24
Peak memory 256100 kb
Host smart-2720b754-e1a4-49a2-b0f8-8bf2b7827789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30838
95881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3083895881
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3147767564
Short name T387
Test name
Test status
Simulation time 634559449 ps
CPU time 36.77 seconds
Started Aug 16 04:37:24 PM PDT 24
Finished Aug 16 04:38:01 PM PDT 24
Peak memory 256892 kb
Host smart-4d3224fb-3272-4e81-9694-234991d03c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31477
67564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3147767564
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3838337109
Short name T380
Test name
Test status
Simulation time 1106302767 ps
CPU time 32.49 seconds
Started Aug 16 04:37:03 PM PDT 24
Finished Aug 16 04:37:36 PM PDT 24
Peak memory 255808 kb
Host smart-5820715a-94eb-4e32-9a8f-3492b62a564a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38383
37109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3838337109
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.5486670
Short name T631
Test name
Test status
Simulation time 7546002252 ps
CPU time 57.89 seconds
Started Aug 16 04:37:24 PM PDT 24
Finished Aug 16 04:38:22 PM PDT 24
Peak memory 256828 kb
Host smart-8b035064-3aae-4eaa-aad6-bb5f667aaf04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54866
70 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.5486670
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.580610683
Short name T622
Test name
Test status
Simulation time 6807856422 ps
CPU time 137.87 seconds
Started Aug 16 04:37:00 PM PDT 24
Finished Aug 16 04:39:18 PM PDT 24
Peak memory 256836 kb
Host smart-5f42cb6e-4889-443b-bfba-7f7ac1337fa9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580610683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.580610683
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3833693639
Short name T682
Test name
Test status
Simulation time 13216235353 ps
CPU time 1273.13 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 04:58:19 PM PDT 24
Peak memory 286260 kb
Host smart-3352351f-a7b0-4027-9211-86dfadf59d84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833693639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3833693639
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.105268388
Short name T1
Test name
Test status
Simulation time 5813325223 ps
CPU time 48.56 seconds
Started Aug 16 04:37:36 PM PDT 24
Finished Aug 16 04:38:25 PM PDT 24
Peak memory 256364 kb
Host smart-f0dcf1b1-5ea9-4d90-b52c-137d73c9e710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10526
8388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.105268388
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2190723097
Short name T694
Test name
Test status
Simulation time 250709873 ps
CPU time 13.6 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:37:18 PM PDT 24
Peak memory 248240 kb
Host smart-f1eb2b55-f335-44c6-bec8-d3db0ca8aa69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21907
23097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2190723097
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2582212006
Short name T497
Test name
Test status
Simulation time 46478727598 ps
CPU time 1207.59 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 04:57:13 PM PDT 24
Peak memory 288316 kb
Host smart-f7e76ead-47cc-4026-885c-2134343d004f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582212006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2582212006
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.145442089
Short name T486
Test name
Test status
Simulation time 106252091400 ps
CPU time 1276.33 seconds
Started Aug 16 04:37:10 PM PDT 24
Finished Aug 16 04:58:27 PM PDT 24
Peak memory 286552 kb
Host smart-b15ac3f3-0bdb-4404-8923-54296e017761
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145442089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.145442089
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2987684187
Short name T576
Test name
Test status
Simulation time 16228411081 ps
CPU time 339.91 seconds
Started Aug 16 04:37:17 PM PDT 24
Finished Aug 16 04:42:57 PM PDT 24
Peak memory 255788 kb
Host smart-d778c36f-1eb6-476e-9fc0-60b1599e0b9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987684187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2987684187
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.4183294792
Short name T349
Test name
Test status
Simulation time 1127161557 ps
CPU time 64.76 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 04:38:10 PM PDT 24
Peak memory 248928 kb
Host smart-a75671f0-2ee5-492a-8476-25fa1584150f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41832
94792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.4183294792
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.622196107
Short name T487
Test name
Test status
Simulation time 4132173611 ps
CPU time 62.78 seconds
Started Aug 16 04:37:31 PM PDT 24
Finished Aug 16 04:38:34 PM PDT 24
Peak memory 247272 kb
Host smart-1ea9e580-731f-4b69-bbd6-6fbce0af50d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62219
6107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.622196107
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3812654764
Short name T413
Test name
Test status
Simulation time 287595676 ps
CPU time 31.02 seconds
Started Aug 16 04:37:02 PM PDT 24
Finished Aug 16 04:37:33 PM PDT 24
Peak memory 248560 kb
Host smart-90e909c8-1e3c-4f50-a51b-bb2af455b419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38126
54764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3812654764
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2569677254
Short name T364
Test name
Test status
Simulation time 636470687 ps
CPU time 8.02 seconds
Started Aug 16 04:37:00 PM PDT 24
Finished Aug 16 04:37:08 PM PDT 24
Peak memory 251600 kb
Host smart-c65172b2-9d84-42e3-92cf-00c8caff54c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25696
77254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2569677254
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1748260348
Short name T120
Test name
Test status
Simulation time 2089576490 ps
CPU time 154.08 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 04:39:40 PM PDT 24
Peak memory 265400 kb
Host smart-cfe27cf2-2008-40d2-b5c5-bce97b3dd272
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748260348 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1748260348
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.4231111474
Short name T71
Test name
Test status
Simulation time 66666935811 ps
CPU time 2158.31 seconds
Started Aug 16 04:37:34 PM PDT 24
Finished Aug 16 05:13:32 PM PDT 24
Peak memory 281344 kb
Host smart-b9751654-c16e-4c97-93a1-9f8e3100458a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231111474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.4231111474
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1193774449
Short name T472
Test name
Test status
Simulation time 7598174503 ps
CPU time 200.46 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:40:24 PM PDT 24
Peak memory 256456 kb
Host smart-197050bc-2113-4678-b559-44ba3c26fbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11937
74449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1193774449
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3552716873
Short name T123
Test name
Test status
Simulation time 4757958035 ps
CPU time 73.35 seconds
Started Aug 16 04:37:19 PM PDT 24
Finished Aug 16 04:38:33 PM PDT 24
Peak memory 256324 kb
Host smart-c4d48498-a608-4d0a-8665-eae3c30c4727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35527
16873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3552716873
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3135758673
Short name T234
Test name
Test status
Simulation time 134863069052 ps
CPU time 1676.84 seconds
Started Aug 16 04:37:24 PM PDT 24
Finished Aug 16 05:05:21 PM PDT 24
Peak memory 273168 kb
Host smart-4be5c492-8677-4926-93e1-b3e9c1d5ee84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135758673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3135758673
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1561929064
Short name T702
Test name
Test status
Simulation time 19712565477 ps
CPU time 1231.47 seconds
Started Aug 16 04:37:32 PM PDT 24
Finished Aug 16 04:58:04 PM PDT 24
Peak memory 289036 kb
Host smart-453ac149-1eaa-478b-890c-fee0ad905228
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561929064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1561929064
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3412554275
Short name T662
Test name
Test status
Simulation time 13508380906 ps
CPU time 131.28 seconds
Started Aug 16 04:37:19 PM PDT 24
Finished Aug 16 04:39:30 PM PDT 24
Peak memory 248812 kb
Host smart-61ec065e-b916-40c8-b4e4-649bc979cc66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412554275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3412554275
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2185657985
Short name T695
Test name
Test status
Simulation time 621050269 ps
CPU time 36.29 seconds
Started Aug 16 04:37:27 PM PDT 24
Finished Aug 16 04:38:03 PM PDT 24
Peak memory 256056 kb
Host smart-61b905a6-49fe-485b-86a2-bad9ce0db178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21856
57985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2185657985
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.63867715
Short name T558
Test name
Test status
Simulation time 847900989 ps
CPU time 45.57 seconds
Started Aug 16 04:37:17 PM PDT 24
Finished Aug 16 04:38:03 PM PDT 24
Peak memory 256012 kb
Host smart-3c531f36-fe4d-4596-8a4f-8dcbb413c61a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63867
715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.63867715
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2086414923
Short name T703
Test name
Test status
Simulation time 1355044960 ps
CPU time 52.57 seconds
Started Aug 16 04:37:21 PM PDT 24
Finished Aug 16 04:38:19 PM PDT 24
Peak memory 249152 kb
Host smart-27839541-076b-4d4a-9ca5-55460ede7e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20864
14923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2086414923
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2170499044
Short name T447
Test name
Test status
Simulation time 2969046695 ps
CPU time 39.43 seconds
Started Aug 16 04:37:11 PM PDT 24
Finished Aug 16 04:37:51 PM PDT 24
Peak memory 256008 kb
Host smart-31ee2056-8a09-498d-ac63-19b716bb4983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21704
99044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2170499044
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.644574680
Short name T274
Test name
Test status
Simulation time 16524002243 ps
CPU time 1480.59 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 05:01:46 PM PDT 24
Peak memory 297376 kb
Host smart-26fab3fe-7b68-49fd-9b2c-c948d1da5131
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644574680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.644574680
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.981531952
Short name T108
Test name
Test status
Simulation time 21137505053 ps
CPU time 317.61 seconds
Started Aug 16 04:37:13 PM PDT 24
Finished Aug 16 04:42:31 PM PDT 24
Peak memory 267160 kb
Host smart-b5137bff-455d-4d7d-81c3-ef20e9c1946d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981531952 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.981531952
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.606046829
Short name T513
Test name
Test status
Simulation time 365291777 ps
CPU time 34.86 seconds
Started Aug 16 04:37:17 PM PDT 24
Finished Aug 16 04:37:52 PM PDT 24
Peak memory 255956 kb
Host smart-3cd0de45-b0b5-4249-a609-d3588d153c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60604
6829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.606046829
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2458065503
Short name T469
Test name
Test status
Simulation time 2185622437 ps
CPU time 31.15 seconds
Started Aug 16 04:37:25 PM PDT 24
Finished Aug 16 04:37:56 PM PDT 24
Peak memory 256384 kb
Host smart-9a2161be-25fc-4e1a-9c20-c4d94a6b7b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24580
65503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2458065503
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2995088413
Short name T39
Test name
Test status
Simulation time 58090505671 ps
CPU time 1683.23 seconds
Started Aug 16 04:37:34 PM PDT 24
Finished Aug 16 05:05:38 PM PDT 24
Peak memory 272584 kb
Host smart-aaf784b3-d36b-463c-a1a0-8156038b92d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995088413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2995088413
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2977036731
Short name T589
Test name
Test status
Simulation time 200507466010 ps
CPU time 1232.9 seconds
Started Aug 16 04:37:34 PM PDT 24
Finished Aug 16 04:58:08 PM PDT 24
Peak memory 273400 kb
Host smart-4a39bcb3-56b2-4a97-9ddd-5aef4863a91b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977036731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2977036731
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3600969875
Short name T476
Test name
Test status
Simulation time 2138245216 ps
CPU time 95.64 seconds
Started Aug 16 04:37:25 PM PDT 24
Finished Aug 16 04:39:00 PM PDT 24
Peak memory 247840 kb
Host smart-56c737f1-09dd-4c8e-b0c1-800256494740
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600969875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3600969875
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3167272306
Short name T379
Test name
Test status
Simulation time 819676227 ps
CPU time 47.75 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:37:52 PM PDT 24
Peak memory 255876 kb
Host smart-ec2beaba-fbd7-409a-b5d9-dbf3ccaa8e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31672
72306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3167272306
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3134423892
Short name T294
Test name
Test status
Simulation time 790677242 ps
CPU time 49.13 seconds
Started Aug 16 04:37:06 PM PDT 24
Finished Aug 16 04:37:55 PM PDT 24
Peak memory 248712 kb
Host smart-7fb80460-ac62-4c05-bff6-a613578841bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31344
23892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3134423892
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2394419309
Short name T87
Test name
Test status
Simulation time 1491644018 ps
CPU time 43.96 seconds
Started Aug 16 04:37:21 PM PDT 24
Finished Aug 16 04:38:05 PM PDT 24
Peak memory 255896 kb
Host smart-d4baf155-551f-4f70-a49a-ca72bfe9b73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23944
19309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2394419309
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1401155813
Short name T522
Test name
Test status
Simulation time 3961283355 ps
CPU time 54.06 seconds
Started Aug 16 04:37:15 PM PDT 24
Finished Aug 16 04:38:09 PM PDT 24
Peak memory 256908 kb
Host smart-05cbab02-c4ae-4f2f-a118-dbb2739d0e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14011
55813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1401155813
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3506773085
Short name T47
Test name
Test status
Simulation time 107392375552 ps
CPU time 3091.98 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 05:28:38 PM PDT 24
Peak memory 289716 kb
Host smart-b6391a72-0519-4ad1-a1b9-8b7686bddd37
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506773085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3506773085
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.386204413
Short name T30
Test name
Test status
Simulation time 5191009853 ps
CPU time 610.09 seconds
Started Aug 16 04:37:12 PM PDT 24
Finished Aug 16 04:47:22 PM PDT 24
Peak memory 273048 kb
Host smart-80ef6d3c-a714-4f95-ae30-101f5210310a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386204413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.386204413
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.406052409
Short name T632
Test name
Test status
Simulation time 1587038273 ps
CPU time 128.8 seconds
Started Aug 16 04:37:36 PM PDT 24
Finished Aug 16 04:39:45 PM PDT 24
Peak memory 256128 kb
Host smart-414aa0e2-4849-4f39-b596-992a2326ee01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40605
2409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.406052409
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2650785139
Short name T106
Test name
Test status
Simulation time 575359695 ps
CPU time 11.82 seconds
Started Aug 16 04:37:32 PM PDT 24
Finished Aug 16 04:37:44 PM PDT 24
Peak memory 256392 kb
Host smart-26cea09f-e697-4b03-8827-3253e9e143f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26507
85139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2650785139
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.589466574
Short name T255
Test name
Test status
Simulation time 32164996110 ps
CPU time 674.89 seconds
Started Aug 16 04:37:16 PM PDT 24
Finished Aug 16 04:48:31 PM PDT 24
Peak memory 273280 kb
Host smart-c95eec41-fc4a-4f49-a076-3eff38dff51c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589466574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.589466574
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.977104210
Short name T29
Test name
Test status
Simulation time 5579872896 ps
CPU time 633.23 seconds
Started Aug 16 04:37:22 PM PDT 24
Finished Aug 16 04:47:55 PM PDT 24
Peak memory 273548 kb
Host smart-ed24b805-79cb-4e5e-80e3-a55bcf8d006f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977104210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.977104210
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2409235639
Short name T303
Test name
Test status
Simulation time 8223767409 ps
CPU time 326.55 seconds
Started Aug 16 04:37:32 PM PDT 24
Finished Aug 16 04:42:59 PM PDT 24
Peak memory 248788 kb
Host smart-15196061-b421-44ec-ace0-46bf3d486380
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409235639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2409235639
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1107831732
Short name T259
Test name
Test status
Simulation time 783282491 ps
CPU time 49.4 seconds
Started Aug 16 04:37:23 PM PDT 24
Finished Aug 16 04:38:12 PM PDT 24
Peak memory 256824 kb
Host smart-fd5c75f5-096a-4831-bcd7-cbe20e0afa4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11078
31732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1107831732
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2055711074
Short name T634
Test name
Test status
Simulation time 67811454 ps
CPU time 10.02 seconds
Started Aug 16 04:37:20 PM PDT 24
Finished Aug 16 04:37:30 PM PDT 24
Peak memory 247832 kb
Host smart-1f7842cf-19cd-4a98-9689-4747e5f2f18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20557
11074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2055711074
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.781043461
Short name T375
Test name
Test status
Simulation time 239167085 ps
CPU time 5.65 seconds
Started Aug 16 04:37:06 PM PDT 24
Finished Aug 16 04:37:12 PM PDT 24
Peak memory 254296 kb
Host smart-ba934b41-190b-4b79-9e69-a976c72cebd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78104
3461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.781043461
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.15502191
Short name T672
Test name
Test status
Simulation time 823343849 ps
CPU time 38.79 seconds
Started Aug 16 04:37:11 PM PDT 24
Finished Aug 16 04:37:50 PM PDT 24
Peak memory 256452 kb
Host smart-bc363114-a810-418e-a5b8-9702f9a8cc85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15502
191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.15502191
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2356647841
Short name T56
Test name
Test status
Simulation time 66999180323 ps
CPU time 1633.31 seconds
Started Aug 16 04:37:23 PM PDT 24
Finished Aug 16 05:04:37 PM PDT 24
Peak memory 298752 kb
Host smart-d5a37c5c-fac8-4c99-bd65-bc3d5aa6294c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356647841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2356647841
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2447058494
Short name T232
Test name
Test status
Simulation time 5894239585 ps
CPU time 107.66 seconds
Started Aug 16 04:37:23 PM PDT 24
Finished Aug 16 04:39:11 PM PDT 24
Peak memory 266196 kb
Host smart-b6f4f498-e812-4233-ace9-c1eb6dafa3e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447058494 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2447058494
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.4268369819
Short name T461
Test name
Test status
Simulation time 478426782964 ps
CPU time 3450.52 seconds
Started Aug 16 04:37:32 PM PDT 24
Finished Aug 16 05:35:03 PM PDT 24
Peak memory 289792 kb
Host smart-4ab694aa-58f0-440e-94fa-fde55adbc719
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268369819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.4268369819
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.4081347096
Short name T358
Test name
Test status
Simulation time 4585461988 ps
CPU time 37.57 seconds
Started Aug 16 04:37:24 PM PDT 24
Finished Aug 16 04:38:02 PM PDT 24
Peak memory 255964 kb
Host smart-0cbf4342-38e3-4e42-9fb0-8b5568488155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40813
47096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.4081347096
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2326920370
Short name T613
Test name
Test status
Simulation time 456216740 ps
CPU time 8.78 seconds
Started Aug 16 04:37:31 PM PDT 24
Finished Aug 16 04:37:41 PM PDT 24
Peak memory 251204 kb
Host smart-abcb343b-d503-42c1-9d9c-4d08331e9ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23269
20370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2326920370
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.583036921
Short name T485
Test name
Test status
Simulation time 39835770062 ps
CPU time 2278.41 seconds
Started Aug 16 04:37:35 PM PDT 24
Finished Aug 16 05:15:34 PM PDT 24
Peak memory 282024 kb
Host smart-8b977fc5-eeaf-4816-9e96-2efcb49a892c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583036921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.583036921
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1909319577
Short name T638
Test name
Test status
Simulation time 53479110921 ps
CPU time 2794.49 seconds
Started Aug 16 04:37:28 PM PDT 24
Finished Aug 16 05:24:03 PM PDT 24
Peak memory 288488 kb
Host smart-1e3ca7a9-f29a-4bc3-87f3-58e28552f884
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909319577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1909319577
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3929401560
Short name T437
Test name
Test status
Simulation time 119878232049 ps
CPU time 477.73 seconds
Started Aug 16 04:37:33 PM PDT 24
Finished Aug 16 04:45:31 PM PDT 24
Peak memory 248608 kb
Host smart-1484d76d-b047-4428-a414-8e3468d09b7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929401560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3929401560
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3986834964
Short name T593
Test name
Test status
Simulation time 1084047677 ps
CPU time 65.12 seconds
Started Aug 16 04:37:21 PM PDT 24
Finished Aug 16 04:38:26 PM PDT 24
Peak memory 255972 kb
Host smart-fa6372d5-ee52-4f9a-bcad-4101a5d5a7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39868
34964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3986834964
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1404763002
Short name T509
Test name
Test status
Simulation time 21950322 ps
CPU time 3.72 seconds
Started Aug 16 04:37:33 PM PDT 24
Finished Aug 16 04:37:37 PM PDT 24
Peak memory 240112 kb
Host smart-c5813790-6509-493c-9cb6-e4511396583f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14047
63002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1404763002
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.4060679812
Short name T325
Test name
Test status
Simulation time 695599599 ps
CPU time 8.26 seconds
Started Aug 16 04:37:06 PM PDT 24
Finished Aug 16 04:37:14 PM PDT 24
Peak memory 248700 kb
Host smart-bd4ce218-2d5d-49eb-92e5-aa52d8659c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40606
79812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.4060679812
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2991348047
Short name T421
Test name
Test status
Simulation time 197370684 ps
CPU time 7.19 seconds
Started Aug 16 04:37:27 PM PDT 24
Finished Aug 16 04:37:35 PM PDT 24
Peak memory 251552 kb
Host smart-75472ead-bb89-46e7-ab6f-8c369f7ec05c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29913
48047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2991348047
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1225819841
Short name T289
Test name
Test status
Simulation time 164123169789 ps
CPU time 2470.85 seconds
Started Aug 16 04:37:08 PM PDT 24
Finished Aug 16 05:18:19 PM PDT 24
Peak memory 284600 kb
Host smart-77f829c9-4a19-4844-ba8c-41ca517d5ca7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225819841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1225819841
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1116208474
Short name T93
Test name
Test status
Simulation time 7780857007 ps
CPU time 217.54 seconds
Started Aug 16 04:37:34 PM PDT 24
Finished Aug 16 04:41:12 PM PDT 24
Peak memory 256940 kb
Host smart-f5832647-ab1f-4bbd-a3cf-af7fd19d936d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11162
08474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1116208474
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2089171439
Short name T640
Test name
Test status
Simulation time 764957758 ps
CPU time 12.55 seconds
Started Aug 16 04:37:44 PM PDT 24
Finished Aug 16 04:37:56 PM PDT 24
Peak memory 256876 kb
Host smart-ad126268-56f9-46a9-b2b9-73f5fafc68ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20891
71439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2089171439
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1937180933
Short name T301
Test name
Test status
Simulation time 34316879490 ps
CPU time 2044.86 seconds
Started Aug 16 04:37:19 PM PDT 24
Finished Aug 16 05:11:24 PM PDT 24
Peak memory 284688 kb
Host smart-2193a330-ba60-47de-804f-a091e2fe57be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937180933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1937180933
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2049380391
Short name T556
Test name
Test status
Simulation time 11581932660 ps
CPU time 767.68 seconds
Started Aug 16 04:37:38 PM PDT 24
Finished Aug 16 04:50:26 PM PDT 24
Peak memory 271688 kb
Host smart-11e897f1-aee1-4c4b-96ba-5e4404d831b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049380391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2049380391
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3929000979
Short name T309
Test name
Test status
Simulation time 20110864471 ps
CPU time 388.89 seconds
Started Aug 16 04:37:31 PM PDT 24
Finished Aug 16 04:44:00 PM PDT 24
Peak memory 248832 kb
Host smart-df49cf1f-2742-4899-926a-fdbbe5cd2fec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929000979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3929000979
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.82814220
Short name T350
Test name
Test status
Simulation time 1793123443 ps
CPU time 51.8 seconds
Started Aug 16 04:37:31 PM PDT 24
Finished Aug 16 04:38:23 PM PDT 24
Peak memory 256216 kb
Host smart-0809dd5a-5e49-4229-8e4c-58c2f1b5dd32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82814
220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.82814220
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2132408585
Short name T273
Test name
Test status
Simulation time 121720715 ps
CPU time 10.75 seconds
Started Aug 16 04:37:27 PM PDT 24
Finished Aug 16 04:37:38 PM PDT 24
Peak memory 248312 kb
Host smart-4b7cd4dd-002c-47c5-970f-fb3a59daad6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21324
08585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2132408585
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1435871621
Short name T286
Test name
Test status
Simulation time 223442284 ps
CPU time 33.88 seconds
Started Aug 16 04:37:26 PM PDT 24
Finished Aug 16 04:38:00 PM PDT 24
Peak memory 248656 kb
Host smart-76c6f8ba-382b-435f-a43e-e681026630be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14358
71621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1435871621
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3876762526
Short name T362
Test name
Test status
Simulation time 30047816 ps
CPU time 4.32 seconds
Started Aug 16 04:37:40 PM PDT 24
Finished Aug 16 04:37:45 PM PDT 24
Peak memory 251816 kb
Host smart-4e9d7112-7134-4c0d-b4b4-f21e48344c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38767
62526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3876762526
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3570868554
Short name T355
Test name
Test status
Simulation time 835351640 ps
CPU time 54.35 seconds
Started Aug 16 04:37:07 PM PDT 24
Finished Aug 16 04:38:02 PM PDT 24
Peak memory 256804 kb
Host smart-1393bd99-8608-4335-962b-46b4e6021cf2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570868554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3570868554
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3585738292
Short name T275
Test name
Test status
Simulation time 3273339890 ps
CPU time 349.22 seconds
Started Aug 16 04:37:28 PM PDT 24
Finished Aug 16 04:43:18 PM PDT 24
Peak memory 273472 kb
Host smart-ea510331-d79f-49e2-b9e9-8cbd6acce6a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585738292 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3585738292
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3118093991
Short name T606
Test name
Test status
Simulation time 61192356216 ps
CPU time 1500.77 seconds
Started Aug 16 04:37:32 PM PDT 24
Finished Aug 16 05:02:33 PM PDT 24
Peak memory 289368 kb
Host smart-908ff6e4-d694-4482-8015-43c33db4fd56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118093991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3118093991
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.724221574
Short name T636
Test name
Test status
Simulation time 7840003024 ps
CPU time 117.58 seconds
Started Aug 16 04:37:07 PM PDT 24
Finished Aug 16 04:39:05 PM PDT 24
Peak memory 256480 kb
Host smart-85eede62-8c04-43ce-929b-c4c148afcfd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72422
1574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.724221574
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3200825477
Short name T564
Test name
Test status
Simulation time 264999105 ps
CPU time 4.92 seconds
Started Aug 16 04:37:19 PM PDT 24
Finished Aug 16 04:37:24 PM PDT 24
Peak memory 240456 kb
Host smart-2baf4c78-b237-409c-bbf4-c5b1ac8372dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32008
25477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3200825477
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.193764399
Short name T318
Test name
Test status
Simulation time 134963192394 ps
CPU time 1740.09 seconds
Started Aug 16 04:37:27 PM PDT 24
Finished Aug 16 05:06:28 PM PDT 24
Peak memory 289516 kb
Host smart-b7314a3f-ca03-4ab3-b615-d411379872d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193764399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.193764399
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.92250942
Short name T103
Test name
Test status
Simulation time 10247616667 ps
CPU time 879.25 seconds
Started Aug 16 04:37:23 PM PDT 24
Finished Aug 16 04:52:02 PM PDT 24
Peak memory 272468 kb
Host smart-5b94f4e6-6436-43c7-b583-ce31ad04af05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92250942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.92250942
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3751642581
Short name T228
Test name
Test status
Simulation time 11799129238 ps
CPU time 462.84 seconds
Started Aug 16 04:37:31 PM PDT 24
Finished Aug 16 04:45:14 PM PDT 24
Peak memory 248588 kb
Host smart-eefdef07-c256-494e-bad2-e53b506491e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751642581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3751642581
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.55964957
Short name T35
Test name
Test status
Simulation time 236210291 ps
CPU time 18.75 seconds
Started Aug 16 04:37:30 PM PDT 24
Finished Aug 16 04:37:49 PM PDT 24
Peak memory 256344 kb
Host smart-b94a86b2-78bc-4a2d-85e0-1624aff052ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55964
957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.55964957
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1944658314
Short name T651
Test name
Test status
Simulation time 162645511 ps
CPU time 13.51 seconds
Started Aug 16 04:37:20 PM PDT 24
Finished Aug 16 04:37:34 PM PDT 24
Peak memory 248308 kb
Host smart-a4052b1f-0e16-4b8b-aa15-0cbb13822149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19446
58314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1944658314
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.796381708
Short name T681
Test name
Test status
Simulation time 270896094 ps
CPU time 5.85 seconds
Started Aug 16 04:37:33 PM PDT 24
Finished Aug 16 04:37:39 PM PDT 24
Peak memory 254832 kb
Host smart-a916fed8-98c6-461e-9cae-794501f2fb79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79638
1708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.796381708
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1431189147
Short name T648
Test name
Test status
Simulation time 298204927269 ps
CPU time 3537.77 seconds
Started Aug 16 04:37:28 PM PDT 24
Finished Aug 16 05:36:27 PM PDT 24
Peak memory 305672 kb
Host smart-13cb3c54-6b54-47e8-a4fa-cdb54ad0c617
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431189147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1431189147
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2823921570
Short name T64
Test name
Test status
Simulation time 28832876557 ps
CPU time 1920.69 seconds
Started Aug 16 04:37:25 PM PDT 24
Finished Aug 16 05:09:26 PM PDT 24
Peak memory 283164 kb
Host smart-08a02fcf-b84f-4503-a846-9cb3fe1b189c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823921570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2823921570
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3359303085
Short name T527
Test name
Test status
Simulation time 13545580146 ps
CPU time 239.05 seconds
Started Aug 16 04:37:41 PM PDT 24
Finished Aug 16 04:41:41 PM PDT 24
Peak memory 256964 kb
Host smart-dda53f96-9304-4589-9ecf-7a4d32555274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33593
03085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3359303085
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1916298942
Short name T641
Test name
Test status
Simulation time 291368498 ps
CPU time 20.21 seconds
Started Aug 16 04:37:38 PM PDT 24
Finished Aug 16 04:37:58 PM PDT 24
Peak memory 248696 kb
Host smart-83dcb7d1-e8df-4568-9ec4-7341f322fb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19162
98942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1916298942
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1953831642
Short name T602
Test name
Test status
Simulation time 153549261940 ps
CPU time 1614.49 seconds
Started Aug 16 04:37:35 PM PDT 24
Finished Aug 16 05:04:30 PM PDT 24
Peak memory 289796 kb
Host smart-dc658a42-8f63-468a-b669-e59a612a2a2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953831642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1953831642
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.915798056
Short name T414
Test name
Test status
Simulation time 16379844418 ps
CPU time 703.28 seconds
Started Aug 16 04:37:35 PM PDT 24
Finished Aug 16 04:49:19 PM PDT 24
Peak memory 272868 kb
Host smart-128c96f9-75b8-4f24-a6ac-c94d5d9e5cc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915798056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.915798056
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3961494975
Short name T321
Test name
Test status
Simulation time 27507144443 ps
CPU time 273.05 seconds
Started Aug 16 04:37:27 PM PDT 24
Finished Aug 16 04:42:01 PM PDT 24
Peak memory 248716 kb
Host smart-cd0de0bc-507e-4d7a-abcc-736f9f1abff8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961494975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3961494975
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.300664763
Short name T376
Test name
Test status
Simulation time 623680217 ps
CPU time 32.09 seconds
Started Aug 16 04:37:40 PM PDT 24
Finished Aug 16 04:38:12 PM PDT 24
Peak memory 254696 kb
Host smart-a213c127-0d9e-404e-92ca-654408499bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30066
4763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.300664763
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2787877108
Short name T573
Test name
Test status
Simulation time 164067868 ps
CPU time 10.82 seconds
Started Aug 16 04:37:36 PM PDT 24
Finished Aug 16 04:37:47 PM PDT 24
Peak memory 248196 kb
Host smart-46d6e61b-7963-4bbe-a9ad-6a6f15bfdd17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27878
77108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2787877108
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3495289911
Short name T658
Test name
Test status
Simulation time 1161735483 ps
CPU time 53.24 seconds
Started Aug 16 04:37:28 PM PDT 24
Finished Aug 16 04:38:21 PM PDT 24
Peak memory 256100 kb
Host smart-12e7bf4c-c088-4be3-8ceb-2f666e875e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34952
89911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3495289911
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2518426534
Short name T542
Test name
Test status
Simulation time 87288734467 ps
CPU time 1483.67 seconds
Started Aug 16 04:37:33 PM PDT 24
Finished Aug 16 05:02:18 PM PDT 24
Peak memory 273356 kb
Host smart-636ede2b-0680-40fd-a167-d5448b63efa3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518426534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2518426534
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2458242252
Short name T95
Test name
Test status
Simulation time 4905973167 ps
CPU time 99.72 seconds
Started Aug 16 04:37:29 PM PDT 24
Finished Aug 16 04:39:09 PM PDT 24
Peak memory 265268 kb
Host smart-e903e53c-1d74-4a31-8b37-9f91ed166661
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458242252 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2458242252
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3197089492
Short name T114
Test name
Test status
Simulation time 40873499720 ps
CPU time 1143.5 seconds
Started Aug 16 04:37:38 PM PDT 24
Finished Aug 16 04:56:42 PM PDT 24
Peak memory 284736 kb
Host smart-6ee604db-a17e-4212-abe4-cc73d8c79223
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197089492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3197089492
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.10866464
Short name T502
Test name
Test status
Simulation time 527135125 ps
CPU time 53.72 seconds
Started Aug 16 04:37:27 PM PDT 24
Finished Aug 16 04:38:20 PM PDT 24
Peak memory 255996 kb
Host smart-f42ce6ee-e1ab-4681-826e-241fb6a3fe98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10866
464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.10866464
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2646889384
Short name T78
Test name
Test status
Simulation time 1909821364 ps
CPU time 38.07 seconds
Started Aug 16 04:37:29 PM PDT 24
Finished Aug 16 04:38:08 PM PDT 24
Peak memory 256340 kb
Host smart-8da1479c-dd31-41f6-878f-617ddd1b995b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26468
89384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2646889384
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.4046132690
Short name T67
Test name
Test status
Simulation time 9850524398 ps
CPU time 780.1 seconds
Started Aug 16 04:37:34 PM PDT 24
Finished Aug 16 04:50:35 PM PDT 24
Peak memory 273264 kb
Host smart-4aab1c2d-392d-4fb0-a03c-1f137db40dc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046132690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.4046132690
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1923652319
Short name T531
Test name
Test status
Simulation time 76860315600 ps
CPU time 1379.34 seconds
Started Aug 16 04:37:36 PM PDT 24
Finished Aug 16 05:00:36 PM PDT 24
Peak memory 272792 kb
Host smart-915fca02-e416-4b8b-adb5-8a5f3470140c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923652319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1923652319
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.4241209961
Short name T592
Test name
Test status
Simulation time 9691552435 ps
CPU time 112.99 seconds
Started Aug 16 04:37:27 PM PDT 24
Finished Aug 16 04:39:20 PM PDT 24
Peak memory 248672 kb
Host smart-eb182f50-dec1-4aeb-8e72-97fa0c4a64b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241209961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.4241209961
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.4124997725
Short name T92
Test name
Test status
Simulation time 528208527 ps
CPU time 32.21 seconds
Started Aug 16 04:37:28 PM PDT 24
Finished Aug 16 04:38:00 PM PDT 24
Peak memory 256828 kb
Host smart-bdc5950e-090a-4c33-bb24-3acdae027f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41249
97725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.4124997725
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2642273753
Short name T504
Test name
Test status
Simulation time 79391295 ps
CPU time 10.24 seconds
Started Aug 16 04:37:28 PM PDT 24
Finished Aug 16 04:37:38 PM PDT 24
Peak memory 255140 kb
Host smart-3320c4e5-b095-4f23-a109-b8763d7c0537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26422
73753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2642273753
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.373334798
Short name T125
Test name
Test status
Simulation time 573486629 ps
CPU time 33.43 seconds
Started Aug 16 04:37:26 PM PDT 24
Finished Aug 16 04:37:59 PM PDT 24
Peak memory 256660 kb
Host smart-cc951ad6-39c3-44ef-8edf-995c3421cbfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37333
4798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.373334798
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2173178593
Short name T597
Test name
Test status
Simulation time 250239482 ps
CPU time 30.26 seconds
Started Aug 16 04:37:32 PM PDT 24
Finished Aug 16 04:38:02 PM PDT 24
Peak memory 256764 kb
Host smart-f4ff5faa-d8ad-40d8-99b0-57146399e048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21731
78593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2173178593
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3133421248
Short name T510
Test name
Test status
Simulation time 5202317472 ps
CPU time 223.29 seconds
Started Aug 16 04:37:31 PM PDT 24
Finished Aug 16 04:41:14 PM PDT 24
Peak memory 253084 kb
Host smart-a0576e47-46ce-480d-a143-2a42e088f17d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133421248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3133421248
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2987401
Short name T203
Test name
Test status
Simulation time 49503233 ps
CPU time 4.03 seconds
Started Aug 16 04:36:39 PM PDT 24
Finished Aug 16 04:36:43 PM PDT 24
Peak memory 248840 kb
Host smart-d5bb59ec-22b1-42b1-9b9a-1f702511842f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2987401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2987401
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3062624239
Short name T549
Test name
Test status
Simulation time 473486770405 ps
CPU time 2446.92 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 05:17:49 PM PDT 24
Peak memory 281468 kb
Host smart-8676c0fc-3b3a-40d3-a0ec-a8fd0658746e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062624239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3062624239
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.702682551
Short name T586
Test name
Test status
Simulation time 395656429 ps
CPU time 11.23 seconds
Started Aug 16 04:36:38 PM PDT 24
Finished Aug 16 04:36:49 PM PDT 24
Peak memory 248568 kb
Host smart-49960281-7bd8-46f5-9adb-af4c5ed09d32
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=702682551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.702682551
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.236626257
Short name T505
Test name
Test status
Simulation time 997932385 ps
CPU time 42.38 seconds
Started Aug 16 04:36:38 PM PDT 24
Finished Aug 16 04:37:21 PM PDT 24
Peak memory 255884 kb
Host smart-8773630b-802a-4334-9f45-2ab5bd34b4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23662
6257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.236626257
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1369051034
Short name T74
Test name
Test status
Simulation time 103756405 ps
CPU time 4.19 seconds
Started Aug 16 04:36:45 PM PDT 24
Finished Aug 16 04:36:49 PM PDT 24
Peak memory 239936 kb
Host smart-0d619ddf-2f88-45c5-a357-68a682a7ba1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13690
51034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1369051034
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2334919471
Short name T334
Test name
Test status
Simulation time 82344612786 ps
CPU time 2362.3 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 05:16:17 PM PDT 24
Peak memory 283900 kb
Host smart-3fdd313c-46b1-4fcf-96ac-475a607e4f58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334919471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2334919471
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1972860613
Short name T356
Test name
Test status
Simulation time 98814629678 ps
CPU time 920.29 seconds
Started Aug 16 04:36:32 PM PDT 24
Finished Aug 16 04:51:52 PM PDT 24
Peak memory 272920 kb
Host smart-50372442-c0ec-433a-819a-002fb021803d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972860613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1972860613
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1271745576
Short name T17
Test name
Test status
Simulation time 44192422022 ps
CPU time 433.98 seconds
Started Aug 16 04:36:40 PM PDT 24
Finished Aug 16 04:43:54 PM PDT 24
Peak memory 247568 kb
Host smart-b4acbc8a-4a52-4634-8291-3e39348cf335
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271745576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1271745576
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1672083753
Short name T420
Test name
Test status
Simulation time 966109501 ps
CPU time 10.43 seconds
Started Aug 16 04:36:45 PM PDT 24
Finished Aug 16 04:36:56 PM PDT 24
Peak memory 248624 kb
Host smart-3c138ea2-c038-41bc-8230-c22fc57b801a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16720
83753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1672083753
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.324454663
Short name T401
Test name
Test status
Simulation time 158742819 ps
CPU time 13.74 seconds
Started Aug 16 04:36:33 PM PDT 24
Finished Aug 16 04:36:46 PM PDT 24
Peak memory 248164 kb
Host smart-127fcfa6-9051-4c0c-8b23-2ccfa9321282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32445
4663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.324454663
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.711340099
Short name T9
Test name
Test status
Simulation time 418835075 ps
CPU time 13.67 seconds
Started Aug 16 04:36:43 PM PDT 24
Finished Aug 16 04:36:57 PM PDT 24
Peak memory 274196 kb
Host smart-a714dd3e-6b29-4876-aaff-ddf6f6badddb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=711340099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.711340099
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1710162383
Short name T649
Test name
Test status
Simulation time 86625069 ps
CPU time 6.81 seconds
Started Aug 16 04:36:40 PM PDT 24
Finished Aug 16 04:36:47 PM PDT 24
Peak memory 251776 kb
Host smart-21abd228-fb84-4888-923f-6e012cd11631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17101
62383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1710162383
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1793034150
Short name T386
Test name
Test status
Simulation time 85326093 ps
CPU time 9.31 seconds
Started Aug 16 04:36:40 PM PDT 24
Finished Aug 16 04:36:49 PM PDT 24
Peak memory 254668 kb
Host smart-b0cd76c2-e429-415e-9d7d-8a31f0b9c9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17930
34150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1793034150
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2794183694
Short name T90
Test name
Test status
Simulation time 274378559844 ps
CPU time 3701.61 seconds
Started Aug 16 04:36:51 PM PDT 24
Finished Aug 16 05:38:33 PM PDT 24
Peak memory 303580 kb
Host smart-34fb2ca3-39f9-4791-8413-cbbb1ff0fae3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794183694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2794183694
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.127944019
Short name T262
Test name
Test status
Simulation time 2436413779 ps
CPU time 265.44 seconds
Started Aug 16 04:36:43 PM PDT 24
Finished Aug 16 04:41:08 PM PDT 24
Peak memory 266224 kb
Host smart-007840a6-6be0-4528-af57-20e9bc8bba21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127944019 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.127944019
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1398253122
Short name T521
Test name
Test status
Simulation time 778965910 ps
CPU time 51.85 seconds
Started Aug 16 04:37:26 PM PDT 24
Finished Aug 16 04:38:18 PM PDT 24
Peak memory 256248 kb
Host smart-39a67c52-9791-4429-8ea9-a7ab01b472fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13982
53122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1398253122
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.538808574
Short name T371
Test name
Test status
Simulation time 376558103 ps
CPU time 31.62 seconds
Started Aug 16 04:37:27 PM PDT 24
Finished Aug 16 04:37:59 PM PDT 24
Peak memory 248704 kb
Host smart-afc9d9ed-9236-4dfc-9b5d-b67a5fd024b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53880
8574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.538808574
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1530882698
Short name T433
Test name
Test status
Simulation time 35058097073 ps
CPU time 2156.16 seconds
Started Aug 16 04:37:36 PM PDT 24
Finished Aug 16 05:13:33 PM PDT 24
Peak memory 289276 kb
Host smart-d548dda1-86a7-4928-9c2f-6641c348bc78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530882698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1530882698
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1044153474
Short name T368
Test name
Test status
Simulation time 69122102370 ps
CPU time 2031.85 seconds
Started Aug 16 04:37:30 PM PDT 24
Finished Aug 16 05:11:23 PM PDT 24
Peak memory 273204 kb
Host smart-30e009c5-6ec3-48fb-aa49-7545e716177f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044153474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1044153474
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3081313352
Short name T404
Test name
Test status
Simulation time 11094657585 ps
CPU time 234.68 seconds
Started Aug 16 04:37:30 PM PDT 24
Finished Aug 16 04:41:25 PM PDT 24
Peak memory 256624 kb
Host smart-5476aa51-af78-4d2d-aee8-d94106873f3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081313352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3081313352
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3256434608
Short name T507
Test name
Test status
Simulation time 769195804 ps
CPU time 14.89 seconds
Started Aug 16 04:37:33 PM PDT 24
Finished Aug 16 04:37:49 PM PDT 24
Peak memory 248644 kb
Host smart-cfe38b11-0066-4183-a691-71892b0b70a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32564
34608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3256434608
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3750509950
Short name T248
Test name
Test status
Simulation time 288926310 ps
CPU time 27.13 seconds
Started Aug 16 04:37:37 PM PDT 24
Finished Aug 16 04:38:04 PM PDT 24
Peak memory 256508 kb
Host smart-268f7977-0c90-4e76-8193-1065587fee2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37505
09950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3750509950
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3156169949
Short name T101
Test name
Test status
Simulation time 185943425 ps
CPU time 23.26 seconds
Started Aug 16 04:37:34 PM PDT 24
Finished Aug 16 04:37:58 PM PDT 24
Peak memory 255836 kb
Host smart-13c8ebcb-9767-4199-8af8-e5b11432c2c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31561
69949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3156169949
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2090415633
Short name T239
Test name
Test status
Simulation time 527832135 ps
CPU time 25.38 seconds
Started Aug 16 04:37:38 PM PDT 24
Finished Aug 16 04:38:03 PM PDT 24
Peak memory 255736 kb
Host smart-3ca5b71e-7a4e-4029-b0dd-bfecbf73c223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20904
15633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2090415633
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2355773846
Short name T389
Test name
Test status
Simulation time 1325218841 ps
CPU time 116.68 seconds
Started Aug 16 04:37:34 PM PDT 24
Finished Aug 16 04:39:31 PM PDT 24
Peak memory 256832 kb
Host smart-8cd10f57-1032-4215-8b89-067ce774ea83
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355773846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2355773846
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3162248926
Short name T407
Test name
Test status
Simulation time 5356716159 ps
CPU time 149.21 seconds
Started Aug 16 04:37:30 PM PDT 24
Finished Aug 16 04:39:59 PM PDT 24
Peak memory 265212 kb
Host smart-cd2b03a9-ab88-44be-9ca9-988e4862596c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162248926 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3162248926
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1186594660
Short name T455
Test name
Test status
Simulation time 17891570994 ps
CPU time 1222.02 seconds
Started Aug 16 04:37:43 PM PDT 24
Finished Aug 16 04:58:05 PM PDT 24
Peak memory 273340 kb
Host smart-4af1ebd8-fe0c-468c-9ebf-b39982554f09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186594660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1186594660
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.201449789
Short name T626
Test name
Test status
Simulation time 16095731924 ps
CPU time 253.9 seconds
Started Aug 16 04:37:43 PM PDT 24
Finished Aug 16 04:41:57 PM PDT 24
Peak memory 257044 kb
Host smart-a38997bb-a093-48bb-9ccd-edee39102d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20144
9789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.201449789
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3177692632
Short name T671
Test name
Test status
Simulation time 367004718 ps
CPU time 24.71 seconds
Started Aug 16 04:37:35 PM PDT 24
Finished Aug 16 04:38:00 PM PDT 24
Peak memory 248020 kb
Host smart-b7752dc0-d3c7-4394-95cb-957c773f5dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31776
92632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3177692632
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1309396206
Short name T431
Test name
Test status
Simulation time 9094601011 ps
CPU time 723.55 seconds
Started Aug 16 04:37:36 PM PDT 24
Finished Aug 16 04:49:40 PM PDT 24
Peak memory 273028 kb
Host smart-d7cc3db0-414c-4e11-95d0-134d2b674ce9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309396206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1309396206
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1643076828
Short name T590
Test name
Test status
Simulation time 12974651501 ps
CPU time 1528.19 seconds
Started Aug 16 04:37:35 PM PDT 24
Finished Aug 16 05:03:04 PM PDT 24
Peak memory 289648 kb
Host smart-64cdd39f-5acf-40bb-b501-da9565d50aa7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643076828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1643076828
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2485157351
Short name T601
Test name
Test status
Simulation time 2313548213 ps
CPU time 96.72 seconds
Started Aug 16 04:37:34 PM PDT 24
Finished Aug 16 04:39:11 PM PDT 24
Peak memory 255844 kb
Host smart-83202e94-de10-48d6-a7ed-48ee478e1c23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485157351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2485157351
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1778253438
Short name T661
Test name
Test status
Simulation time 323061061 ps
CPU time 27.76 seconds
Started Aug 16 04:37:46 PM PDT 24
Finished Aug 16 04:38:14 PM PDT 24
Peak memory 256212 kb
Host smart-62df1a6a-eda8-48a3-b149-a9de326498f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17782
53438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1778253438
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2968022786
Short name T272
Test name
Test status
Simulation time 261623683 ps
CPU time 13.23 seconds
Started Aug 16 04:37:39 PM PDT 24
Finished Aug 16 04:37:52 PM PDT 24
Peak memory 248196 kb
Host smart-28b3d6e8-d8ac-425a-84f1-17925107f516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29680
22786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2968022786
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3806162040
Short name T390
Test name
Test status
Simulation time 340540035 ps
CPU time 22.84 seconds
Started Aug 16 04:37:32 PM PDT 24
Finished Aug 16 04:37:55 PM PDT 24
Peak memory 256380 kb
Host smart-f4dfd2c9-add4-43df-b004-04acfbe7e2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38061
62040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3806162040
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3367613167
Short name T411
Test name
Test status
Simulation time 552169278 ps
CPU time 42.44 seconds
Started Aug 16 04:37:31 PM PDT 24
Finished Aug 16 04:38:13 PM PDT 24
Peak memory 256956 kb
Host smart-08b0aeba-c0cb-46b9-8f53-070c6b1f3478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33676
13167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3367613167
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2991574001
Short name T594
Test name
Test status
Simulation time 10217468879 ps
CPU time 628.08 seconds
Started Aug 16 04:37:35 PM PDT 24
Finished Aug 16 04:48:04 PM PDT 24
Peak memory 256280 kb
Host smart-44d0aa67-eb89-49fa-bcde-4d86fe37cbed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991574001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2991574001
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.320202067
Short name T58
Test name
Test status
Simulation time 2380411373 ps
CPU time 87 seconds
Started Aug 16 04:37:41 PM PDT 24
Finished Aug 16 04:39:08 PM PDT 24
Peak memory 265204 kb
Host smart-4f8e7d19-68f0-44f1-9583-a8e2cf1e2f41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320202067 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.320202067
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2467751776
Short name T492
Test name
Test status
Simulation time 23286535337 ps
CPU time 1373.34 seconds
Started Aug 16 04:37:42 PM PDT 24
Finished Aug 16 05:00:35 PM PDT 24
Peak memory 272712 kb
Host smart-41a51f5d-3347-4a9a-a429-070433eadf8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467751776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2467751776
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1072147256
Short name T441
Test name
Test status
Simulation time 106519147 ps
CPU time 8.1 seconds
Started Aug 16 04:37:36 PM PDT 24
Finished Aug 16 04:37:44 PM PDT 24
Peak memory 251764 kb
Host smart-69a55c3c-f492-4860-84ea-81cc05098a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10721
47256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1072147256
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1129602246
Short name T683
Test name
Test status
Simulation time 2578498491 ps
CPU time 37.56 seconds
Started Aug 16 04:37:40 PM PDT 24
Finished Aug 16 04:38:18 PM PDT 24
Peak memory 255432 kb
Host smart-9c9ded2c-addf-4143-be85-fa8ae9d9ad0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11296
02246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1129602246
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1464325769
Short name T512
Test name
Test status
Simulation time 84562512512 ps
CPU time 1494.93 seconds
Started Aug 16 04:37:33 PM PDT 24
Finished Aug 16 05:02:29 PM PDT 24
Peak memory 289416 kb
Host smart-a24f3064-452c-426a-9c42-a313e475b4f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464325769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1464325769
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.917762458
Short name T679
Test name
Test status
Simulation time 146031298830 ps
CPU time 2198.32 seconds
Started Aug 16 04:37:37 PM PDT 24
Finished Aug 16 05:14:16 PM PDT 24
Peak memory 289432 kb
Host smart-46810530-e79e-4dec-9ce2-eee0d34a57ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917762458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.917762458
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.302743249
Short name T693
Test name
Test status
Simulation time 24761672055 ps
CPU time 510.41 seconds
Started Aug 16 04:37:35 PM PDT 24
Finished Aug 16 04:46:06 PM PDT 24
Peak memory 248692 kb
Host smart-4023cdc7-b5e8-4f71-ac00-33d1dac658ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302743249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.302743249
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3526827172
Short name T568
Test name
Test status
Simulation time 2971480456 ps
CPU time 48.06 seconds
Started Aug 16 04:37:45 PM PDT 24
Finished Aug 16 04:38:34 PM PDT 24
Peak memory 256164 kb
Host smart-56e06328-84d4-450c-9c10-0643a3122005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35268
27172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3526827172
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1634619930
Short name T541
Test name
Test status
Simulation time 831326092 ps
CPU time 53.18 seconds
Started Aug 16 04:37:32 PM PDT 24
Finished Aug 16 04:38:26 PM PDT 24
Peak memory 248720 kb
Host smart-9fab9c7a-e850-4f09-8421-19a768eeacc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16346
19930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1634619930
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2243285260
Short name T395
Test name
Test status
Simulation time 416695288 ps
CPU time 27.12 seconds
Started Aug 16 04:37:33 PM PDT 24
Finished Aug 16 04:38:00 PM PDT 24
Peak memory 256812 kb
Host smart-368109b0-d5a7-47ba-8ed6-1e3b92e3f441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22432
85260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2243285260
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.410875764
Short name T582
Test name
Test status
Simulation time 2893628632 ps
CPU time 43.88 seconds
Started Aug 16 04:37:35 PM PDT 24
Finished Aug 16 04:38:19 PM PDT 24
Peak memory 256776 kb
Host smart-ddca5089-89bc-4bbd-bff3-8d65ed10e2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41087
5764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.410875764
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3526600979
Short name T297
Test name
Test status
Simulation time 151185958787 ps
CPU time 2519.68 seconds
Started Aug 16 04:37:42 PM PDT 24
Finished Aug 16 05:19:42 PM PDT 24
Peak memory 289384 kb
Host smart-aa2296c8-8dae-4ad6-ab17-afea1085d8de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526600979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3526600979
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3667561160
Short name T562
Test name
Test status
Simulation time 960944443 ps
CPU time 75.71 seconds
Started Aug 16 04:37:36 PM PDT 24
Finished Aug 16 04:38:52 PM PDT 24
Peak memory 270440 kb
Host smart-2d99e298-f48f-4aca-89e5-06c1c03501b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667561160 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3667561160
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2699740263
Short name T610
Test name
Test status
Simulation time 5365253371 ps
CPU time 316.01 seconds
Started Aug 16 04:37:41 PM PDT 24
Finished Aug 16 04:42:57 PM PDT 24
Peak memory 256936 kb
Host smart-26867d0f-a0e7-4183-9d12-f6979a8f1c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26997
40263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2699740263
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2977534463
Short name T283
Test name
Test status
Simulation time 4822757401 ps
CPU time 68.14 seconds
Started Aug 16 04:37:44 PM PDT 24
Finished Aug 16 04:38:52 PM PDT 24
Peak memory 248680 kb
Host smart-0b93cb81-639a-4b52-a757-638a2f301180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29775
34463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2977534463
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.958316593
Short name T326
Test name
Test status
Simulation time 24304609563 ps
CPU time 1633.92 seconds
Started Aug 16 04:37:41 PM PDT 24
Finished Aug 16 05:04:55 PM PDT 24
Peak memory 272704 kb
Host smart-5bb06783-6a50-4693-a219-b66bb23407b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958316593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.958316593
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3996450513
Short name T654
Test name
Test status
Simulation time 295270711148 ps
CPU time 1878.94 seconds
Started Aug 16 04:37:40 PM PDT 24
Finished Aug 16 05:09:00 PM PDT 24
Peak memory 283464 kb
Host smart-0c72dc3e-8e3e-4577-bf6a-6e55973e4fa1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996450513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3996450513
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.433710617
Short name T15
Test name
Test status
Simulation time 7883679742 ps
CPU time 172.22 seconds
Started Aug 16 04:37:45 PM PDT 24
Finished Aug 16 04:40:38 PM PDT 24
Peak memory 247220 kb
Host smart-6b745367-e2f5-418a-addf-c06d31bebb7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433710617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.433710617
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3751276906
Short name T515
Test name
Test status
Simulation time 125286794 ps
CPU time 9.25 seconds
Started Aug 16 04:37:44 PM PDT 24
Finished Aug 16 04:37:53 PM PDT 24
Peak memory 248652 kb
Host smart-529c94cc-e442-4219-9288-90a479e53176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37512
76906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3751276906
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1651146122
Short name T451
Test name
Test status
Simulation time 2947449336 ps
CPU time 37.66 seconds
Started Aug 16 04:37:47 PM PDT 24
Finished Aug 16 04:38:24 PM PDT 24
Peak memory 248664 kb
Host smart-42185a81-43ac-4b11-9e4f-f6b65ef28fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16511
46122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1651146122
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2924567845
Short name T59
Test name
Test status
Simulation time 1111200189 ps
CPU time 36.7 seconds
Started Aug 16 04:37:38 PM PDT 24
Finished Aug 16 04:38:15 PM PDT 24
Peak memory 248348 kb
Host smart-16504bbb-6931-4577-9158-0cd1895086f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29245
67845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2924567845
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2869942526
Short name T637
Test name
Test status
Simulation time 726222198 ps
CPU time 51.44 seconds
Started Aug 16 04:37:44 PM PDT 24
Finished Aug 16 04:38:35 PM PDT 24
Peak memory 256864 kb
Host smart-634f7469-251b-45ba-8904-355c525c6634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28699
42526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2869942526
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1668897811
Short name T217
Test name
Test status
Simulation time 21161445140 ps
CPU time 1347.33 seconds
Started Aug 16 04:37:41 PM PDT 24
Finished Aug 16 05:00:09 PM PDT 24
Peak memory 273204 kb
Host smart-51f9de90-158f-49d4-ae50-c2d9f52b8f29
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668897811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1668897811
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.455665688
Short name T517
Test name
Test status
Simulation time 31324514086 ps
CPU time 719 seconds
Started Aug 16 04:37:37 PM PDT 24
Finished Aug 16 04:49:37 PM PDT 24
Peak memory 265032 kb
Host smart-0b959fd4-9ffe-404c-85eb-13ad41ae5c0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455665688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.455665688
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3581823027
Short name T213
Test name
Test status
Simulation time 324431323 ps
CPU time 19.04 seconds
Started Aug 16 04:37:45 PM PDT 24
Finished Aug 16 04:38:04 PM PDT 24
Peak memory 256592 kb
Host smart-5d23b879-0bf3-4954-a886-d90164acb38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35818
23027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3581823027
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.491071960
Short name T76
Test name
Test status
Simulation time 250083990 ps
CPU time 9.52 seconds
Started Aug 16 04:37:46 PM PDT 24
Finished Aug 16 04:37:56 PM PDT 24
Peak memory 248184 kb
Host smart-584d855b-d2e7-4e17-996a-df3d4716ba80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49107
1960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.491071960
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.587849538
Short name T652
Test name
Test status
Simulation time 83797896471 ps
CPU time 1471.45 seconds
Started Aug 16 04:37:41 PM PDT 24
Finished Aug 16 05:02:12 PM PDT 24
Peak memory 272896 kb
Host smart-b48a1819-b771-43ba-853f-51bac9ad8202
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587849538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.587849538
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1554536594
Short name T311
Test name
Test status
Simulation time 197837580651 ps
CPU time 410.24 seconds
Started Aug 16 04:37:41 PM PDT 24
Finished Aug 16 04:44:31 PM PDT 24
Peak memory 248724 kb
Host smart-38db48c4-b0ac-4ac3-967e-d40c7695591f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554536594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1554536594
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3427020021
Short name T705
Test name
Test status
Simulation time 5202596570 ps
CPU time 74.33 seconds
Started Aug 16 04:37:40 PM PDT 24
Finished Aug 16 04:38:55 PM PDT 24
Peak memory 256160 kb
Host smart-b3dfbc03-56cd-4609-8a56-0b619c173eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34270
20021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3427020021
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2214626010
Short name T372
Test name
Test status
Simulation time 515652585 ps
CPU time 22.53 seconds
Started Aug 16 04:37:38 PM PDT 24
Finished Aug 16 04:38:00 PM PDT 24
Peak memory 248228 kb
Host smart-34f22800-270a-4aae-9ec3-f15af8f706b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22146
26010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2214626010
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1956250417
Short name T436
Test name
Test status
Simulation time 432138262 ps
CPU time 26.16 seconds
Started Aug 16 04:37:43 PM PDT 24
Finished Aug 16 04:38:10 PM PDT 24
Peak memory 255864 kb
Host smart-9e28e474-5f36-4f6e-b364-f10accab4328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19562
50417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1956250417
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2165054928
Short name T698
Test name
Test status
Simulation time 513413813 ps
CPU time 26.38 seconds
Started Aug 16 04:37:41 PM PDT 24
Finished Aug 16 04:38:07 PM PDT 24
Peak memory 256848 kb
Host smart-ec9b3483-c735-4b7f-9f8a-b28f03f29d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21650
54928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2165054928
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3486502918
Short name T37
Test name
Test status
Simulation time 6719232416 ps
CPU time 182.78 seconds
Started Aug 16 04:37:38 PM PDT 24
Finished Aug 16 04:40:41 PM PDT 24
Peak memory 266336 kb
Host smart-95a49725-e861-4ab4-9aed-ed166f6a5670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486502918 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3486502918
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.532061507
Short name T453
Test name
Test status
Simulation time 30822514632 ps
CPU time 2035.09 seconds
Started Aug 16 04:37:44 PM PDT 24
Finished Aug 16 05:11:39 PM PDT 24
Peak memory 285048 kb
Host smart-80ce36e2-e338-4c78-923b-5189e1200cd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532061507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.532061507
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3422932985
Short name T479
Test name
Test status
Simulation time 6875897248 ps
CPU time 324.81 seconds
Started Aug 16 04:37:52 PM PDT 24
Finished Aug 16 04:43:17 PM PDT 24
Peak memory 256796 kb
Host smart-b1604610-84d2-4164-b304-b49447538c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34229
32985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3422932985
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.352833709
Short name T426
Test name
Test status
Simulation time 1018906450 ps
CPU time 14.08 seconds
Started Aug 16 04:37:44 PM PDT 24
Finished Aug 16 04:37:58 PM PDT 24
Peak memory 248052 kb
Host smart-99a7bbb6-a9b5-4db5-8d76-6bbdd9653046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35283
3709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.352833709
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.4263832109
Short name T252
Test name
Test status
Simulation time 53574083518 ps
CPU time 1644.96 seconds
Started Aug 16 04:37:46 PM PDT 24
Finished Aug 16 05:05:11 PM PDT 24
Peak memory 289144 kb
Host smart-42bf1a38-d6fe-4ff1-b698-ff225da164b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263832109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.4263832109
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1771800532
Short name T374
Test name
Test status
Simulation time 19002989372 ps
CPU time 1166.64 seconds
Started Aug 16 04:37:53 PM PDT 24
Finished Aug 16 04:57:20 PM PDT 24
Peak memory 266156 kb
Host smart-40627dac-403d-497f-b75a-1c08e6154b00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771800532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1771800532
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.460107440
Short name T322
Test name
Test status
Simulation time 31853752467 ps
CPU time 330.28 seconds
Started Aug 16 04:37:52 PM PDT 24
Finished Aug 16 04:43:22 PM PDT 24
Peak memory 247580 kb
Host smart-9bc9a2ab-ab70-4d7c-b697-1080bdeb7d4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460107440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.460107440
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1412090733
Short name T351
Test name
Test status
Simulation time 1433105343 ps
CPU time 46.77 seconds
Started Aug 16 04:37:52 PM PDT 24
Finished Aug 16 04:38:39 PM PDT 24
Peak memory 256092 kb
Host smart-5097e15f-bc31-44a0-a32f-cd814e0b2a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14120
90733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1412090733
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1159918073
Short name T25
Test name
Test status
Simulation time 783340222 ps
CPU time 14.34 seconds
Started Aug 16 04:37:52 PM PDT 24
Finished Aug 16 04:38:06 PM PDT 24
Peak memory 248120 kb
Host smart-41851243-800c-4e8e-b171-95dbedd26f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11599
18073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1159918073
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.875216803
Short name T260
Test name
Test status
Simulation time 3650630740 ps
CPU time 57.74 seconds
Started Aug 16 04:37:52 PM PDT 24
Finished Aug 16 04:38:50 PM PDT 24
Peak memory 248668 kb
Host smart-2880a6e7-f15b-40e2-a76b-7d0bb5656043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87521
6803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.875216803
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3118714315
Short name T409
Test name
Test status
Simulation time 578151135 ps
CPU time 10.85 seconds
Started Aug 16 04:37:42 PM PDT 24
Finished Aug 16 04:37:53 PM PDT 24
Peak memory 248632 kb
Host smart-81809c6c-01a3-491f-83d1-8c58677bad91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31187
14315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3118714315
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.858984189
Short name T569
Test name
Test status
Simulation time 140146413 ps
CPU time 17.22 seconds
Started Aug 16 04:37:53 PM PDT 24
Finished Aug 16 04:38:11 PM PDT 24
Peak memory 255480 kb
Host smart-3a724e36-d3c7-4c36-acea-624cb2c74be8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858984189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.858984189
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.956870598
Short name T19
Test name
Test status
Simulation time 123818117282 ps
CPU time 1685.45 seconds
Started Aug 16 04:37:52 PM PDT 24
Finished Aug 16 05:05:58 PM PDT 24
Peak memory 272900 kb
Host smart-11e99e62-dab1-4df0-8325-75c4e7e11e80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956870598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.956870598
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.935727252
Short name T547
Test name
Test status
Simulation time 2596929534 ps
CPU time 61.55 seconds
Started Aug 16 04:37:45 PM PDT 24
Finished Aug 16 04:38:47 PM PDT 24
Peak memory 256356 kb
Host smart-01b23379-2df4-4b2d-8b25-d10fcdb2897a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93572
7252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.935727252
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2138828192
Short name T607
Test name
Test status
Simulation time 967733062 ps
CPU time 56.92 seconds
Started Aug 16 04:37:52 PM PDT 24
Finished Aug 16 04:38:49 PM PDT 24
Peak memory 256228 kb
Host smart-585dc1ab-9f60-4728-9fe8-0ad8bef59681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21388
28192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2138828192
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2484712918
Short name T339
Test name
Test status
Simulation time 183160511825 ps
CPU time 2314.41 seconds
Started Aug 16 04:37:52 PM PDT 24
Finished Aug 16 05:16:27 PM PDT 24
Peak memory 288700 kb
Host smart-3fea385d-ffd4-4c6f-b755-164a6a5b04bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484712918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2484712918
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.972655429
Short name T471
Test name
Test status
Simulation time 46081140694 ps
CPU time 1432.95 seconds
Started Aug 16 04:37:45 PM PDT 24
Finished Aug 16 05:01:38 PM PDT 24
Peak memory 269168 kb
Host smart-5f35d4ea-8d3f-4e71-b07b-dec477f889ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972655429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.972655429
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.906613629
Short name T701
Test name
Test status
Simulation time 5426517518 ps
CPU time 222.1 seconds
Started Aug 16 04:37:52 PM PDT 24
Finished Aug 16 04:41:35 PM PDT 24
Peak memory 247832 kb
Host smart-95f69a9b-6fdc-4631-bcd2-105e159492b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906613629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.906613629
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.858168824
Short name T256
Test name
Test status
Simulation time 4433721681 ps
CPU time 61.22 seconds
Started Aug 16 04:37:43 PM PDT 24
Finished Aug 16 04:38:45 PM PDT 24
Peak memory 256884 kb
Host smart-4cebd846-c1da-45f3-9f5b-b1f02bb57010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85816
8824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.858168824
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4100858830
Short name T263
Test name
Test status
Simulation time 5930084216 ps
CPU time 37.53 seconds
Started Aug 16 04:37:52 PM PDT 24
Finished Aug 16 04:38:30 PM PDT 24
Peak memory 248308 kb
Host smart-cc066cf5-9d9e-4fc2-8310-f262602d73a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41008
58830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4100858830
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1952814513
Short name T557
Test name
Test status
Simulation time 196428041 ps
CPU time 4.85 seconds
Started Aug 16 04:37:53 PM PDT 24
Finished Aug 16 04:37:58 PM PDT 24
Peak memory 249020 kb
Host smart-f7a4a37e-46b6-452f-bd43-a805b1cc6616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19528
14513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1952814513
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.245193525
Short name T412
Test name
Test status
Simulation time 6889680955 ps
CPU time 50.94 seconds
Started Aug 16 04:37:46 PM PDT 24
Finished Aug 16 04:38:37 PM PDT 24
Peak memory 248728 kb
Host smart-22e988b8-d4ac-45f5-9fa2-d1d4a816ecb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24519
3525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.245193525
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3476229945
Short name T644
Test name
Test status
Simulation time 28554245610 ps
CPU time 1280.55 seconds
Started Aug 16 04:37:44 PM PDT 24
Finished Aug 16 04:59:05 PM PDT 24
Peak memory 289556 kb
Host smart-d88ee19a-923b-4e20-bf8f-374694fd06a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476229945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3476229945
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1472252444
Short name T416
Test name
Test status
Simulation time 95122523807 ps
CPU time 1385.7 seconds
Started Aug 16 04:38:01 PM PDT 24
Finished Aug 16 05:01:07 PM PDT 24
Peak memory 272420 kb
Host smart-63436fa0-c92a-4679-b73a-337783175b67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472252444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1472252444
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.4138771585
Short name T266
Test name
Test status
Simulation time 2547321425 ps
CPU time 148.66 seconds
Started Aug 16 04:37:45 PM PDT 24
Finished Aug 16 04:40:14 PM PDT 24
Peak memory 256544 kb
Host smart-4bdad7ac-027d-461d-a537-70b74f6ac8ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41387
71585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.4138771585
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.221771976
Short name T84
Test name
Test status
Simulation time 1192652987 ps
CPU time 26.11 seconds
Started Aug 16 04:38:00 PM PDT 24
Finished Aug 16 04:38:26 PM PDT 24
Peak memory 256168 kb
Host smart-24542975-f24e-4206-81fd-69542acc88cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22177
1976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.221771976
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3770487118
Short name T337
Test name
Test status
Simulation time 50394557756 ps
CPU time 1466.73 seconds
Started Aug 16 04:37:50 PM PDT 24
Finished Aug 16 05:02:17 PM PDT 24
Peak memory 273332 kb
Host smart-71ae9490-0e77-460f-b4a9-f6680c1c556e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770487118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3770487118
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.537668209
Short name T630
Test name
Test status
Simulation time 33062611498 ps
CPU time 1495.78 seconds
Started Aug 16 04:37:51 PM PDT 24
Finished Aug 16 05:02:47 PM PDT 24
Peak memory 289492 kb
Host smart-6e5cff85-3eaa-4eb4-a08e-ca0ea2241bd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537668209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.537668209
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3960354001
Short name T323
Test name
Test status
Simulation time 23604256201 ps
CPU time 382.28 seconds
Started Aug 16 04:38:00 PM PDT 24
Finished Aug 16 04:44:22 PM PDT 24
Peak memory 248644 kb
Host smart-14a3682b-ed96-4d53-bac6-fe69bcc87cd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960354001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3960354001
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1794666596
Short name T444
Test name
Test status
Simulation time 254553262 ps
CPU time 5.39 seconds
Started Aug 16 04:37:50 PM PDT 24
Finished Aug 16 04:37:56 PM PDT 24
Peak memory 248648 kb
Host smart-316e016e-bb9e-4d8d-bb2e-42afefc8418c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17946
66596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1794666596
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1576260860
Short name T277
Test name
Test status
Simulation time 231070382 ps
CPU time 8.55 seconds
Started Aug 16 04:38:00 PM PDT 24
Finished Aug 16 04:38:09 PM PDT 24
Peak memory 254352 kb
Host smart-433af81a-bacf-4f88-b785-372a71729a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15762
60860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1576260860
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3410034586
Short name T653
Test name
Test status
Simulation time 340193059 ps
CPU time 26.8 seconds
Started Aug 16 04:38:00 PM PDT 24
Finished Aug 16 04:38:27 PM PDT 24
Peak memory 247832 kb
Host smart-67850d5a-d144-47c5-915e-a5293612ec84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34100
34586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3410034586
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1372179993
Short name T393
Test name
Test status
Simulation time 647289672 ps
CPU time 18.46 seconds
Started Aug 16 04:37:50 PM PDT 24
Finished Aug 16 04:38:09 PM PDT 24
Peak memory 256952 kb
Host smart-38fcd8f2-c22b-48a8-910e-5bce4cc0d4f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13721
79993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1372179993
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.4043327290
Short name T216
Test name
Test status
Simulation time 488731340 ps
CPU time 26.94 seconds
Started Aug 16 04:37:51 PM PDT 24
Finished Aug 16 04:38:19 PM PDT 24
Peak memory 255452 kb
Host smart-a8915baa-b7b3-44cf-a1bc-a59ddca47800
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043327290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.4043327290
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.36289015
Short name T113
Test name
Test status
Simulation time 22269681481 ps
CPU time 293.86 seconds
Started Aug 16 04:38:00 PM PDT 24
Finished Aug 16 04:42:55 PM PDT 24
Peak memory 267188 kb
Host smart-b325ce95-71e4-4614-b1e7-5048cceeb06d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36289015 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.36289015
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1579766319
Short name T442
Test name
Test status
Simulation time 33318315022 ps
CPU time 1481.02 seconds
Started Aug 16 04:37:50 PM PDT 24
Finished Aug 16 05:02:32 PM PDT 24
Peak memory 286612 kb
Host smart-3168bda9-6b65-49b1-af2b-97a13d38b8d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579766319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1579766319
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3378415060
Short name T366
Test name
Test status
Simulation time 5123787710 ps
CPU time 93.42 seconds
Started Aug 16 04:37:53 PM PDT 24
Finished Aug 16 04:39:26 PM PDT 24
Peak memory 256964 kb
Host smart-97e9ac6c-27d6-49bf-9997-410ddc3cc6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33784
15060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3378415060
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.298063677
Short name T82
Test name
Test status
Simulation time 298888317 ps
CPU time 20.89 seconds
Started Aug 16 04:37:59 PM PDT 24
Finished Aug 16 04:38:20 PM PDT 24
Peak memory 256356 kb
Host smart-f352a639-5417-4b90-8c58-3fa43fad687c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29806
3677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.298063677
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.17387578
Short name T319
Test name
Test status
Simulation time 155637850551 ps
CPU time 1274.76 seconds
Started Aug 16 04:38:01 PM PDT 24
Finished Aug 16 04:59:16 PM PDT 24
Peak memory 273272 kb
Host smart-d877a6ca-b9c8-48e7-ac71-1ae9bd91b4ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17387578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.17387578
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.75161420
Short name T700
Test name
Test status
Simulation time 392627063367 ps
CPU time 1942.14 seconds
Started Aug 16 04:37:48 PM PDT 24
Finished Aug 16 05:10:10 PM PDT 24
Peak memory 272812 kb
Host smart-f9784b51-180b-4e5f-8481-6d1149db9e5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75161420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.75161420
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3022620866
Short name T617
Test name
Test status
Simulation time 17697231867 ps
CPU time 116.66 seconds
Started Aug 16 04:37:52 PM PDT 24
Finished Aug 16 04:39:49 PM PDT 24
Peak memory 248464 kb
Host smart-6bc7d2c6-f247-4889-866a-9ca935c81cca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022620866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3022620866
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2739598875
Short name T48
Test name
Test status
Simulation time 286531899 ps
CPU time 19.2 seconds
Started Aug 16 04:37:56 PM PDT 24
Finished Aug 16 04:38:15 PM PDT 24
Peak memory 256116 kb
Host smart-447b71fd-c4f8-49ad-b27e-93c12b35334e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27395
98875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2739598875
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1485838594
Short name T415
Test name
Test status
Simulation time 967241653 ps
CPU time 63.56 seconds
Started Aug 16 04:37:43 PM PDT 24
Finished Aug 16 04:38:47 PM PDT 24
Peak memory 256432 kb
Host smart-c8d379d0-f20c-4a45-94b0-174077521d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14858
38594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1485838594
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1823004916
Short name T429
Test name
Test status
Simulation time 196277949 ps
CPU time 12.54 seconds
Started Aug 16 04:38:01 PM PDT 24
Finished Aug 16 04:38:14 PM PDT 24
Peak memory 248940 kb
Host smart-7e53896d-2131-4ee8-a95b-59b1febdf689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18230
04916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1823004916
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1434971267
Short name T655
Test name
Test status
Simulation time 125498377 ps
CPU time 13.37 seconds
Started Aug 16 04:37:48 PM PDT 24
Finished Aug 16 04:38:01 PM PDT 24
Peak memory 256348 kb
Host smart-a4736f83-274a-4621-8a27-d88cefab2fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14349
71267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1434971267
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.4267926967
Short name T88
Test name
Test status
Simulation time 38279132879 ps
CPU time 2426.31 seconds
Started Aug 16 04:37:49 PM PDT 24
Finished Aug 16 05:18:15 PM PDT 24
Peak memory 289604 kb
Host smart-48b33c79-d212-4251-be93-afdba1add01a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267926967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.4267926967
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.87346466
Short name T20
Test name
Test status
Simulation time 105331071516 ps
CPU time 1580.72 seconds
Started Aug 16 04:37:58 PM PDT 24
Finished Aug 16 05:04:19 PM PDT 24
Peak memory 273412 kb
Host smart-3b7cc96c-4e72-40d1-aa4d-e34649656c89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87346466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.87346466
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1223864588
Short name T669
Test name
Test status
Simulation time 5526724191 ps
CPU time 93.56 seconds
Started Aug 16 04:37:54 PM PDT 24
Finished Aug 16 04:39:28 PM PDT 24
Peak memory 257036 kb
Host smart-c2f7f387-5af2-43f3-80e0-2f137344816b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12238
64588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1223864588
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1888517196
Short name T424
Test name
Test status
Simulation time 1407058670 ps
CPU time 33.38 seconds
Started Aug 16 04:37:52 PM PDT 24
Finished Aug 16 04:38:25 PM PDT 24
Peak memory 248628 kb
Host smart-d33d5932-99d8-4865-9660-40395c8ac43d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18885
17196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1888517196
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2346488974
Short name T221
Test name
Test status
Simulation time 229826542677 ps
CPU time 2040.83 seconds
Started Aug 16 04:37:52 PM PDT 24
Finished Aug 16 05:11:54 PM PDT 24
Peak memory 287320 kb
Host smart-41d9b589-2504-46ba-9af8-95c0f5c01001
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346488974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2346488974
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.870357751
Short name T63
Test name
Test status
Simulation time 12577741748 ps
CPU time 1053.38 seconds
Started Aug 16 04:37:54 PM PDT 24
Finished Aug 16 04:55:28 PM PDT 24
Peak memory 273388 kb
Host smart-59f77348-5be1-4aa3-8d01-cf777f6e0ccf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870357751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.870357751
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.689692973
Short name T546
Test name
Test status
Simulation time 10296900772 ps
CPU time 411.71 seconds
Started Aug 16 04:37:56 PM PDT 24
Finished Aug 16 04:44:48 PM PDT 24
Peak memory 248700 kb
Host smart-4065db72-e87b-4f5f-9539-be65810f46ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689692973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.689692973
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1267257724
Short name T572
Test name
Test status
Simulation time 826577503 ps
CPU time 19.52 seconds
Started Aug 16 04:37:53 PM PDT 24
Finished Aug 16 04:38:13 PM PDT 24
Peak memory 256008 kb
Host smart-4bd71ba2-c959-4154-a046-eeec2240bf3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12672
57724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1267257724
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.38544468
Short name T109
Test name
Test status
Simulation time 567981699 ps
CPU time 11.6 seconds
Started Aug 16 04:38:00 PM PDT 24
Finished Aug 16 04:38:11 PM PDT 24
Peak memory 247836 kb
Host smart-92ac6326-1ce1-4137-b19c-2e3acf118242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38544
468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.38544468
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.89058628
Short name T33
Test name
Test status
Simulation time 1857775583 ps
CPU time 33.04 seconds
Started Aug 16 04:37:53 PM PDT 24
Finished Aug 16 04:38:27 PM PDT 24
Peak memory 248352 kb
Host smart-3c26649b-8d6b-4f3f-a102-6dbe89a12ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89058
628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.89058628
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1959717094
Short name T599
Test name
Test status
Simulation time 260889741 ps
CPU time 16.22 seconds
Started Aug 16 04:37:53 PM PDT 24
Finished Aug 16 04:38:09 PM PDT 24
Peak memory 256312 kb
Host smart-5b595b64-6063-44d2-b43c-e6c0c53432ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19597
17094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1959717094
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1412620591
Short name T646
Test name
Test status
Simulation time 5686714631 ps
CPU time 147.6 seconds
Started Aug 16 04:37:53 PM PDT 24
Finished Aug 16 04:40:21 PM PDT 24
Peak memory 256944 kb
Host smart-ae90dc63-f631-4362-8b31-139d29583d1d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412620591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1412620591
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.210691208
Short name T233
Test name
Test status
Simulation time 4961603118 ps
CPU time 86.24 seconds
Started Aug 16 04:37:51 PM PDT 24
Finished Aug 16 04:39:18 PM PDT 24
Peak memory 266276 kb
Host smart-a435a4ff-c56a-4e9f-a724-a639c2252078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210691208 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.210691208
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1761165105
Short name T202
Test name
Test status
Simulation time 29350707 ps
CPU time 3.07 seconds
Started Aug 16 04:36:41 PM PDT 24
Finished Aug 16 04:36:44 PM PDT 24
Peak memory 248840 kb
Host smart-ca7c60fb-4c6f-431b-8529-da54c1b7cf54
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1761165105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1761165105
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2207576245
Short name T520
Test name
Test status
Simulation time 57849608921 ps
CPU time 1430.9 seconds
Started Aug 16 04:36:40 PM PDT 24
Finished Aug 16 05:00:31 PM PDT 24
Peak memory 289372 kb
Host smart-236e699b-91ee-4b67-a395-1c4cfa8b12f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207576245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2207576245
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1489592471
Short name T534
Test name
Test status
Simulation time 1194609238 ps
CPU time 40.05 seconds
Started Aug 16 04:37:11 PM PDT 24
Finished Aug 16 04:37:51 PM PDT 24
Peak memory 256408 kb
Host smart-cb9f202a-a4fe-443d-8f2c-5eaf43672d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14895
92471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1489592471
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3984182921
Short name T551
Test name
Test status
Simulation time 4987803704 ps
CPU time 41.74 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 04:37:43 PM PDT 24
Peak memory 256456 kb
Host smart-37b0eff3-b613-47f9-a9f6-ab30a9aa1019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39841
82921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3984182921
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3081417716
Short name T529
Test name
Test status
Simulation time 111235711943 ps
CPU time 1563.88 seconds
Started Aug 16 04:36:50 PM PDT 24
Finished Aug 16 05:02:54 PM PDT 24
Peak memory 273264 kb
Host smart-f74a9718-5cc1-494a-9a08-4a56bb3b1f82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081417716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3081417716
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2047122054
Short name T686
Test name
Test status
Simulation time 174354566710 ps
CPU time 1523.51 seconds
Started Aug 16 04:36:48 PM PDT 24
Finished Aug 16 05:02:12 PM PDT 24
Peak memory 272240 kb
Host smart-6fa3118f-58f6-4109-9aac-f683d4dc4c4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047122054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2047122054
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2301484446
Short name T38
Test name
Test status
Simulation time 43997685975 ps
CPU time 500.44 seconds
Started Aug 16 04:37:01 PM PDT 24
Finished Aug 16 04:45:21 PM PDT 24
Peak memory 248736 kb
Host smart-2e887e17-2cb4-44de-b0bd-526275d8d48e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301484446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2301484446
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.192087932
Short name T53
Test name
Test status
Simulation time 104546891 ps
CPU time 4.4 seconds
Started Aug 16 04:36:48 PM PDT 24
Finished Aug 16 04:36:53 PM PDT 24
Peak memory 248644 kb
Host smart-f4bb749b-e7db-4d0e-a9dc-7c7429b50134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19208
7932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.192087932
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2967428508
Short name T578
Test name
Test status
Simulation time 674000564 ps
CPU time 40.34 seconds
Started Aug 16 04:36:44 PM PDT 24
Finished Aug 16 04:37:25 PM PDT 24
Peak memory 248208 kb
Host smart-0621b02c-2640-432e-aa67-206714b57ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29674
28508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2967428508
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1849930334
Short name T571
Test name
Test status
Simulation time 742138091 ps
CPU time 20.47 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:37:14 PM PDT 24
Peak memory 248000 kb
Host smart-18700c9d-c00f-4fef-a64a-4e8f36d332b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18499
30334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1849930334
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1275328150
Short name T659
Test name
Test status
Simulation time 1997388060 ps
CPU time 16.2 seconds
Started Aug 16 04:36:52 PM PDT 24
Finished Aug 16 04:37:08 PM PDT 24
Peak memory 255300 kb
Host smart-9d20a1f1-b0fb-4017-860b-b2e2097f77df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12753
28150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1275328150
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2930818195
Short name T98
Test name
Test status
Simulation time 3752386251 ps
CPU time 482.81 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 04:45:08 PM PDT 24
Peak memory 270396 kb
Host smart-e66b9774-9a0d-4fa6-870a-b6a9239f4f25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930818195 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2930818195
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.623442976
Short name T41
Test name
Test status
Simulation time 55551147 ps
CPU time 4.09 seconds
Started Aug 16 04:36:48 PM PDT 24
Finished Aug 16 04:36:52 PM PDT 24
Peak memory 248744 kb
Host smart-92a433ae-7032-441e-a852-22a88bb8f6fb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=623442976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.623442976
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.980858521
Short name T265
Test name
Test status
Simulation time 40380080273 ps
CPU time 2494.93 seconds
Started Aug 16 04:36:50 PM PDT 24
Finished Aug 16 05:18:26 PM PDT 24
Peak memory 289380 kb
Host smart-1a6f323d-32a0-43be-be15-cfbe27e78009
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980858521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.980858521
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3003705797
Short name T369
Test name
Test status
Simulation time 701898828 ps
CPU time 19.11 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:37:13 PM PDT 24
Peak memory 248676 kb
Host smart-9ffd15e5-c28c-44e5-b319-27a7bb2c73e8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3003705797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3003705797
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.316440372
Short name T627
Test name
Test status
Simulation time 3771762711 ps
CPU time 58.47 seconds
Started Aug 16 04:36:46 PM PDT 24
Finished Aug 16 04:37:45 PM PDT 24
Peak memory 256268 kb
Host smart-336f30f3-d554-4c97-895a-db4884c9ed46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31644
0372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.316440372
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3475021499
Short name T612
Test name
Test status
Simulation time 370396768 ps
CPU time 28.24 seconds
Started Aug 16 04:36:51 PM PDT 24
Finished Aug 16 04:37:20 PM PDT 24
Peak memory 248732 kb
Host smart-714e0bf6-67b2-4dbd-9299-f6946e3cda63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34750
21499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3475021499
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.686512573
Short name T665
Test name
Test status
Simulation time 26847544961 ps
CPU time 1730.07 seconds
Started Aug 16 04:36:39 PM PDT 24
Finished Aug 16 05:05:29 PM PDT 24
Peak memory 282456 kb
Host smart-d285725c-c1c8-4333-b464-d576ec651bde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686512573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.686512573
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3103260097
Short name T417
Test name
Test status
Simulation time 56920748533 ps
CPU time 1536.72 seconds
Started Aug 16 04:36:40 PM PDT 24
Finished Aug 16 05:02:17 PM PDT 24
Peak memory 271612 kb
Host smart-67380f09-4a6b-47ca-b853-003fe445eb41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103260097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3103260097
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2494162019
Short name T611
Test name
Test status
Simulation time 6458106547 ps
CPU time 249.44 seconds
Started Aug 16 04:36:42 PM PDT 24
Finished Aug 16 04:40:51 PM PDT 24
Peak memory 247676 kb
Host smart-ebfc5708-454f-43b9-a36c-e703d7db9a82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494162019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2494162019
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1748459257
Short name T488
Test name
Test status
Simulation time 149808422 ps
CPU time 13.14 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:37:09 PM PDT 24
Peak memory 248680 kb
Host smart-6c7c29b4-8c20-4cab-b228-a8dcdc4a7d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17484
59257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1748459257
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2220727253
Short name T468
Test name
Test status
Simulation time 1662589030 ps
CPU time 7.59 seconds
Started Aug 16 04:36:35 PM PDT 24
Finished Aug 16 04:36:42 PM PDT 24
Peak memory 248124 kb
Host smart-7d8d5063-9511-49b5-8508-1cda5a3846ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22207
27253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2220727253
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.348603934
Short name T399
Test name
Test status
Simulation time 1010063421 ps
CPU time 33.96 seconds
Started Aug 16 04:36:48 PM PDT 24
Finished Aug 16 04:37:23 PM PDT 24
Peak memory 256100 kb
Host smart-e34ffa07-b137-4993-b7b8-acdb6a59c603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34860
3934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.348603934
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2126443494
Short name T591
Test name
Test status
Simulation time 2566612283 ps
CPU time 39.31 seconds
Started Aug 16 04:37:02 PM PDT 24
Finished Aug 16 04:37:42 PM PDT 24
Peak memory 248796 kb
Host smart-04ee9a3c-c5ae-4674-a023-7a7e91176754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21264
43494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2126443494
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3107899592
Short name T60
Test name
Test status
Simulation time 38450503455 ps
CPU time 2501.72 seconds
Started Aug 16 04:36:49 PM PDT 24
Finished Aug 16 05:18:31 PM PDT 24
Peak memory 289012 kb
Host smart-15a548f0-c6d7-4b89-97d5-b5076a7922d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107899592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3107899592
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.59753554
Short name T196
Test name
Test status
Simulation time 120979336 ps
CPU time 3.12 seconds
Started Aug 16 04:36:49 PM PDT 24
Finished Aug 16 04:36:57 PM PDT 24
Peak memory 248584 kb
Host smart-ae4d8208-5a3f-4360-8d5b-9b46fdd4f09e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=59753554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.59753554
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1244160447
Short name T490
Test name
Test status
Simulation time 25925018210 ps
CPU time 1764.7 seconds
Started Aug 16 04:36:53 PM PDT 24
Finished Aug 16 05:06:18 PM PDT 24
Peak memory 282264 kb
Host smart-819d9006-cde5-43eb-8f6e-5998e2979e11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244160447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1244160447
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3846367453
Short name T36
Test name
Test status
Simulation time 106150405 ps
CPU time 7.04 seconds
Started Aug 16 04:36:44 PM PDT 24
Finished Aug 16 04:36:51 PM PDT 24
Peak memory 248664 kb
Host smart-73ddb7f0-d2c2-4bf1-9429-e6a700d1f7f6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3846367453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3846367453
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2780483883
Short name T254
Test name
Test status
Simulation time 33354097694 ps
CPU time 179.66 seconds
Started Aug 16 04:36:27 PM PDT 24
Finished Aug 16 04:39:36 PM PDT 24
Peak memory 256868 kb
Host smart-9f69c163-63a3-4985-a26b-54181442f91d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27804
83883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2780483883
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1342255502
Short name T565
Test name
Test status
Simulation time 1503455352 ps
CPU time 20.92 seconds
Started Aug 16 04:36:50 PM PDT 24
Finished Aug 16 04:37:16 PM PDT 24
Peak memory 248644 kb
Host smart-0d212891-f3d7-4101-8813-77499cbfd0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13422
55502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1342255502
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3724654827
Short name T14
Test name
Test status
Simulation time 120727206124 ps
CPU time 1917.44 seconds
Started Aug 16 04:36:52 PM PDT 24
Finished Aug 16 05:08:50 PM PDT 24
Peak memory 281412 kb
Host smart-d5bc1d95-4787-4030-88dc-cf64326ae256
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724654827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3724654827
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1343633044
Short name T690
Test name
Test status
Simulation time 8606000424 ps
CPU time 181.17 seconds
Started Aug 16 04:36:34 PM PDT 24
Finished Aug 16 04:39:35 PM PDT 24
Peak memory 256684 kb
Host smart-fcdfa61d-86e7-4866-aa51-42af214bcd75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343633044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1343633044
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3985559851
Short name T580
Test name
Test status
Simulation time 238638160 ps
CPU time 5.9 seconds
Started Aug 16 04:36:46 PM PDT 24
Finished Aug 16 04:36:52 PM PDT 24
Peak memory 248588 kb
Host smart-4babd3d7-c4a7-4829-a003-7193d16afb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39855
59851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3985559851
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3772753661
Short name T674
Test name
Test status
Simulation time 62931176 ps
CPU time 5.38 seconds
Started Aug 16 04:36:39 PM PDT 24
Finished Aug 16 04:36:45 PM PDT 24
Peak memory 240004 kb
Host smart-39e79acd-d42e-4f5d-b4f2-8109dc9a27e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37727
53661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3772753661
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.95058647
Short name T295
Test name
Test status
Simulation time 4669675431 ps
CPU time 34.34 seconds
Started Aug 16 04:37:04 PM PDT 24
Finished Aug 16 04:37:39 PM PDT 24
Peak memory 249272 kb
Host smart-888e5010-f7bf-4347-8af2-05618711aeaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95058
647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.95058647
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1212420658
Short name T435
Test name
Test status
Simulation time 406177120 ps
CPU time 24.59 seconds
Started Aug 16 04:36:49 PM PDT 24
Finished Aug 16 04:37:14 PM PDT 24
Peak memory 254644 kb
Host smart-565eb064-8728-446a-bfb0-7a996d613e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12124
20658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1212420658
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.4024609684
Short name T291
Test name
Test status
Simulation time 15089417292 ps
CPU time 1549.62 seconds
Started Aug 16 04:37:07 PM PDT 24
Finished Aug 16 05:02:57 PM PDT 24
Peak memory 289060 kb
Host smart-087ecae5-21a4-416d-82e9-5f03bfaf14ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024609684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.4024609684
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.233109445
Short name T198
Test name
Test status
Simulation time 156531707 ps
CPU time 3.24 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:36:58 PM PDT 24
Peak memory 248876 kb
Host smart-b106fd0f-2fdf-46a5-92cb-540ac671150a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=233109445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.233109445
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.10367930
Short name T688
Test name
Test status
Simulation time 197794588877 ps
CPU time 2034.31 seconds
Started Aug 16 04:36:45 PM PDT 24
Finished Aug 16 05:10:40 PM PDT 24
Peak memory 273040 kb
Host smart-f7e218e6-c66e-4955-b1ba-4f9b03850514
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10367930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.10367930
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2946282130
Short name T532
Test name
Test status
Simulation time 1527757556 ps
CPU time 65.77 seconds
Started Aug 16 04:37:00 PM PDT 24
Finished Aug 16 04:38:06 PM PDT 24
Peak memory 248596 kb
Host smart-b8743235-9669-4fb2-ad34-0358ad5fb449
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2946282130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2946282130
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1055080552
Short name T363
Test name
Test status
Simulation time 708261975 ps
CPU time 22.97 seconds
Started Aug 16 04:36:50 PM PDT 24
Finished Aug 16 04:37:13 PM PDT 24
Peak memory 256104 kb
Host smart-63b8f06f-7aca-45df-909f-c02803a509dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10550
80552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1055080552
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1458377985
Short name T235
Test name
Test status
Simulation time 249771811 ps
CPU time 8.83 seconds
Started Aug 16 04:36:43 PM PDT 24
Finished Aug 16 04:36:52 PM PDT 24
Peak memory 251576 kb
Host smart-1010e84e-638e-4bee-9fdd-085872f5cbca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14583
77985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1458377985
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2345689292
Short name T635
Test name
Test status
Simulation time 47533938810 ps
CPU time 2318.88 seconds
Started Aug 16 04:36:56 PM PDT 24
Finished Aug 16 05:15:35 PM PDT 24
Peak memory 289388 kb
Host smart-4da80320-c69c-4da3-890f-55337c1247f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345689292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2345689292
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1772642168
Short name T692
Test name
Test status
Simulation time 41872809713 ps
CPU time 2249.85 seconds
Started Aug 16 04:36:58 PM PDT 24
Finished Aug 16 05:14:28 PM PDT 24
Peak memory 273412 kb
Host smart-09de9b27-719a-4843-ba99-0907d5fcbffc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772642168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1772642168
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1269849241
Short name T226
Test name
Test status
Simulation time 7476566029 ps
CPU time 286.96 seconds
Started Aug 16 04:36:56 PM PDT 24
Finished Aug 16 04:41:43 PM PDT 24
Peak memory 247672 kb
Host smart-a3b9d96c-e99e-497a-bd37-569a380c3d7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269849241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1269849241
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.4072661673
Short name T484
Test name
Test status
Simulation time 653266464 ps
CPU time 7.5 seconds
Started Aug 16 04:37:03 PM PDT 24
Finished Aug 16 04:37:11 PM PDT 24
Peak memory 248780 kb
Host smart-46a74eb4-ed82-468a-9506-646b9f5cff44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40726
61673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.4072661673
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3885768595
Short name T466
Test name
Test status
Simulation time 330916893 ps
CPU time 27.17 seconds
Started Aug 16 04:36:48 PM PDT 24
Finished Aug 16 04:37:16 PM PDT 24
Peak memory 256280 kb
Host smart-7f7186ea-7896-4323-b3fc-8756894c3abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38857
68595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3885768595
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1281524916
Short name T663
Test name
Test status
Simulation time 420440687 ps
CPU time 18.38 seconds
Started Aug 16 04:37:02 PM PDT 24
Finished Aug 16 04:37:20 PM PDT 24
Peak memory 256172 kb
Host smart-38bce984-26a7-472c-aeb8-990a4a37f38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12815
24916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1281524916
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2971062133
Short name T445
Test name
Test status
Simulation time 255285364 ps
CPU time 21.48 seconds
Started Aug 16 04:36:39 PM PDT 24
Finished Aug 16 04:37:01 PM PDT 24
Peak memory 248648 kb
Host smart-04e9b8a6-edf4-4d78-93e3-32028efd3b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29710
62133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2971062133
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.702491520
Short name T119
Test name
Test status
Simulation time 12693985176 ps
CPU time 325.88 seconds
Started Aug 16 04:36:40 PM PDT 24
Finished Aug 16 04:42:06 PM PDT 24
Peak memory 256984 kb
Host smart-db696461-f859-4c3c-8684-33b74f7e66a5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702491520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.702491520
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3759888765
Short name T205
Test name
Test status
Simulation time 69674119 ps
CPU time 4.5 seconds
Started Aug 16 04:37:05 PM PDT 24
Finished Aug 16 04:37:10 PM PDT 24
Peak memory 248860 kb
Host smart-cbf7ed20-81c8-4b06-85a0-9c5307591b92
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3759888765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3759888765
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3098426156
Short name T51
Test name
Test status
Simulation time 21024281219 ps
CPU time 1217.47 seconds
Started Aug 16 04:36:49 PM PDT 24
Finished Aug 16 04:57:07 PM PDT 24
Peak memory 281504 kb
Host smart-2fad0e39-62a3-4fd3-a608-c2ad733ccd39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098426156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3098426156
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3100658140
Short name T563
Test name
Test status
Simulation time 299581330 ps
CPU time 14.73 seconds
Started Aug 16 04:36:53 PM PDT 24
Finished Aug 16 04:37:08 PM PDT 24
Peak memory 248576 kb
Host smart-6ddd7feb-a209-4e2e-9812-77c35ac907d8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3100658140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3100658140
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2406079682
Short name T405
Test name
Test status
Simulation time 8449293491 ps
CPU time 110.01 seconds
Started Aug 16 04:36:51 PM PDT 24
Finished Aug 16 04:38:41 PM PDT 24
Peak memory 256012 kb
Host smart-346f8ab8-0a34-458e-90f8-6693c854cedd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24060
79682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2406079682
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1064226943
Short name T3
Test name
Test status
Simulation time 1228854048 ps
CPU time 17.53 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:37:12 PM PDT 24
Peak memory 248448 kb
Host smart-a4c5c68b-312d-4792-a400-6d7b4cf39fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10642
26943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1064226943
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2531659204
Short name T96
Test name
Test status
Simulation time 40776866068 ps
CPU time 2499.52 seconds
Started Aug 16 04:36:42 PM PDT 24
Finished Aug 16 05:18:22 PM PDT 24
Peak memory 289268 kb
Host smart-3a790ac5-98d4-451b-a8c6-394a076fd0be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531659204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2531659204
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3384485588
Short name T581
Test name
Test status
Simulation time 30342412081 ps
CPU time 1877.9 seconds
Started Aug 16 04:36:50 PM PDT 24
Finished Aug 16 05:08:08 PM PDT 24
Peak memory 273404 kb
Host smart-154ce3d5-e9de-44a8-a6da-2f30c3b0ce5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384485588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3384485588
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.4025687311
Short name T317
Test name
Test status
Simulation time 5700357350 ps
CPU time 238.62 seconds
Started Aug 16 04:36:48 PM PDT 24
Finished Aug 16 04:40:48 PM PDT 24
Peak memory 248692 kb
Host smart-0459545e-0ad5-4e26-92f0-1c0c3e61824d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025687311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.4025687311
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3784429198
Short name T392
Test name
Test status
Simulation time 386506386 ps
CPU time 12.16 seconds
Started Aug 16 04:36:55 PM PDT 24
Finished Aug 16 04:37:08 PM PDT 24
Peak memory 256088 kb
Host smart-ac2c3d7f-3459-4a1b-b352-d11782809a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37844
29198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3784429198
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1831193679
Short name T55
Test name
Test status
Simulation time 907185187 ps
CPU time 27.73 seconds
Started Aug 16 04:36:50 PM PDT 24
Finished Aug 16 04:37:18 PM PDT 24
Peak memory 248568 kb
Host smart-71816089-4ce5-4155-a662-1047f9d5f822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18311
93679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1831193679
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.709834527
Short name T124
Test name
Test status
Simulation time 1118647241 ps
CPU time 23.37 seconds
Started Aug 16 04:36:54 PM PDT 24
Finished Aug 16 04:37:18 PM PDT 24
Peak memory 256412 kb
Host smart-de7d5a07-15ad-4c29-8fcb-f43f1aa2612b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70983
4527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.709834527
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3712255757
Short name T400
Test name
Test status
Simulation time 789307226 ps
CPU time 12.85 seconds
Started Aug 16 04:36:51 PM PDT 24
Finished Aug 16 04:37:05 PM PDT 24
Peak memory 253696 kb
Host smart-aaf47acc-d954-4db2-a0c6-54674d0fccf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37122
55757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3712255757
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1692233091
Short name T219
Test name
Test status
Simulation time 1782341103 ps
CPU time 32.98 seconds
Started Aug 16 04:36:53 PM PDT 24
Finished Aug 16 04:37:27 PM PDT 24
Peak memory 256708 kb
Host smart-1b231142-1f91-4721-8090-9c38ff091b64
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692233091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1692233091
Directory /workspace/9.alert_handler_stress_all/latest
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