Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	60814	1			T1	2956		T4	127		T6	16
class_i[0x1]	28752	1			T1	34		T4	7		T7	10
class_i[0x2]	40963	1			T1	9		T4	697		T20	215
class_i[0x3]	50879	1			T1	20		T4	39		T7	6

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	45370	1			T1	759		T4	194		T20	6
alert[0x1]	43433	1			T1	688		T4	65		T20	196
alert[0x2]	46546	1			T1	798		T4	45		T20	5
alert[0x3]	46059	1			T1	774		T4	566		T20	8

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

181131

1

T1

3019

T4

870

T20

215

esc_ping_fail

277

1

T6

6

T15

5

T16

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	45291	1			T1	759		T4	194		T20	6
esc_integrity_fail	alert[0x1]	43364	1			T1	688		T4	65		T20	196
esc_integrity_fail	alert[0x2]	46485	1			T1	798		T4	45		T20	5
esc_integrity_fail	alert[0x3]	45991	1			T1	774		T4	566		T20	8
esc_ping_fail	alert[0x0]	79	1			T6	1		T15	2		T16	1
esc_ping_fail	alert[0x1]	69	1			T6	2		T15	1		T277	1
esc_ping_fail	alert[0x2]	61	1			T6	1		T15	1		T277	4
esc_ping_fail	alert[0x3]	68	1			T6	2		T15	1		T16	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	60742	1			T1	2956		T4	127		T6	16
esc_integrity_fail	class_i[0x1]	28683	1			T1	34		T4	7		T7	10
esc_integrity_fail	class_i[0x2]	40887	1			T1	9		T4	697		T20	215
esc_integrity_fail	class_i[0x3]	50819	1			T1	20		T4	39		T7	6
esc_ping_fail	class_i[0x0]	72	1			T15	1		T277	10		T278	9
esc_ping_fail	class_i[0x1]	69	1			T15	4		T279	10		T278	1
esc_ping_fail	class_i[0x2]	76	1			T6	6		T284	1		T103	1
esc_ping_fail	class_i[0x3]	60	1			T16	2		T103	6		T206	4