Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	606803802	0	0	630
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	606803802	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	606803802	606631418	0	0
tb.dut.CheckAccuCntDw	0	0	630	630	0	0
tb.dut.CheckEscCntDw	0	0	630	630	0	0
tb.dut.CheckNAlerts	0	0	630	630	0	0
tb.dut.CheckNClasses	0	0	630	630	0	0
tb.dut.CheckNEscSev	0	0	630	630	0	0
tb.dut.CrashdumpKnownO_A	0	0	606803802	606631418	0	0
tb.dut.EdnKnownO_A	0	0	606803802	606631418	0	0
tb.dut.EscPKnownO_A	0	0	606803802	606631418	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	606803802	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	606803802	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	606803802	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	606803802	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	606803802	80	0	0
tb.dut.IrqAKnownO_A	0	0	606803802	606631418	0	0
tb.dut.IrqBKnownO_A	0	0	606803802	606631418	0	0
tb.dut.IrqCKnownO_A	0	0	606803802	606631418	0	0
tb.dut.IrqDKnownO_A	0	0	606803802	606631418	0	0
tb.dut.TlAReadyKnownO_A	0	0	606803802	606631418	0	0
tb.dut.TlDValidKnownO_A	0	0	606803802	606631418	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	630177746	275942	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	630177746	10583	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	630177746	11317	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	630177746	10812	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	630177746	11008	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	630177746	9979	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	630177746	10575	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	630177746	10733	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	630177746	10306	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	630177746	10098	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	630177746	10612	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	630177746	9976	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	630177746	10515	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	630177746	10166	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	630177746	10982	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	630177746	10572	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	630177746	10569	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	630177746	10236	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	630177746	10240	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	630177746	10185	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	630177746	11376	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	630177746	11563	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	630177746	10278	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	630177746	10487	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	630177746	10203	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	630177746	11080	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	630177746	10260	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	630177746	10256	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	630177746	10182	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	630177746	10555	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	630177746	10663	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	630177746	10460	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	630177746	10448	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	630177746	10122	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	630177746	9949	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	630177746	10183	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	630177746	10098	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	630177746	10171	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	630177746	10569	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	630177746	10712	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	630177746	10046	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	630177746	10532	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	630177746	10232	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	630177746	9952	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	630177746	10248	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	630177746	10837	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	630177746	10213	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	630177746	10602	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	630177746	10833	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	630177746	10084	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	630177746	10033	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	630177746	10292	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	630177746	10669	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	630177746	10055	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	630177746	10533	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	630177746	10624	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	630177746	10042	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	630177746	10125	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	630177746	11171	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	630177746	9908	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	630177746	10070	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	630177746	10217	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	630177746	9957	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	630177746	10190	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	630177746	9899	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	630177746	10114	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	630177746	10616	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	630177746	10677	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	630177746	10325	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	630177746	10812	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	630177746	19134	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	630177746	10275	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	630177746	10131	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	630177746	9872	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	630177746	10805	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	630177746	10121	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	630177746	10923	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	630177746	10040	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	630177746	10706	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	606803802	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	606803802	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	606803802	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	606803802	4382	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	606803802	183791	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	606803802	313237397	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	606803802	225	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	606803802	835	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	606803802	42	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	606803802	396	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	606666094	222554898	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	606803802	906	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	606803802	884	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	606803802	869	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	606803802	854	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	606803802	660	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	606803802	79526	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	606803802	563	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	606803802	51	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	606803802	1285	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	606803802	1045	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	606665254	606594861	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	630	630	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	606803802	606631418	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	606803802	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	606803802	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	606803802	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	606803802	2495	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	606803802	164085	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	606803802	332251942	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	606803802	249	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	606803802	494	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	606803802	21	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	606803802	191	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	606666094	243878359	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	606803802	551	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	606803802	540	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	606803802	530	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	606803802	523	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	606803802	438	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	606803802	58031	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	606803802	364	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	606803802	46	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	606803802	1315	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	606803802	1075	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	606665254	606594861	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	630	630	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	606803802	606631418	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	606803802	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	606803802	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	606803802	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	606803802	2874	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	606803802	193522	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	606803802	303319353	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	606803802	257	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	606803802	503	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	606803802	30	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	606803802	214	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	606666094	220457917	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	606803802	570	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	606803802	557	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	606803802	540	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	606803802	533	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	606803802	660	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	606803802	68627	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	606803802	568	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	606803802	57	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	606803802	1216	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	606803802	976	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	606665254	606594861	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	630	630	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	606803802	606631418	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	606803802	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	606803802	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	606803802	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	606803802	3541	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	606803802	186100	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	606803802	300987123	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	606803802	216	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	606803802	508	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	606803802	24	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	606803802	233	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	606666094	233774028	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	606803802	568	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	606803802	560	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	606803802	547	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	606803802	537	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	606803802	801	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	606803802	97973	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	606803802	721	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	606803802	54	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	606803802	1284	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	606803802	1044	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	606665254	606594861	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	630	630	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	606803802	606631418	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	630177746	83502564	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	630177746	629531231	0	0
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