Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.22	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	4	40	90.91

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	4	40	90.91	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	157	1			T5	2		T69	1		T50	2
index[0x1]	176	1			T1	1		T4	2		T20	1
index[0x2]	187	1			T1	1		T4	2		T5	1
index[0x3]	193	1			T1	2		T4	2		T13	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	238	1			T1	3		T4	3		T69	1
lens_less_than_1000[1]	125	1			T20	1		T18	2		T28	2
lens_less_than_1000[2]	81	1			T1	1		T4	1		T77	3
lens_less_than_1000[3]	78	1			T218	1		T71	1		T30	1
lens_less_than_1000[4]	74	1			T13	1		T5	1		T23	1
lens_less_than_1000[5]	40	1			T4	2		T5	4		T34	1
lens_less_than_1000[6]	30	1			T27	1		T53	1		T37	1
lens_less_than_1000[7]	21	1			T30	1		T249	1		T25	3
lens_less_than_1000[8]	12	1			T250	1		T251	2		T252	1
lens_less_than_1000[9]	10	1			T58	8		T94	1		T253	1
len_2	4	1			T74	1		T91	1		T254	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	4	40	90.91	4

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9] , len_2]	--	--	2
[index[0x1]]	[lens_less_than_1000[9]]	0	1	1
[index[0x2]]	[lens_less_than_1000[7]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	57	1			T69	1		T50	2		T28	3
index[0x0]	lens_less_than_1000[1]	27	1			T28	1		T31	1		T255	1
index[0x0]	lens_less_than_1000[2]	14	1			T107	1		T41	1		T35	1
index[0x0]	lens_less_than_1000[3]	13	1			T256	1		T222	1		T257	1
index[0x0]	lens_less_than_1000[4]	19	1			T44	1		T93	1		T228	1
index[0x0]	lens_less_than_1000[5]	10	1			T5	2		T35	1		T258	1
index[0x0]	lens_less_than_1000[6]	5	1			T206	1		T251	1		T259	1
index[0x0]	lens_less_than_1000[7]	9	1			T249	1		T25	3		T222	3
index[0x0]	lens_less_than_1000[8]	3	1			T252	1		T260	1		T261	1
index[0x1]	lens_less_than_1000[0]	58	1			T1	1		T4	2		T27	1
index[0x1]	lens_less_than_1000[1]	36	1			T20	1		T262	1		T114	1
index[0x1]	lens_less_than_1000[2]	20	1			T77	3		T263	1		T41	1
index[0x1]	lens_less_than_1000[3]	19	1			T71	1		T100	1		T264	1
index[0x1]	lens_less_than_1000[4]	20	1			T27	1		T28	1		T265	1
index[0x1]	lens_less_than_1000[5]	8	1			T5	2		T227	1		T237	1
index[0x1]	lens_less_than_1000[6]	6	1			T67	1		T266	1		T267	1
index[0x1]	lens_less_than_1000[7]	4	1			T30	1		T268	1		T242	1
index[0x1]	lens_less_than_1000[8]	4	1			T251	1		T240	1		T106	1
index[0x1]	len_2	1	1			T254	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	61	1			T4	1		T50	1		T27	1
index[0x2]	lens_less_than_1000[1]	35	1			T18	1		T32	1		T203	1
index[0x2]	lens_less_than_1000[2]	25	1			T1	1		T4	1		T85	1
index[0x2]	lens_less_than_1000[3]	18	1			T218	1		T29	1		T74	1
index[0x2]	lens_less_than_1000[4]	17	1			T5	1		T80	1		T107	1
index[0x2]	lens_less_than_1000[5]	10	1			T58	1		T248	1		T231	1
index[0x2]	lens_less_than_1000[6]	8	1			T53	1		T100	2		T57	1
index[0x2]	lens_less_than_1000[8]	3	1			T250	1		T251	1		T269	1
index[0x2]	lens_less_than_1000[9]	9	1			T58	8		T94	1		-	-
index[0x2]	len_2	1	1			T270	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	62	1			T1	2		T71	1		T28	1
index[0x3]	lens_less_than_1000[1]	27	1			T18	1		T28	1		T37	1
index[0x3]	lens_less_than_1000[2]	22	1			T31	1		T35	1		T88	1
index[0x3]	lens_less_than_1000[3]	28	1			T30	1		T35	1		T54	1
index[0x3]	lens_less_than_1000[4]	18	1			T13	1		T23	1		T27	1
index[0x3]	lens_less_than_1000[5]	12	1			T4	2		T34	1		T53	1
index[0x3]	lens_less_than_1000[6]	11	1			T27	1		T37	1		T100	1
index[0x3]	lens_less_than_1000[7]	8	1			T240	2		T105	5		T271	1
index[0x3]	lens_less_than_1000[8]	2	1			T65	1		T272	1		-	-
index[0x3]	lens_less_than_1000[9]	1	1			T253	1		-	-		-	-
index[0x3]	len_2	2	1			T74	1		T91	1		-	-