Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	51	1			T1	2		T28	2		T36	1
class_index[0x1]	46	1			T22	1		T73	1		T30	1
class_index[0x2]	57	1			T23	2		T69	1		T27	1
class_index[0x3]	54	1			T1	1		T77	1		T78	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	93	1			T23	2		T69	1		T28	2
intr_timeout_cnt[1]	43	1			T78	1		T73	1		T80	1
intr_timeout_cnt[2]	20	1			T1	1		T27	1		T99	1
intr_timeout_cnt[3]	9	1			T53	1		T37	1		T223	1
intr_timeout_cnt[4]	3	1			T59	1		T224	1		T225	1
intr_timeout_cnt[5]	14	1			T1	2		T77	1		T36	2
intr_timeout_cnt[6]	6	1			T34	1		T56	1		T226	1
intr_timeout_cnt[7]	7	1			T37	1		T54	1		T227	1
intr_timeout_cnt[8]	11	1			T22	1		T100	1		T56	1
intr_timeout_cnt[9]	2	1			T176	1		T228	1		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[4]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	20	1			T28	2		T80	1		T81	2
class_index[0x0]	intr_timeout_cnt[1]	9	1			T229	1		T230	1		T231	1
class_index[0x0]	intr_timeout_cnt[2]	3	1			T94	1		T232	1		T233	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T234	2		T106	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	2	1			T224	1		T225	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	7	1			T1	2		T36	1		T235	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T226	1		T96	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T37	1		T54	1		T236	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T56	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T176	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	23	1			T30	1		T86	1		T87	1
class_index[0x1]	intr_timeout_cnt[1]	8	1			T73	1		T80	1		T85	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T83	1		T59	1		T237	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T238	1		T239	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	1	1			T59	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	1	1			T35	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	1	1			T240	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T106	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	3	1			T22	1		T61	1		T104	1
class_index[0x2]	intr_timeout_cnt[0]	28	1			T23	2		T69	1		T30	1
class_index[0x2]	intr_timeout_cnt[1]	12	1			T230	1		T102	1		T241	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T27	1		T99	1		T56	1
class_index[0x2]	intr_timeout_cnt[3]	1	1			T37	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	3	1			T111	2		T242	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	2	1			T34	1		T243	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T227	1		T244	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T223	1		T224	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	22	1			T99	1		T83	2		T86	1
class_index[0x3]	intr_timeout_cnt[1]	14	1			T78	1		T34	2		T25	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T1	1		T97	1		T245	1
class_index[0x3]	intr_timeout_cnt[3]	3	1			T53	1		T223	1		T246	1
class_index[0x3]	intr_timeout_cnt[5]	3	1			T77	1		T36	1		T247	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T56	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T234	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	5	1			T100	1		T248	1		T235	1
class_index[0x3]	intr_timeout_cnt[9]	1	1			T228	1		-	-		-	-