Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	295521	1			T1	1554		T2	59		T3	9
all_values[1]	295521	1			T1	1554		T2	59		T3	9
all_values[2]	295521	1			T1	1554		T2	59		T3	9
all_values[3]	295521	1			T1	1554		T2	59		T3	9

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

587365

1

T1

3122

T2

132

T3

18

auto[1]

594719

1

T1

3094

T2

104

T3

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

697961

1

T1

3823

T2

120

T3

20

auto[1]

484123

1

T1

2393

T2

116

T3

16

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	85483	1			T1	439		T2	18		T3	1
all_values[0]	auto[0]	auto[1]	62037	1			T1	314		T2	18		T3	1
all_values[0]	auto[1]	auto[0]	86263	1			T1	457		T2	12		T3	4
all_values[0]	auto[1]	auto[1]	61738	1			T1	344		T2	11		T3	3
all_values[1]	auto[0]	auto[0]	87473	1			T1	483		T2	23		T3	2
all_values[1]	auto[0]	auto[1]	59311	1			T1	329		T2	22		T3	2
all_values[1]	auto[1]	auto[0]	89282	1			T1	448		T2	7		T3	3
all_values[1]	auto[1]	auto[1]	59455	1			T1	294		T2	7		T3	2
all_values[2]	auto[0]	auto[0]	85550	1			T1	487		T2	11		T3	2
all_values[2]	auto[0]	auto[1]	60806	1			T1	260		T2	11		T3	1
all_values[2]	auto[1]	auto[0]	87906	1			T1	574		T2	19		T3	3
all_values[2]	auto[1]	auto[1]	61259	1			T1	233		T2	18		T3	3
all_values[3]	auto[0]	auto[0]	87215	1			T1	485		T2	15		T3	5
all_values[3]	auto[0]	auto[1]	59490	1			T1	325		T2	14		T3	4
all_values[3]	auto[1]	auto[0]	88789	1			T1	450		T2	15		T4	58
all_values[3]	auto[1]	auto[1]	60027	1			T1	294		T2	15		T4	66