Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	295521	1			T1	1554		T2	59		T3	9
all_pins[1]	295521	1			T1	1554		T2	59		T3	9
all_pins[2]	295521	1			T1	1554		T2	59		T3	9
all_pins[3]	295521	1			T1	1554		T2	59		T3	9

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	939605	1			T1	5051		T2	185		T3	28
values[0x1]	242479	1			T1	1165		T2	51		T3	8
transitions[0x0=>0x1]	159919	1			T1	802		T2	35		T3	5
transitions[0x1=>0x0]	160163	1			T1	803		T2	36		T3	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	233783	1			T1	1210		T2	48		T3	6
all_pins[0]	values[0x1]	61738	1			T1	344		T2	11		T3	3
all_pins[0]	transitions[0x0=>0x1]	61164	1			T1	339		T2	10		T3	3
all_pins[0]	transitions[0x1=>0x0]	59697	1			T1	290		T2	15		T4	61
all_pins[1]	values[0x0]	236066	1			T1	1260		T2	52		T3	7
all_pins[1]	values[0x1]	59455	1			T1	294		T2	7		T3	2
all_pins[1]	transitions[0x0=>0x1]	32530	1			T1	140		T2	4		T4	36
all_pins[1]	transitions[0x1=>0x0]	34813	1			T1	190		T2	8		T3	1
all_pins[2]	values[0x0]	234262	1			T1	1321		T2	41		T3	6
all_pins[2]	values[0x1]	61259	1			T1	233		T2	18		T3	3
all_pins[2]	transitions[0x0=>0x1]	33910	1			T1	133		T2	15		T3	2
all_pins[2]	transitions[0x1=>0x0]	32106	1			T1	194		T2	4		T3	1
all_pins[3]	values[0x0]	235494	1			T1	1260		T2	44		T3	9
all_pins[3]	values[0x1]	60027	1			T1	294		T2	15		T4	66
all_pins[3]	transitions[0x0=>0x1]	32315	1			T1	190		T2	6		T4	38
all_pins[3]	transitions[0x1=>0x0]	33547	1			T1	129		T2	9		T3	3