Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	90980	1			T1	578		T7	416		T13	523
accum_cnt_1000	202610	1			T1	1434		T20	1		T7	628
accum_cnt_100	22546	1			T1	131		T2	16		T4	25
accum_cnt_50	50536	1			T1	229		T2	31		T4	221
accum_cnt_10	153455	1			T1	257		T2	8		T3	11
accum_cnt_0	313958	1			T1	1630		T2	61		T3	5

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	219341	1			T1	1133		T2	29		T3	4
class_index[0x1]	219341	1			T1	1133		T2	29		T3	4
class_index[0x2]	219341	1			T1	1133		T2	29		T3	4
class_index[0x3]	219341	1			T1	1133		T2	29		T3	4

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23427	1			T1	271		T13	460		T32	605
class_index[0x0]	accum_cnt_1000	51927	1			T1	241		T13	584		T5	582
class_index[0x0]	accum_cnt_100	5491	1			T1	62		T4	12		T12	5
class_index[0x0]	accum_cnt_50	14776	1			T1	102		T4	69		T12	17
class_index[0x0]	accum_cnt_10	39154	1			T1	149		T4	80		T12	3
class_index[0x0]	accum_cnt_0	74220	1			T1	35		T2	29		T3	4
class_index[0x1]	accum_cnt_2000	22945	1			T1	301		T51	591		T32	544
class_index[0x1]	accum_cnt_1000	48016	1			T1	457		T22	5		T14	704
class_index[0x1]	accum_cnt_100	5048	1			T1	27		T2	10		T14	84
class_index[0x1]	accum_cnt_50	12331	1			T1	35		T2	13		T4	53
class_index[0x1]	accum_cnt_10	38302	1			T1	32		T2	3		T3	3
class_index[0x1]	accum_cnt_0	84661	1			T1	281		T2	3		T3	1
class_index[0x2]	accum_cnt_2000	20906	1			T5	137		T73	352		T33	196
class_index[0x2]	accum_cnt_1000	51856	1			T20	1		T5	430		T19	861
class_index[0x2]	accum_cnt_100	4849	1			T4	13		T12	10		T20	1
class_index[0x2]	accum_cnt_50	11429	1			T1	33		T4	34		T12	11
class_index[0x2]	accum_cnt_10	42131	1			T1	29		T3	4		T4	106
class_index[0x2]	accum_cnt_0	75193	1			T1	1071		T2	29		T4	54
class_index[0x3]	accum_cnt_2000	23702	1			T1	6		T7	416		T13	63
class_index[0x3]	accum_cnt_1000	50811	1			T1	736		T7	628		T13	952
class_index[0x3]	accum_cnt_100	7158	1			T1	42		T2	6		T7	37
class_index[0x3]	accum_cnt_50	12000	1			T1	59		T2	18		T4	65
class_index[0x3]	accum_cnt_10	33868	1			T1	47		T2	5		T3	4
class_index[0x3]	accum_cnt_0	79884	1			T1	243		T4	58		T12	4