Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2109	1			T5	11		T28	45		T277	1
alert[0x1]	6303	1			T22	2		T73	937		T30	1
alert[0x2]	6612	1			T5	12		T78	3		T73	42
alert[0x3]	11061	1			T1	68		T4	1		T28	2
alert[0x4]	1854	1			T5	4		T31	2		T277	1
alert[0x5]	3664	1			T6	1		T73	21		T36	32
alert[0x6]	6640	1			T73	88		T36	159		T262	3
alert[0x7]	4214	1			T31	1		T36	91		T80	21
alert[0x8]	1960	1			T1	7		T22	1		T14	1
alert[0x9]	3757	1			T4	6		T7	11		T15	1
alert[0xa]	3508	1			T1	9		T6	2		T5	22
alert[0xb]	1810	1			T5	9		T16	1		T36	129
alert[0xc]	3536	1			T1	32		T5	98		T31	183
alert[0xd]	9290	1			T15	1		T70	4		T73	711
alert[0xe]	6243	1			T4	1		T6	1		T277	1
alert[0xf]	1965	1			T6	1		T277	1		T278	1
alert[0x10]	5309	1			T6	2		T7	1		T28	4
alert[0x11]	4275	1			T4	1		T279	1		T278	1
alert[0x12]	7993	1			T6	1		T28	6		T73	118
alert[0x13]	8402	1			T1	42		T7	2		T15	1
alert[0x14]	1714	1			T22	3		T19	1		T73	37
alert[0x15]	2025	1			T7	1		T51	8		T37	2
alert[0x16]	6335	1			T6	1		T7	5		T5	37
alert[0x17]	3501	1			T15	1		T28	5		T30	2
alert[0x18]	9754	1			T1	33		T4	2		T7	1
alert[0x19]	3115	1			T1	83		T5	4		T28	1
alert[0x1a]	5168	1			T1	247		T28	8		T73	94
alert[0x1b]	3672	1			T5	272		T15	1		T36	733
alert[0x1c]	7777	1			T5	7		T36	1672		T80	1
alert[0x1d]	7134	1			T6	1		T14	1		T76	7
alert[0x1e]	3794	1			T13	1		T5	15		T28	8
alert[0x1f]	2964	1			T1	15		T7	3		T31	11
alert[0x20]	7203	1			T28	8		T73	121		T31	2
alert[0x21]	8243	1			T31	1		T278	1		T100	3
alert[0x22]	3640	1			T4	5		T5	15		T16	2
alert[0x23]	4831	1			T98	1		T36	138		T33	124
alert[0x24]	7415	1			T15	1		T73	11		T31	8
alert[0x25]	4209	1			T5	10		T277	1		T278	1
alert[0x26]	6058	1			T6	1		T22	1		T5	33
alert[0x27]	9797	1			T76	3		T28	1		T73	627
alert[0x28]	4392	1			T78	5		T73	634		T33	8
alert[0x29]	4600	1			T1	19		T22	64		T28	8
alert[0x2a]	3976	1			T51	2		T16	1		T73	235
alert[0x2b]	4629	1			T22	1		T5	337		T30	21
alert[0x2c]	2068	1			T14	1		T16	1		T30	49
alert[0x2d]	1661	1			T4	4		T6	1		T7	3
alert[0x2e]	11867	1			T22	1		T73	7700		T36	81
alert[0x2f]	6770	1			T73	4		T31	7		T36	7
alert[0x30]	5680	1			T5	62		T28	3		T73	325
alert[0x31]	3358	1			T5	31		T31	14		T36	22
alert[0x32]	3903	1			T28	13		T73	12		T36	59
alert[0x33]	3930	1			T6	2		T73	35		T278	2
alert[0x34]	6435	1			T6	1		T5	117		T98	6
alert[0x35]	10680	1			T1	463		T28	3		T31	25
alert[0x36]	2900	1			T5	134		T73	11		T36	71
alert[0x37]	3004	1			T5	6		T28	19		T16	1
alert[0x38]	7540	1			T28	26		T98	2		T31	2
alert[0x39]	6183	1			T28	10		T30	7		T36	25
alert[0x3a]	3671	1			T1	19		T51	3		T28	21
alert[0x3b]	13918	1			T1	2		T13	1		T5	17
alert[0x3c]	6183	1			T15	1		T73	3803		T278	1
alert[0x3d]	2854	1			T28	2		T73	7		T33	10
alert[0x3e]	5276	1			T6	1		T28	6		T73	443
alert[0x3f]	7931	1			T22	98		T28	9		T31	15
alert[0x40]	3888	1			T7	2		T98	1		T78	13

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	42776	1			T1	2		T7	25		T5	1
class_i[0x1]	87451	1			T1	1037		T4	6		T6	1
class_i[0x2]	121149	1			T4	14		T6	1		T7	1
class_i[0x3]	94775	1			T6	14		T7	3		T51	11

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

345412

1

T1

1039

T4

20

T7

29

alert_ping_fail

739

1

T6

16

T14

3

T15

8

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2099	1			T5	11		T28	45		T41	8
alert_integrity_fail	alert[0x1]	6294	1			T22	2		T73	937		T30	1
alert_integrity_fail	alert[0x2]	6603	1			T5	12		T78	3		T73	42
alert_integrity_fail	alert[0x3]	11052	1			T1	68		T4	1		T28	2
alert_integrity_fail	alert[0x4]	1840	1			T5	4		T31	2		T114	6
alert_integrity_fail	alert[0x5]	3647	1			T73	21		T36	32		T33	489
alert_integrity_fail	alert[0x6]	6629	1			T73	88		T36	159		T33	38
alert_integrity_fail	alert[0x7]	4204	1			T31	1		T36	91		T80	21
alert_integrity_fail	alert[0x8]	1943	1			T1	7		T22	1		T73	11
alert_integrity_fail	alert[0x9]	3744	1			T4	6		T7	11		T28	14
alert_integrity_fail	alert[0xa]	3479	1			T1	9		T5	22		T76	3
alert_integrity_fail	alert[0xb]	1801	1			T5	9		T36	129		T33	17
alert_integrity_fail	alert[0xc]	3526	1			T1	32		T5	98		T31	183
alert_integrity_fail	alert[0xd]	9277	1			T70	4		T73	711		T36	16
alert_integrity_fail	alert[0xe]	6233	1			T4	1		T107	8		T55	130
alert_integrity_fail	alert[0xf]	1953	1			T33	21		T87	48		T109	3
alert_integrity_fail	alert[0x10]	5293	1			T7	1		T28	4		T114	1
alert_integrity_fail	alert[0x11]	4265	1			T4	1		T55	234		T87	183
alert_integrity_fail	alert[0x12]	7982	1			T28	6		T73	118		T31	5
alert_integrity_fail	alert[0x13]	8389	1			T1	42		T7	2		T73	3521
alert_integrity_fail	alert[0x14]	1700	1			T22	3		T73	37		T33	116
alert_integrity_fail	alert[0x15]	2012	1			T7	1		T51	8		T37	2
alert_integrity_fail	alert[0x16]	6321	1			T7	5		T5	37		T73	23
alert_integrity_fail	alert[0x17]	3490	1			T28	5		T30	2		T31	1
alert_integrity_fail	alert[0x18]	9746	1			T1	33		T4	2		T7	1
alert_integrity_fail	alert[0x19]	3109	1			T1	83		T5	4		T28	1
alert_integrity_fail	alert[0x1a]	5154	1			T1	247		T28	8		T73	94
alert_integrity_fail	alert[0x1b]	3660	1			T5	272		T36	733		T54	21
alert_integrity_fail	alert[0x1c]	7758	1			T5	7		T36	1672		T80	1
alert_integrity_fail	alert[0x1d]	7121	1			T76	7		T78	24		T73	22
alert_integrity_fail	alert[0x1e]	3789	1			T13	1		T5	15		T28	8
alert_integrity_fail	alert[0x1f]	2946	1			T1	15		T7	3		T31	11
alert_integrity_fail	alert[0x20]	7194	1			T28	8		T73	121		T31	2
alert_integrity_fail	alert[0x21]	8238	1			T31	1		T100	3		T54	41
alert_integrity_fail	alert[0x22]	3624	1			T4	5		T5	15		T78	4
alert_integrity_fail	alert[0x23]	4821	1			T98	1		T36	138		T33	124
alert_integrity_fail	alert[0x24]	7407	1			T73	11		T31	8		T36	207
alert_integrity_fail	alert[0x25]	4196	1			T5	10		T55	50		T87	50
alert_integrity_fail	alert[0x26]	6047	1			T22	1		T5	33		T28	24
alert_integrity_fail	alert[0x27]	9791	1			T76	3		T28	1		T73	627
alert_integrity_fail	alert[0x28]	4375	1			T78	5		T73	634		T33	8
alert_integrity_fail	alert[0x29]	4590	1			T1	19		T22	64		T28	8
alert_integrity_fail	alert[0x2a]	3970	1			T51	2		T73	235		T31	2
alert_integrity_fail	alert[0x2b]	4620	1			T22	1		T5	337		T30	21
alert_integrity_fail	alert[0x2c]	2056	1			T30	49		T36	784		T107	1
alert_integrity_fail	alert[0x2d]	1648	1			T4	4		T7	3		T107	2
alert_integrity_fail	alert[0x2e]	11851	1			T22	1		T73	7700		T36	81
alert_integrity_fail	alert[0x2f]	6749	1			T73	4		T31	7		T36	7
alert_integrity_fail	alert[0x30]	5665	1			T5	62		T28	3		T73	325
alert_integrity_fail	alert[0x31]	3349	1			T5	31		T31	14		T36	22
alert_integrity_fail	alert[0x32]	3893	1			T28	13		T73	12		T36	59
alert_integrity_fail	alert[0x33]	3916	1			T73	35		T33	34		T55	279
alert_integrity_fail	alert[0x34]	6423	1			T5	117		T98	6		T36	498
alert_integrity_fail	alert[0x35]	10674	1			T1	463		T28	3		T31	25
alert_integrity_fail	alert[0x36]	2899	1			T5	134		T73	11		T36	71
alert_integrity_fail	alert[0x37]	2991	1			T5	6		T28	19		T78	14
alert_integrity_fail	alert[0x38]	7529	1			T28	26		T98	2		T31	2
alert_integrity_fail	alert[0x39]	6178	1			T28	10		T30	7		T36	25
alert_integrity_fail	alert[0x3a]	3660	1			T1	19		T51	3		T28	21
alert_integrity_fail	alert[0x3b]	13912	1			T1	2		T13	1		T5	17
alert_integrity_fail	alert[0x3c]	6172	1			T73	3803		T33	2		T37	25
alert_integrity_fail	alert[0x3d]	2843	1			T28	2		T73	7		T33	10
alert_integrity_fail	alert[0x3e]	5264	1			T28	6		T73	443		T33	109
alert_integrity_fail	alert[0x3f]	7924	1			T22	98		T28	9		T31	15
alert_integrity_fail	alert[0x40]	3884	1			T7	2		T98	1		T78	13
alert_ping_fail	alert[0x0]	10	1			T277	1		T103	1		T258	1
alert_ping_fail	alert[0x1]	9	1			T277	1		T279	1		T103	3
alert_ping_fail	alert[0x2]	9	1			T103	1		T280	1		T110	1
alert_ping_fail	alert[0x3]	9	1			T279	1		T278	1		T103	1
alert_ping_fail	alert[0x4]	14	1			T277	1		T279	1		T281	2
alert_ping_fail	alert[0x5]	17	1			T6	1		T279	1		T282	1
alert_ping_fail	alert[0x6]	11	1			T262	3		T47	1		T200	1
alert_ping_fail	alert[0x7]	10	1			T103	1		T110	1		T283	1
alert_ping_fail	alert[0x8]	17	1			T14	1		T15	1		T19	1
alert_ping_fail	alert[0x9]	13	1			T15	1		T278	1		T103	1
alert_ping_fail	alert[0xa]	29	1			T6	2		T16	1		T280	1
alert_ping_fail	alert[0xb]	9	1			T16	1		T279	2		T280	1
alert_ping_fail	alert[0xc]	10	1			T284	1		T281	1		T206	1
alert_ping_fail	alert[0xd]	13	1			T15	1		T279	1		T258	1
alert_ping_fail	alert[0xe]	10	1			T6	1		T277	1		T285	1
alert_ping_fail	alert[0xf]	12	1			T6	1		T277	1		T278	1
alert_ping_fail	alert[0x10]	16	1			T6	2		T277	1		T278	1
alert_ping_fail	alert[0x11]	10	1			T279	1		T278	1		T285	1
alert_ping_fail	alert[0x12]	11	1			T6	1		T279	1		T286	1
alert_ping_fail	alert[0x13]	13	1			T15	1		T273	1		T277	1
alert_ping_fail	alert[0x14]	14	1			T19	1		T262	1		T284	1
alert_ping_fail	alert[0x15]	13	1			T206	1		T287	1		T110	1
alert_ping_fail	alert[0x16]	14	1			T6	1		T277	1		T284	1
alert_ping_fail	alert[0x17]	11	1			T15	1		T212	1		T286	1
alert_ping_fail	alert[0x18]	8	1			T258	1		T281	1		T288	1
alert_ping_fail	alert[0x19]	6	1			T286	1		T289	1		T290	1
alert_ping_fail	alert[0x1a]	14	1			T277	1		T279	2		T103	2
alert_ping_fail	alert[0x1b]	12	1			T15	1		T277	1		T291	1
alert_ping_fail	alert[0x1c]	19	1			T103	1		T258	1		T291	1
alert_ping_fail	alert[0x1d]	13	1			T6	1		T14	1		T277	2
alert_ping_fail	alert[0x1e]	5	1			T292	1		T293	2		T294	1
alert_ping_fail	alert[0x1f]	18	1			T281	2		T282	1		T295	1
alert_ping_fail	alert[0x20]	9	1			T279	1		T212	1		T296	1
alert_ping_fail	alert[0x21]	5	1			T278	1		T297	2		T298	1
alert_ping_fail	alert[0x22]	16	1			T16	2		T277	1		T278	1
alert_ping_fail	alert[0x23]	10	1			T291	1		T281	1		T295	1
alert_ping_fail	alert[0x24]	8	1			T15	1		T279	1		T206	1
alert_ping_fail	alert[0x25]	13	1			T277	1		T278	1		T285	1
alert_ping_fail	alert[0x26]	11	1			T6	1		T258	1		T206	1
alert_ping_fail	alert[0x27]	6	1			T103	1		T212	1		T292	1
alert_ping_fail	alert[0x28]	17	1			T276	3		T285	1		T295	1
alert_ping_fail	alert[0x29]	10	1			T278	1		T284	1		T281	1
alert_ping_fail	alert[0x2a]	6	1			T16	1		T206	1		T296	3
alert_ping_fail	alert[0x2b]	9	1			T262	2		T279	1		T212	1
alert_ping_fail	alert[0x2c]	12	1			T14	1		T16	1		T258	1
alert_ping_fail	alert[0x2d]	13	1			T6	1		T200	1		T258	1
alert_ping_fail	alert[0x2e]	16	1			T279	1		T200	2		T103	2
alert_ping_fail	alert[0x2f]	21	1			T277	1		T279	1		T278	1
alert_ping_fail	alert[0x30]	15	1			T277	1		T284	1		T258	1
alert_ping_fail	alert[0x31]	9	1			T103	1		T281	1		T285	1
alert_ping_fail	alert[0x32]	10	1			T110	1		T290	1		T297	1
alert_ping_fail	alert[0x33]	14	1			T6	2		T278	2		T103	1
alert_ping_fail	alert[0x34]	12	1			T6	1		T281	1		T206	1
alert_ping_fail	alert[0x35]	6	1			T258	1		T286	1		T293	1
alert_ping_fail	alert[0x36]	1	1			T299	1		-	-		-	-
alert_ping_fail	alert[0x37]	13	1			T16	1		T278	2		T281	1
alert_ping_fail	alert[0x38]	11	1			T277	1		T279	1		T258	1
alert_ping_fail	alert[0x39]	5	1			T258	1		T289	1		T293	1
alert_ping_fail	alert[0x3a]	11	1			T277	1		T280	1		T288	1
alert_ping_fail	alert[0x3b]	6	1			T280	1		T288	1		T300	1
alert_ping_fail	alert[0x3c]	11	1			T15	1		T278	1		T212	1
alert_ping_fail	alert[0x3d]	11	1			T258	1		T291	1		T212	1
alert_ping_fail	alert[0x3e]	12	1			T6	1		T277	2		T279	1
alert_ping_fail	alert[0x3f]	7	1			T285	1		T286	1		T301	2
alert_ping_fail	alert[0x40]	4	1			T279	1		T280	1		T110	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	42608	1			T1	2		T7	25		T5	1
alert_integrity_fail	class_i[0x1]	87277	1			T1	1037		T4	6		T22	171
alert_integrity_fail	class_i[0x2]	121012	1			T4	14		T7	1		T13	2
alert_integrity_fail	class_i[0x3]	94515	1			T7	3		T51	11		T70	4
alert_ping_fail	class_i[0x0]	168	1			T15	1		T19	2		T16	8
alert_ping_fail	class_i[0x1]	174	1			T6	1		T15	5		T277	1
alert_ping_fail	class_i[0x2]	137	1			T6	1		T14	3		T15	2
alert_ping_fail	class_i[0x3]	260	1			T6	14		T276	4		T103	18