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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.23 99.99 98.67 97.09 100.00 100.00 99.38 99.48


Total test records in report: 835
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T775 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2049818890 Aug 17 06:33:45 PM PDT 24 Aug 17 06:33:51 PM PDT 24 348694136 ps
T168 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.923215341 Aug 17 06:33:46 PM PDT 24 Aug 17 06:33:49 PM PDT 24 83635384 ps
T776 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3218302396 Aug 17 06:33:52 PM PDT 24 Aug 17 06:33:54 PM PDT 24 10397377 ps
T777 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3058395284 Aug 17 06:33:55 PM PDT 24 Aug 17 06:34:10 PM PDT 24 218837516 ps
T778 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.563266169 Aug 17 06:33:54 PM PDT 24 Aug 17 06:34:01 PM PDT 24 354314000 ps
T779 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3857192082 Aug 17 06:33:25 PM PDT 24 Aug 17 06:33:48 PM PDT 24 168089672 ps
T780 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1783714709 Aug 17 06:33:51 PM PDT 24 Aug 17 06:33:53 PM PDT 24 11971284 ps
T781 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4100627021 Aug 17 06:34:00 PM PDT 24 Aug 17 06:34:50 PM PDT 24 712573560 ps
T782 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3735829133 Aug 17 06:33:38 PM PDT 24 Aug 17 06:33:39 PM PDT 24 6500897 ps
T783 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2939205976 Aug 17 06:33:55 PM PDT 24 Aug 17 06:33:57 PM PDT 24 7340474 ps
T784 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.335951389 Aug 17 06:33:41 PM PDT 24 Aug 17 06:33:44 PM PDT 24 34974112 ps
T785 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3860306410 Aug 17 06:33:46 PM PDT 24 Aug 17 06:33:55 PM PDT 24 430289767 ps
T786 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1752961912 Aug 17 06:33:44 PM PDT 24 Aug 17 06:34:25 PM PDT 24 505594380 ps
T787 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1641688326 Aug 17 06:33:59 PM PDT 24 Aug 17 06:34:01 PM PDT 24 9062870 ps
T788 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.4287770434 Aug 17 06:33:50 PM PDT 24 Aug 17 06:33:57 PM PDT 24 126467639 ps
T789 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1203601004 Aug 17 06:33:46 PM PDT 24 Aug 17 06:33:59 PM PDT 24 417707469 ps
T140 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3936127654 Aug 17 06:33:42 PM PDT 24 Aug 17 06:36:34 PM PDT 24 6658196498 ps
T790 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3209574807 Aug 17 06:33:36 PM PDT 24 Aug 17 06:33:41 PM PDT 24 66139863 ps
T170 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3987066633 Aug 17 06:33:55 PM PDT 24 Aug 17 06:33:58 PM PDT 24 107742891 ps
T149 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1889138671 Aug 17 06:33:49 PM PDT 24 Aug 17 06:49:13 PM PDT 24 12138303647 ps
T791 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.4048194437 Aug 17 06:33:53 PM PDT 24 Aug 17 06:33:55 PM PDT 24 40955518 ps
T792 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2778653073 Aug 17 06:33:25 PM PDT 24 Aug 17 06:33:31 PM PDT 24 139791997 ps
T793 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.103281378 Aug 17 06:33:45 PM PDT 24 Aug 17 06:33:54 PM PDT 24 515536278 ps
T794 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.210223663 Aug 17 06:33:30 PM PDT 24 Aug 17 06:33:38 PM PDT 24 357842108 ps
T795 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3026623228 Aug 17 06:33:50 PM PDT 24 Aug 17 06:33:52 PM PDT 24 9103440 ps
T796 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2138727085 Aug 17 06:33:40 PM PDT 24 Aug 17 06:33:47 PM PDT 24 200936090 ps
T174 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.864777904 Aug 17 06:33:48 PM PDT 24 Aug 17 06:33:51 PM PDT 24 61311725 ps
T147 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2949286772 Aug 17 06:33:22 PM PDT 24 Aug 17 06:35:35 PM PDT 24 7719692311 ps
T797 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1105265372 Aug 17 06:34:06 PM PDT 24 Aug 17 06:34:16 PM PDT 24 180236352 ps
T798 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3751583782 Aug 17 06:33:22 PM PDT 24 Aug 17 06:33:29 PM PDT 24 909452373 ps
T164 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1153795117 Aug 17 06:33:44 PM PDT 24 Aug 17 06:35:14 PM PDT 24 11205129325 ps
T799 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3279256677 Aug 17 06:33:52 PM PDT 24 Aug 17 06:33:54 PM PDT 24 24953894 ps
T800 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3236535384 Aug 17 06:33:56 PM PDT 24 Aug 17 06:34:07 PM PDT 24 839859477 ps
T801 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1394703988 Aug 17 06:33:18 PM PDT 24 Aug 17 06:33:19 PM PDT 24 7392492 ps
T802 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3226537835 Aug 17 06:33:46 PM PDT 24 Aug 17 06:33:48 PM PDT 24 12777975 ps
T803 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.777945245 Aug 17 06:33:24 PM PDT 24 Aug 17 06:34:01 PM PDT 24 306722160 ps
T150 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.152444026 Aug 17 06:33:26 PM PDT 24 Aug 17 06:35:03 PM PDT 24 1004636110 ps
T804 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.264161598 Aug 17 06:33:52 PM PDT 24 Aug 17 06:33:58 PM PDT 24 35213188 ps
T805 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.898331880 Aug 17 06:33:25 PM PDT 24 Aug 17 06:33:32 PM PDT 24 437892430 ps
T806 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2237985338 Aug 17 06:33:49 PM PDT 24 Aug 17 06:33:54 PM PDT 24 42274786 ps
T153 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1895648686 Aug 17 06:33:35 PM PDT 24 Aug 17 06:43:17 PM PDT 24 112029502679 ps
T166 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1300752710 Aug 17 06:33:50 PM PDT 24 Aug 17 06:34:30 PM PDT 24 318012362 ps
T134 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2852585694 Aug 17 06:33:39 PM PDT 24 Aug 17 06:44:15 PM PDT 24 17129065774 ps
T807 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.714352274 Aug 17 06:33:27 PM PDT 24 Aug 17 06:39:42 PM PDT 24 14621368523 ps
T808 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.4243504532 Aug 17 06:33:38 PM PDT 24 Aug 17 06:34:29 PM PDT 24 2835706811 ps
T809 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2109086773 Aug 17 06:33:52 PM PDT 24 Aug 17 06:34:00 PM PDT 24 170181715 ps
T810 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3601881571 Aug 17 06:33:54 PM PDT 24 Aug 17 06:34:44 PM PDT 24 2795222116 ps
T811 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3826063778 Aug 17 06:33:20 PM PDT 24 Aug 17 06:33:29 PM PDT 24 532771024 ps
T812 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3487229801 Aug 17 06:33:19 PM PDT 24 Aug 17 06:34:58 PM PDT 24 3291493676 ps
T152 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1496304354 Aug 17 06:33:51 PM PDT 24 Aug 17 06:51:24 PM PDT 24 50112787814 ps
T813 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.4223460723 Aug 17 06:33:40 PM PDT 24 Aug 17 06:33:56 PM PDT 24 2547175253 ps
T814 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.455951522 Aug 17 06:33:51 PM PDT 24 Aug 17 06:33:52 PM PDT 24 10855914 ps
T167 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3993098310 Aug 17 06:33:45 PM PDT 24 Aug 17 06:34:22 PM PDT 24 5775868211 ps
T138 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.630902730 Aug 17 06:33:20 PM PDT 24 Aug 17 06:36:30 PM PDT 24 9978157013 ps
T815 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.34693704 Aug 17 06:33:56 PM PDT 24 Aug 17 06:33:57 PM PDT 24 32715636 ps
T161 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1246644099 Aug 17 06:33:22 PM PDT 24 Aug 17 06:33:27 PM PDT 24 97087089 ps
T816 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.721325324 Aug 17 06:33:21 PM PDT 24 Aug 17 06:33:50 PM PDT 24 1644634356 ps
T817 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4156464046 Aug 17 06:33:44 PM PDT 24 Aug 17 06:34:01 PM PDT 24 269968214 ps
T818 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3363197057 Aug 17 06:33:44 PM PDT 24 Aug 17 06:33:45 PM PDT 24 10443780 ps
T819 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1297464774 Aug 17 06:33:50 PM PDT 24 Aug 17 06:33:52 PM PDT 24 12361337 ps
T820 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.63565174 Aug 17 06:33:44 PM PDT 24 Aug 17 06:33:54 PM PDT 24 267603494 ps
T821 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2184451439 Aug 17 06:33:34 PM PDT 24 Aug 17 06:37:40 PM PDT 24 4061180209 ps
T822 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2955418831 Aug 17 06:33:52 PM PDT 24 Aug 17 06:33:54 PM PDT 24 10019258 ps
T141 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1951458575 Aug 17 06:33:22 PM PDT 24 Aug 17 06:49:21 PM PDT 24 12532248676 ps
T823 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.365452333 Aug 17 06:33:51 PM PDT 24 Aug 17 06:33:59 PM PDT 24 97536523 ps
T824 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1695890135 Aug 17 06:33:48 PM PDT 24 Aug 17 06:34:02 PM PDT 24 174241599 ps
T825 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2159995504 Aug 17 06:33:42 PM PDT 24 Aug 17 06:33:50 PM PDT 24 203106769 ps
T826 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3884043517 Aug 17 06:33:35 PM PDT 24 Aug 17 06:34:17 PM PDT 24 666431879 ps
T144 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4105939890 Aug 17 06:33:45 PM PDT 24 Aug 17 06:38:28 PM PDT 24 8178932123 ps
T162 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1396426381 Aug 17 06:33:32 PM PDT 24 Aug 17 06:33:36 PM PDT 24 205126273 ps
T146 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2394974810 Aug 17 06:33:19 PM PDT 24 Aug 17 06:35:55 PM PDT 24 9743068021 ps
T827 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3374409716 Aug 17 06:33:48 PM PDT 24 Aug 17 06:33:50 PM PDT 24 22593207 ps
T333 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4234531792 Aug 17 06:33:43 PM PDT 24 Aug 17 06:39:23 PM PDT 24 4482115492 ps
T828 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3433839670 Aug 17 06:33:22 PM PDT 24 Aug 17 06:33:33 PM PDT 24 169940678 ps
T151 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.544004098 Aug 17 06:33:28 PM PDT 24 Aug 17 06:38:07 PM PDT 24 4305272446 ps
T829 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2543891610 Aug 17 06:33:49 PM PDT 24 Aug 17 06:33:51 PM PDT 24 6785388 ps
T830 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3478929525 Aug 17 06:33:49 PM PDT 24 Aug 17 06:33:55 PM PDT 24 157469792 ps
T831 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3192231019 Aug 17 06:33:41 PM PDT 24 Aug 17 06:33:42 PM PDT 24 14685511 ps
T832 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.379817120 Aug 17 06:33:29 PM PDT 24 Aug 17 06:33:36 PM PDT 24 1049693461 ps
T833 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.461690008 Aug 17 06:33:49 PM PDT 24 Aug 17 06:33:51 PM PDT 24 11715850 ps
T173 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1382302379 Aug 17 06:33:48 PM PDT 24 Aug 17 06:33:51 PM PDT 24 20518654 ps
T834 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4212161755 Aug 17 06:33:50 PM PDT 24 Aug 17 06:33:52 PM PDT 24 10137160 ps
T835 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3260356887 Aug 17 06:33:39 PM PDT 24 Aug 17 06:33:41 PM PDT 24 11577164 ps
T139 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2356172244 Aug 17 06:33:35 PM PDT 24 Aug 17 06:38:20 PM PDT 24 17816185611 ps
T129 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3203173828 Aug 17 06:33:39 PM PDT 24 Aug 17 06:49:51 PM PDT 24 55051540903 ps

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1372776579
Short name T4
Test name
Test status
Simulation time 13655038774 ps
CPU time 424.78 seconds
Started Aug 17 05:58:12 PM PDT 24
Finished Aug 17 06:05:16 PM PDT 24
Peak memory 269448 kb
Host smart-304d6435-df2d-47df-8de3-59d3eac2acd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372776579 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1372776579
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.195423905
Short name T1
Test name
Test status
Simulation time 262360421719 ps
CPU time 2161.91 seconds
Started Aug 17 05:56:05 PM PDT 24
Finished Aug 17 06:32:07 PM PDT 24
Peak memory 288768 kb
Host smart-669b1603-398b-47be-aedc-a2781f36853a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195423905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.195423905
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1044198648
Short name T8
Test name
Test status
Simulation time 1059591593 ps
CPU time 22.38 seconds
Started Aug 17 05:56:04 PM PDT 24
Finished Aug 17 05:56:26 PM PDT 24
Peak memory 269680 kb
Host smart-c1452ec2-0f57-4b5b-aef4-b3e0fbee70e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1044198648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1044198648
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3697486391
Short name T33
Test name
Test status
Simulation time 207909061470 ps
CPU time 2963.82 seconds
Started Aug 17 05:58:46 PM PDT 24
Finished Aug 17 06:48:11 PM PDT 24
Peak memory 289488 kb
Host smart-329c6b04-ac12-4c8e-9581-3ee656012052
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697486391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3697486391
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3235476157
Short name T125
Test name
Test status
Simulation time 9778957502 ps
CPU time 324.72 seconds
Started Aug 17 06:33:52 PM PDT 24
Finished Aug 17 06:39:17 PM PDT 24
Peak memory 272152 kb
Host smart-f7fa0b3f-0621-4797-b465-beb68b7724ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3235476157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3235476157
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1201436140
Short name T121
Test name
Test status
Simulation time 9145748423 ps
CPU time 604.61 seconds
Started Aug 17 06:33:29 PM PDT 24
Finished Aug 17 06:43:34 PM PDT 24
Peak memory 266588 kb
Host smart-284711d4-ebc3-4793-a990-07af0a43cfee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201436140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1201436140
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1867666853
Short name T28
Test name
Test status
Simulation time 5862748848 ps
CPU time 362.77 seconds
Started Aug 17 05:57:07 PM PDT 24
Finished Aug 17 06:03:09 PM PDT 24
Peak memory 273504 kb
Host smart-30e46061-df44-4f4f-8ab9-2366ba86c140
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867666853 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1867666853
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.970396197
Short name T115
Test name
Test status
Simulation time 1368899785 ps
CPU time 41.34 seconds
Started Aug 17 05:56:57 PM PDT 24
Finished Aug 17 05:57:38 PM PDT 24
Peak memory 248764 kb
Host smart-755236c8-c060-45b2-8e99-d42358b6ea02
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=970396197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.970396197
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2125849202
Short name T247
Test name
Test status
Simulation time 28809865700 ps
CPU time 1388.02 seconds
Started Aug 17 05:57:47 PM PDT 24
Finished Aug 17 06:20:56 PM PDT 24
Peak memory 289864 kb
Host smart-d0ee25c4-a19a-47d5-9d3b-60678f2f268e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125849202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2125849202
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1457202058
Short name T215
Test name
Test status
Simulation time 13779460712 ps
CPU time 261.31 seconds
Started Aug 17 05:56:13 PM PDT 24
Finished Aug 17 06:00:35 PM PDT 24
Peak memory 266380 kb
Host smart-d0c24250-2652-4dd1-8874-6898b02d1f5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457202058 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1457202058
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1554281631
Short name T262
Test name
Test status
Simulation time 48753015866 ps
CPU time 3068.31 seconds
Started Aug 17 05:57:12 PM PDT 24
Finished Aug 17 06:48:21 PM PDT 24
Peak memory 289876 kb
Host smart-18ca6bff-01f6-4a07-91cc-30f8c46d77d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554281631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1554281631
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1200387511
Short name T328
Test name
Test status
Simulation time 1705127996 ps
CPU time 190.37 seconds
Started Aug 17 06:33:23 PM PDT 24
Finished Aug 17 06:36:33 PM PDT 24
Peak memory 237752 kb
Host smart-48942b0a-f15e-4432-a754-1ee2545a299e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1200387511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1200387511
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.43633349
Short name T51
Test name
Test status
Simulation time 28524538997 ps
CPU time 1797.75 seconds
Started Aug 17 05:57:24 PM PDT 24
Finished Aug 17 06:27:22 PM PDT 24
Peak memory 287160 kb
Host smart-4656663f-a372-41a2-928e-51cc6f7ff33d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43633349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.43633349
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3592369634
Short name T131
Test name
Test status
Simulation time 1541145598 ps
CPU time 209.68 seconds
Started Aug 17 06:33:52 PM PDT 24
Finished Aug 17 06:37:22 PM PDT 24
Peak memory 265580 kb
Host smart-9471ad83-04dd-4c49-9d66-ac13ed7abef1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3592369634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3592369634
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.656469051
Short name T56
Test name
Test status
Simulation time 197042831802 ps
CPU time 2997.17 seconds
Started Aug 17 05:57:54 PM PDT 24
Finished Aug 17 06:47:52 PM PDT 24
Peak memory 289192 kb
Host smart-f27bd28e-6937-4441-8d89-c8fde6be5c58
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656469051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.656469051
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1561918878
Short name T117
Test name
Test status
Simulation time 3777728720 ps
CPU time 282.72 seconds
Started Aug 17 06:33:48 PM PDT 24
Finished Aug 17 06:38:30 PM PDT 24
Peak memory 265580 kb
Host smart-46c0303e-4fe5-4872-9230-baf889a52b72
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1561918878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1561918878
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.285026878
Short name T276
Test name
Test status
Simulation time 41078087530 ps
CPU time 2551.36 seconds
Started Aug 17 05:56:04 PM PDT 24
Finished Aug 17 06:38:36 PM PDT 24
Peak memory 289184 kb
Host smart-adf3a247-716a-4e5f-8a62-3f3da7deb1d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285026878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.285026878
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2435925790
Short name T258
Test name
Test status
Simulation time 25507947988 ps
CPU time 543.51 seconds
Started Aug 17 05:57:49 PM PDT 24
Finished Aug 17 06:06:53 PM PDT 24
Peak memory 248772 kb
Host smart-b5523f11-cfff-4952-8c7e-68a0af3d3ea7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435925790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2435925790
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3568578710
Short name T325
Test name
Test status
Simulation time 13030305 ps
CPU time 1.51 seconds
Started Aug 17 06:33:48 PM PDT 24
Finished Aug 17 06:33:50 PM PDT 24
Peak memory 237764 kb
Host smart-0e6ca3a8-577a-4692-817b-b8e67096ebea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3568578710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3568578710
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1889138671
Short name T149
Test name
Test status
Simulation time 12138303647 ps
CPU time 923.59 seconds
Started Aug 17 06:33:49 PM PDT 24
Finished Aug 17 06:49:13 PM PDT 24
Peak memory 265656 kb
Host smart-83135a16-8ec0-42e1-a84f-938cbec55f1a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889138671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1889138671
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3764123788
Short name T87
Test name
Test status
Simulation time 43936353428 ps
CPU time 1527 seconds
Started Aug 17 05:58:33 PM PDT 24
Finished Aug 17 06:24:00 PM PDT 24
Peak memory 273432 kb
Host smart-498017e0-a3ca-4c21-99e8-d9b6d4034d46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764123788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3764123788
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2191280161
Short name T116
Test name
Test status
Simulation time 4745215600 ps
CPU time 675.39 seconds
Started Aug 17 06:33:26 PM PDT 24
Finished Aug 17 06:44:41 PM PDT 24
Peak memory 265704 kb
Host smart-758eba96-a590-46e6-a1fb-dbe7ae4136a3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191280161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2191280161
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1885213971
Short name T206
Test name
Test status
Simulation time 39410632517 ps
CPU time 395.47 seconds
Started Aug 17 05:57:22 PM PDT 24
Finished Aug 17 06:03:58 PM PDT 24
Peak memory 248860 kb
Host smart-d1acebad-951f-49a1-9926-bad6a45bf3cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885213971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1885213971
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2281934969
Short name T307
Test name
Test status
Simulation time 20119813543 ps
CPU time 1451.54 seconds
Started Aug 17 05:59:07 PM PDT 24
Finished Aug 17 06:23:19 PM PDT 24
Peak memory 273412 kb
Host smart-55aa4ae8-d214-47a9-8705-01931504aafb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281934969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2281934969
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.275520414
Short name T278
Test name
Test status
Simulation time 70831309580 ps
CPU time 560.14 seconds
Started Aug 17 05:56:27 PM PDT 24
Finished Aug 17 06:05:48 PM PDT 24
Peak memory 248876 kb
Host smart-d4559ee2-30fa-4599-ac92-7fc10d1e2614
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275520414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.275520414
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2617536599
Short name T142
Test name
Test status
Simulation time 5482786363 ps
CPU time 271.37 seconds
Started Aug 17 06:33:49 PM PDT 24
Finished Aug 17 06:38:21 PM PDT 24
Peak memory 265620 kb
Host smart-b70a96a7-2e1c-4abd-a676-7c464b25436b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617536599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2617536599
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.65162140
Short name T252
Test name
Test status
Simulation time 176574414912 ps
CPU time 1144.66 seconds
Started Aug 17 05:59:32 PM PDT 24
Finished Aug 17 06:18:37 PM PDT 24
Peak memory 271424 kb
Host smart-9c462cf8-9277-4913-841c-1b4640e04f8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65162140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.65162140
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.73798279
Short name T156
Test name
Test status
Simulation time 63004196 ps
CPU time 2.14 seconds
Started Aug 17 06:33:24 PM PDT 24
Finished Aug 17 06:33:26 PM PDT 24
Peak memory 237604 kb
Host smart-ddbb7721-75ee-4e33-a64a-a41dcba59021
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=73798279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.73798279
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2080224256
Short name T58
Test name
Test status
Simulation time 14359397484 ps
CPU time 987.38 seconds
Started Aug 17 05:56:22 PM PDT 24
Finished Aug 17 06:12:49 PM PDT 24
Peak memory 289164 kb
Host smart-ef0cb007-c410-4631-9171-9ec2131e8a57
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080224256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2080224256
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1951458575
Short name T141
Test name
Test status
Simulation time 12532248676 ps
CPU time 959.34 seconds
Started Aug 17 06:33:22 PM PDT 24
Finished Aug 17 06:49:21 PM PDT 24
Peak memory 265660 kb
Host smart-c33af681-8bf4-4fb0-aa9a-0e2bbd6969c1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951458575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1951458575
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1181881582
Short name T172
Test name
Test status
Simulation time 588506937 ps
CPU time 8.51 seconds
Started Aug 17 06:33:21 PM PDT 24
Finished Aug 17 06:33:29 PM PDT 24
Peak memory 242792 kb
Host smart-31dc7e2f-04be-4412-8ed7-ccb21eb56fa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181881582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1181881582
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3605110628
Short name T30
Test name
Test status
Simulation time 3119473808 ps
CPU time 306.84 seconds
Started Aug 17 05:58:23 PM PDT 24
Finished Aug 17 06:03:30 PM PDT 24
Peak memory 267116 kb
Host smart-e35e427f-7eb0-402c-bf40-623e03b4d488
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605110628 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3605110628
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3534545592
Short name T280
Test name
Test status
Simulation time 5210025270 ps
CPU time 215.71 seconds
Started Aug 17 05:57:47 PM PDT 24
Finished Aug 17 06:01:23 PM PDT 24
Peak memory 248844 kb
Host smart-c1bca677-c743-48cc-935d-df96271bd886
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534545592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3534545592
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.164134392
Short name T283
Test name
Test status
Simulation time 503123532334 ps
CPU time 1354.12 seconds
Started Aug 17 05:58:33 PM PDT 24
Finished Aug 17 06:21:07 PM PDT 24
Peak memory 265028 kb
Host smart-7521369b-b666-4a50-b43e-125a31f85090
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164134392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.164134392
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2580158173
Short name T106
Test name
Test status
Simulation time 132213555165 ps
CPU time 2153.69 seconds
Started Aug 17 05:59:34 PM PDT 24
Finished Aug 17 06:35:28 PM PDT 24
Peak memory 287020 kb
Host smart-6422e749-bb48-4119-a78f-7282730f4370
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580158173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2580158173
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2852585694
Short name T134
Test name
Test status
Simulation time 17129065774 ps
CPU time 635.88 seconds
Started Aug 17 06:33:39 PM PDT 24
Finished Aug 17 06:44:15 PM PDT 24
Peak memory 265708 kb
Host smart-8ce802c6-494c-4a17-ad92-5cf3a1376f52
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852585694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2852585694
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.914889875
Short name T224
Test name
Test status
Simulation time 63593470720 ps
CPU time 3490.59 seconds
Started Aug 17 05:56:06 PM PDT 24
Finished Aug 17 06:54:17 PM PDT 24
Peak memory 298264 kb
Host smart-3d0e1992-bf16-4a38-a53c-5a7823b4bc7f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914889875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.914889875
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1447148692
Short name T294
Test name
Test status
Simulation time 64051394023 ps
CPU time 438.72 seconds
Started Aug 17 05:56:36 PM PDT 24
Finished Aug 17 06:03:55 PM PDT 24
Peak memory 248808 kb
Host smart-9a57c9ce-9f73-45fe-97e1-35c72afb4e49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447148692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1447148692
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2453904802
Short name T126
Test name
Test status
Simulation time 3769279847 ps
CPU time 295.95 seconds
Started Aug 17 06:33:26 PM PDT 24
Finished Aug 17 06:38:22 PM PDT 24
Peak memory 265680 kb
Host smart-08745f22-fdd3-4dd7-be0f-ea71a4223dbe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2453904802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2453904802
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.112511036
Short name T324
Test name
Test status
Simulation time 8701274 ps
CPU time 1.59 seconds
Started Aug 17 06:33:21 PM PDT 24
Finished Aug 17 06:33:22 PM PDT 24
Peak memory 237764 kb
Host smart-203cb92f-d28a-4813-a252-3d0bed0ee80c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=112511036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.112511036
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3024390955
Short name T311
Test name
Test status
Simulation time 125932259588 ps
CPU time 2905.92 seconds
Started Aug 17 05:55:57 PM PDT 24
Finished Aug 17 06:44:23 PM PDT 24
Peak memory 289584 kb
Host smart-a8bc9af6-0bf5-41d1-9450-fb6f3674ce48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024390955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3024390955
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.689200291
Short name T89
Test name
Test status
Simulation time 117596578711 ps
CPU time 2266.78 seconds
Started Aug 17 05:57:00 PM PDT 24
Finished Aug 17 06:34:48 PM PDT 24
Peak memory 287040 kb
Host smart-b712c474-6a30-4973-a869-df6991287259
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689200291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.689200291
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2665228243
Short name T240
Test name
Test status
Simulation time 136293204336 ps
CPU time 4250.05 seconds
Started Aug 17 05:57:23 PM PDT 24
Finished Aug 17 07:08:13 PM PDT 24
Peak memory 305928 kb
Host smart-14b54cec-9fcb-414e-8514-bb576e0e2586
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665228243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2665228243
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1164754756
Short name T237
Test name
Test status
Simulation time 54038832818 ps
CPU time 757.94 seconds
Started Aug 17 05:57:34 PM PDT 24
Finished Aug 17 06:10:12 PM PDT 24
Peak memory 265256 kb
Host smart-487efa6f-81ea-48b7-b4df-9b6b252564dc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164754756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1164754756
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.366529295
Short name T287
Test name
Test status
Simulation time 82787284568 ps
CPU time 2745 seconds
Started Aug 17 05:58:17 PM PDT 24
Finished Aug 17 06:44:03 PM PDT 24
Peak memory 289176 kb
Host smart-9955be06-e1e0-4183-8e4c-490e74578a6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366529295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.366529295
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4105939890
Short name T144
Test name
Test status
Simulation time 8178932123 ps
CPU time 283.26 seconds
Started Aug 17 06:33:45 PM PDT 24
Finished Aug 17 06:38:28 PM PDT 24
Peak memory 265644 kb
Host smart-7ecd50e4-3605-448b-8744-b435ab1543e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4105939890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.4105939890
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3443528011
Short name T336
Test name
Test status
Simulation time 63079276 ps
CPU time 9.12 seconds
Started Aug 17 06:33:38 PM PDT 24
Finished Aug 17 06:33:47 PM PDT 24
Peak memory 255424 kb
Host smart-ccb316b6-3e66-42a1-8fed-29c48f8cf4ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443528011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3443528011
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.4059233459
Short name T693
Test name
Test status
Simulation time 7309441502 ps
CPU time 290.01 seconds
Started Aug 17 05:56:04 PM PDT 24
Finished Aug 17 06:00:54 PM PDT 24
Peak memory 248820 kb
Host smart-2927b500-bd29-407f-858f-e0a069902a29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059233459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.4059233459
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.4053766736
Short name T633
Test name
Test status
Simulation time 6688160005 ps
CPU time 287.34 seconds
Started Aug 17 05:56:36 PM PDT 24
Finished Aug 17 06:01:24 PM PDT 24
Peak memory 256340 kb
Host smart-5bc0251d-81bf-494e-9c73-9faed5a8e7f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053766736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.4053766736
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1176218560
Short name T37
Test name
Test status
Simulation time 17996291102 ps
CPU time 398.14 seconds
Started Aug 17 05:58:45 PM PDT 24
Finished Aug 17 06:05:23 PM PDT 24
Peak memory 266736 kb
Host smart-4c23db6e-f6c6-4c71-a91d-96672297c21b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176218560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1176218560
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.544004098
Short name T151
Test name
Test status
Simulation time 4305272446 ps
CPU time 278.45 seconds
Started Aug 17 06:33:28 PM PDT 24
Finished Aug 17 06:38:07 PM PDT 24
Peak memory 265644 kb
Host smart-fbf15979-7416-4cba-a04d-33f626bf0d81
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544004098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.544004098
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1153270773
Short name T45
Test name
Test status
Simulation time 50460048 ps
CPU time 4.44 seconds
Started Aug 17 05:56:07 PM PDT 24
Finished Aug 17 05:56:11 PM PDT 24
Peak memory 248956 kb
Host smart-215e9202-3842-4bfa-b493-3bb130f0a3e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1153270773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1153270773
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.732699688
Short name T198
Test name
Test status
Simulation time 24983299 ps
CPU time 3.01 seconds
Started Aug 17 05:56:05 PM PDT 24
Finished Aug 17 05:56:08 PM PDT 24
Peak memory 248956 kb
Host smart-459f8e76-978a-4159-a789-f3c53753f445
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=732699688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.732699688
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.161157826
Short name T191
Test name
Test status
Simulation time 17246502 ps
CPU time 3.59 seconds
Started Aug 17 05:56:42 PM PDT 24
Finished Aug 17 05:56:46 PM PDT 24
Peak memory 249028 kb
Host smart-b5aedb7c-2b24-4be7-99c9-1ae68132c2f3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=161157826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.161157826
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2440011585
Short name T196
Test name
Test status
Simulation time 25651924 ps
CPU time 2.79 seconds
Started Aug 17 05:56:45 PM PDT 24
Finished Aug 17 05:56:48 PM PDT 24
Peak memory 249016 kb
Host smart-e910f52f-a258-41ca-8faf-47f86d3af219
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2440011585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2440011585
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2005155030
Short name T331
Test name
Test status
Simulation time 104239787 ps
CPU time 5.1 seconds
Started Aug 17 06:33:45 PM PDT 24
Finished Aug 17 06:33:50 PM PDT 24
Peak memory 238772 kb
Host smart-bbf62f39-7b6a-4702-be84-b58ae3da17ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005155030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2005155030
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.994209271
Short name T270
Test name
Test status
Simulation time 36938647157 ps
CPU time 953.33 seconds
Started Aug 17 05:56:52 PM PDT 24
Finished Aug 17 06:12:46 PM PDT 24
Peak memory 289760 kb
Host smart-d99ac4a2-6bc4-4c08-b9de-c4dbcf261c86
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994209271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.994209271
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2068292600
Short name T67
Test name
Test status
Simulation time 48154021109 ps
CPU time 1112.25 seconds
Started Aug 17 05:57:05 PM PDT 24
Finished Aug 17 06:15:37 PM PDT 24
Peak memory 284380 kb
Host smart-2aba95e9-6531-4da6-937e-91d8131860c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068292600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2068292600
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.836106496
Short name T228
Test name
Test status
Simulation time 3397873783 ps
CPU time 374.23 seconds
Started Aug 17 05:57:25 PM PDT 24
Finished Aug 17 06:03:40 PM PDT 24
Peak memory 273272 kb
Host smart-fdcdace3-7dab-4a1c-9bce-abd82651212d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836106496 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.836106496
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1029450535
Short name T499
Test name
Test status
Simulation time 81891305542 ps
CPU time 2092.37 seconds
Started Aug 17 05:57:25 PM PDT 24
Finished Aug 17 06:32:17 PM PDT 24
Peak memory 289852 kb
Host smart-c8f7d7fc-3933-4572-9592-cbdd0fce50ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029450535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1029450535
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2920073372
Short name T128
Test name
Test status
Simulation time 3217388644 ps
CPU time 128.12 seconds
Started Aug 17 06:33:44 PM PDT 24
Finished Aug 17 06:35:52 PM PDT 24
Peak memory 256916 kb
Host smart-e6add26e-4dc5-45ec-bbb1-c637ba5daef8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2920073372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2920073372
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3805979377
Short name T31
Test name
Test status
Simulation time 4388550989 ps
CPU time 560.15 seconds
Started Aug 17 05:56:09 PM PDT 24
Finished Aug 17 06:05:29 PM PDT 24
Peak memory 271748 kb
Host smart-2b03f56a-d332-4f44-a87f-d4b6866c75bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805979377 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3805979377
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1143075276
Short name T127
Test name
Test status
Simulation time 5470835118 ps
CPU time 612.06 seconds
Started Aug 17 06:33:50 PM PDT 24
Finished Aug 17 06:44:02 PM PDT 24
Peak memory 265656 kb
Host smart-e6a83748-ce32-4cf1-958f-f33816d73be3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143075276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1143075276
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.36068723
Short name T169
Test name
Test status
Simulation time 34365719 ps
CPU time 2.76 seconds
Started Aug 17 06:33:34 PM PDT 24
Finished Aug 17 06:33:37 PM PDT 24
Peak memory 237956 kb
Host smart-1a00d9d0-a55a-4dcc-9f54-95eb724e033b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=36068723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.36068723
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3147619505
Short name T750
Test name
Test status
Simulation time 13936295 ps
CPU time 1.72 seconds
Started Aug 17 06:33:37 PM PDT 24
Finished Aug 17 06:33:39 PM PDT 24
Peak memory 237784 kb
Host smart-4790ce2e-bb14-463d-b23a-caf84dd000a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3147619505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3147619505
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1863961496
Short name T244
Test name
Test status
Simulation time 2083725299 ps
CPU time 34.92 seconds
Started Aug 17 05:56:06 PM PDT 24
Finished Aug 17 05:56:41 PM PDT 24
Peak memory 249164 kb
Host smart-16eafcc1-6a7a-45cb-a84f-0e50ba7805ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18639
61496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1863961496
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.4280546770
Short name T65
Test name
Test status
Simulation time 7796002269 ps
CPU time 547.35 seconds
Started Aug 17 05:56:42 PM PDT 24
Finished Aug 17 06:05:49 PM PDT 24
Peak memory 271188 kb
Host smart-a5bb0a7f-3234-4170-b259-c88aa87b3fbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280546770 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.4280546770
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.213758502
Short name T96
Test name
Test status
Simulation time 94472933 ps
CPU time 7.78 seconds
Started Aug 17 05:56:41 PM PDT 24
Finished Aug 17 05:56:49 PM PDT 24
Peak memory 251920 kb
Host smart-9da142ba-3e9e-49f5-b9ec-ec6f8f4a8377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21375
8502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.213758502
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3151325963
Short name T103
Test name
Test status
Simulation time 41563631122 ps
CPU time 470.41 seconds
Started Aug 17 05:56:44 PM PDT 24
Finished Aug 17 06:04:35 PM PDT 24
Peak memory 248848 kb
Host smart-892d961e-5de6-4e13-a978-8c75d6f22ed5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151325963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3151325963
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3615636191
Short name T233
Test name
Test status
Simulation time 8085608670 ps
CPU time 215.77 seconds
Started Aug 17 05:56:57 PM PDT 24
Finished Aug 17 06:00:33 PM PDT 24
Peak memory 266636 kb
Host smart-9338b206-6440-4bb6-8bc1-b644c954e8eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615636191 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3615636191
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3325614568
Short name T253
Test name
Test status
Simulation time 19122385693 ps
CPU time 220.33 seconds
Started Aug 17 05:56:52 PM PDT 24
Finished Aug 17 06:00:33 PM PDT 24
Peak memory 248868 kb
Host smart-d2988547-7bd2-4cb1-b4bf-b323fd846b28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325614568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3325614568
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.890897461
Short name T254
Test name
Test status
Simulation time 24237805353 ps
CPU time 1516.57 seconds
Started Aug 17 05:56:58 PM PDT 24
Finished Aug 17 06:22:14 PM PDT 24
Peak memory 273456 kb
Host smart-aacf8c39-7a24-402b-9a1e-aa61ebf2deb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890897461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.890897461
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.902375467
Short name T111
Test name
Test status
Simulation time 4495450266 ps
CPU time 283.5 seconds
Started Aug 17 05:57:03 PM PDT 24
Finished Aug 17 06:01:47 PM PDT 24
Peak memory 267192 kb
Host smart-154b38f1-d6fd-4761-8030-f8f0451b3edd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902375467 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.902375467
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1473548071
Short name T239
Test name
Test status
Simulation time 22733543546 ps
CPU time 355.77 seconds
Started Aug 17 05:57:28 PM PDT 24
Finished Aug 17 06:03:24 PM PDT 24
Peak memory 273512 kb
Host smart-c618d4bd-a937-4ab2-a449-0f9ee571da5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473548071 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1473548071
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3402368887
Short name T74
Test name
Test status
Simulation time 2474145259 ps
CPU time 61.93 seconds
Started Aug 17 05:57:33 PM PDT 24
Finished Aug 17 05:58:35 PM PDT 24
Peak memory 256320 kb
Host smart-6e2cadfa-9e38-4b9b-a69e-95ea7b1cf097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34023
68887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3402368887
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2231911782
Short name T319
Test name
Test status
Simulation time 271994173238 ps
CPU time 1387.73 seconds
Started Aug 17 05:57:29 PM PDT 24
Finished Aug 17 06:20:37 PM PDT 24
Peak memory 288820 kb
Host smart-08cff4fb-b107-4dfd-9e30-be83a6f51868
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231911782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2231911782
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2986143984
Short name T104
Test name
Test status
Simulation time 271326896367 ps
CPU time 4186.06 seconds
Started Aug 17 05:57:33 PM PDT 24
Finished Aug 17 07:07:20 PM PDT 24
Peak memory 302036 kb
Host smart-0f2502dd-7562-4523-a788-96dcde42f160
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986143984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2986143984
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.4294752238
Short name T234
Test name
Test status
Simulation time 338348175 ps
CPU time 23.38 seconds
Started Aug 17 05:57:38 PM PDT 24
Finished Aug 17 05:58:01 PM PDT 24
Peak memory 248824 kb
Host smart-e67f6b21-2eb9-41a9-ae54-940ce4875ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42947
52238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.4294752238
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.889408710
Short name T243
Test name
Test status
Simulation time 186080166242 ps
CPU time 2140.33 seconds
Started Aug 17 05:57:39 PM PDT 24
Finished Aug 17 06:33:19 PM PDT 24
Peak memory 282100 kb
Host smart-9bb20d83-4683-4fbb-9f96-ae2d0126e0c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889408710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.889408710
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1953360832
Short name T176
Test name
Test status
Simulation time 6805587213 ps
CPU time 228.15 seconds
Started Aug 17 05:57:53 PM PDT 24
Finished Aug 17 06:01:42 PM PDT 24
Peak memory 265604 kb
Host smart-1eb4c7b6-85b8-47a3-ab55-e7e12ecea7e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953360832 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1953360832
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1651438524
Short name T35
Test name
Test status
Simulation time 14620872755 ps
CPU time 177.5 seconds
Started Aug 17 05:56:21 PM PDT 24
Finished Aug 17 05:59:19 PM PDT 24
Peak memory 265400 kb
Host smart-24c66208-6db4-4765-a3c2-f9ad4a79ab47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651438524 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1651438524
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2380240395
Short name T53
Test name
Test status
Simulation time 1745689457 ps
CPU time 39.31 seconds
Started Aug 17 05:57:57 PM PDT 24
Finished Aug 17 05:58:36 PM PDT 24
Peak memory 256424 kb
Host smart-8f53750a-6a09-42c6-85a0-7ea84f8831a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23802
40395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2380240395
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.368784563
Short name T269
Test name
Test status
Simulation time 891565459 ps
CPU time 53.21 seconds
Started Aug 17 05:58:17 PM PDT 24
Finished Aug 17 05:59:11 PM PDT 24
Peak memory 249892 kb
Host smart-1cea9102-9318-4df0-9085-b8249676adfa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368784563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.368784563
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1571462467
Short name T299
Test name
Test status
Simulation time 9925064178 ps
CPU time 427.34 seconds
Started Aug 17 05:56:20 PM PDT 24
Finished Aug 17 06:03:27 PM PDT 24
Peak memory 255884 kb
Host smart-15952606-ffcb-4c70-8927-8b6ad93440c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571462467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1571462467
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3319021278
Short name T59
Test name
Test status
Simulation time 72499167379 ps
CPU time 478.56 seconds
Started Aug 17 05:59:23 PM PDT 24
Finished Aug 17 06:07:22 PM PDT 24
Peak memory 281796 kb
Host smart-93a95b07-b0c4-479e-8d6e-b5ff12dede89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319021278 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3319021278
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.13413286
Short name T132
Test name
Test status
Simulation time 2093715633 ps
CPU time 134.26 seconds
Started Aug 17 06:33:55 PM PDT 24
Finished Aug 17 06:36:10 PM PDT 24
Peak memory 264544 kb
Host smart-3dc8c0e3-4d00-4667-973d-3752f60741d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13413286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_error
s.13413286
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3023948950
Short name T163
Test name
Test status
Simulation time 7235740720 ps
CPU time 80.92 seconds
Started Aug 17 06:33:30 PM PDT 24
Finished Aug 17 06:34:51 PM PDT 24
Peak memory 240768 kb
Host smart-c0fa7e1a-0348-4b57-81c8-32225c36daa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3023948950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3023948950
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1396426381
Short name T162
Test name
Test status
Simulation time 205126273 ps
CPU time 3.51 seconds
Started Aug 17 06:33:32 PM PDT 24
Finished Aug 17 06:33:36 PM PDT 24
Peak memory 237780 kb
Host smart-4a5289a5-aebb-4443-b736-6d5c982312e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1396426381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1396426381
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2866053584
Short name T136
Test name
Test status
Simulation time 2245971804 ps
CPU time 143.11 seconds
Started Aug 17 06:33:25 PM PDT 24
Finished Aug 17 06:35:48 PM PDT 24
Peak memory 266264 kb
Host smart-63d75f99-83a7-4f6d-8de5-928a6f77ea2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2866053584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2866053584
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.575828486
Short name T165
Test name
Test status
Simulation time 160045478 ps
CPU time 19.75 seconds
Started Aug 17 06:33:54 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 240616 kb
Host smart-afe2000b-fd2e-4be2-89d3-1e6b124c2020
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=575828486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.575828486
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1924420352
Short name T27
Test name
Test status
Simulation time 4216771669 ps
CPU time 316.28 seconds
Started Aug 17 05:56:44 PM PDT 24
Finished Aug 17 06:02:00 PM PDT 24
Peak memory 266744 kb
Host smart-00e2b052-5f44-4a83-a674-01e0efd021e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924420352 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1924420352
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1246644099
Short name T161
Test name
Test status
Simulation time 97087089 ps
CPU time 5.41 seconds
Started Aug 17 06:33:22 PM PDT 24
Finished Aug 17 06:33:27 PM PDT 24
Peak memory 237828 kb
Host smart-b392136b-c679-4da4-b424-bc39c78d09af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1246644099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1246644099
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3993098310
Short name T167
Test name
Test status
Simulation time 5775868211 ps
CPU time 36.17 seconds
Started Aug 17 06:33:45 PM PDT 24
Finished Aug 17 06:34:22 PM PDT 24
Peak memory 238928 kb
Host smart-b3be31fb-e42b-4ba0-a4e8-6d159c296878
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3993098310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3993098310
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.691319694
Short name T160
Test name
Test status
Simulation time 41302106 ps
CPU time 3.47 seconds
Started Aug 17 06:33:55 PM PDT 24
Finished Aug 17 06:33:59 PM PDT 24
Peak memory 238204 kb
Host smart-ef34e3ba-dd81-4975-a588-152b5fc792ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=691319694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.691319694
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1153795117
Short name T164
Test name
Test status
Simulation time 11205129325 ps
CPU time 89.9 seconds
Started Aug 17 06:33:44 PM PDT 24
Finished Aug 17 06:35:14 PM PDT 24
Peak memory 240744 kb
Host smart-8dda59c6-9839-455b-bd4c-a13b76e6e8ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1153795117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1153795117
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3920702971
Short name T130
Test name
Test status
Simulation time 6913117266 ps
CPU time 478.03 seconds
Started Aug 17 06:33:58 PM PDT 24
Finished Aug 17 06:41:56 PM PDT 24
Peak memory 265840 kb
Host smart-3793c667-1ae9-423e-8dba-1545dfe7856a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920702971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3920702971
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.864777904
Short name T174
Test name
Test status
Simulation time 61311725 ps
CPU time 3.18 seconds
Started Aug 17 06:33:48 PM PDT 24
Finished Aug 17 06:33:51 PM PDT 24
Peak memory 238012 kb
Host smart-928a2337-0ded-4024-86a9-c1b9775d05e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=864777904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.864777904
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1688117323
Short name T118
Test name
Test status
Simulation time 2834313063 ps
CPU time 210.45 seconds
Started Aug 17 06:33:23 PM PDT 24
Finished Aug 17 06:36:54 PM PDT 24
Peak memory 272880 kb
Host smart-c4fb2181-0933-410c-865e-bb32ed36dfb5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1688117323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1688117323
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2268705536
Short name T123
Test name
Test status
Simulation time 53599217478 ps
CPU time 538.66 seconds
Started Aug 17 06:33:37 PM PDT 24
Finished Aug 17 06:42:36 PM PDT 24
Peak memory 265872 kb
Host smart-301abc46-20ac-4a97-99f9-25b4aa5e9baf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268705536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2268705536
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2479494382
Short name T175
Test name
Test status
Simulation time 34620269 ps
CPU time 2.99 seconds
Started Aug 17 06:33:35 PM PDT 24
Finished Aug 17 06:33:38 PM PDT 24
Peak memory 238016 kb
Host smart-6bf0cb9f-764c-43b9-acd6-863b67f48ec5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2479494382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2479494382
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3987066633
Short name T170
Test name
Test status
Simulation time 107742891 ps
CPU time 2.81 seconds
Started Aug 17 06:33:55 PM PDT 24
Finished Aug 17 06:33:58 PM PDT 24
Peak memory 237588 kb
Host smart-fdbea55f-9142-478a-a253-fc3d115c8510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3987066633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3987066633
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1394424089
Short name T154
Test name
Test status
Simulation time 38770122 ps
CPU time 3.08 seconds
Started Aug 17 06:33:21 PM PDT 24
Finished Aug 17 06:33:24 PM PDT 24
Peak memory 237772 kb
Host smart-1abb97cb-dbd8-4d66-91e4-530e25d6f7f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1394424089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1394424089
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1382302379
Short name T173
Test name
Test status
Simulation time 20518654 ps
CPU time 2.35 seconds
Started Aug 17 06:33:48 PM PDT 24
Finished Aug 17 06:33:51 PM PDT 24
Peak memory 236880 kb
Host smart-ab53c994-9e03-4fed-aa7c-106f4e96977f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1382302379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1382302379
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3055467053
Short name T155
Test name
Test status
Simulation time 63610962 ps
CPU time 2.94 seconds
Started Aug 17 06:33:44 PM PDT 24
Finished Aug 17 06:33:47 PM PDT 24
Peak memory 237752 kb
Host smart-0e0674f8-1d92-449e-995e-35b935e212a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3055467053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3055467053
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.923215341
Short name T168
Test name
Test status
Simulation time 83635384 ps
CPU time 2.97 seconds
Started Aug 17 06:33:46 PM PDT 24
Finished Aug 17 06:33:49 PM PDT 24
Peak memory 237748 kb
Host smart-b9cdb5b0-d789-4ff3-9085-6bf7815563c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=923215341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.923215341
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1300752710
Short name T166
Test name
Test status
Simulation time 318012362 ps
CPU time 39.96 seconds
Started Aug 17 06:33:50 PM PDT 24
Finished Aug 17 06:34:30 PM PDT 24
Peak memory 240724 kb
Host smart-d9cbb972-7ce2-408a-aeb8-71f3a948230e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1300752710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1300752710
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1697196688
Short name T25
Test name
Test status
Simulation time 58153945654 ps
CPU time 1941.89 seconds
Started Aug 17 05:57:49 PM PDT 24
Finished Aug 17 06:30:11 PM PDT 24
Peak memory 287132 kb
Host smart-488a0b53-f81d-489d-963a-5e828dfc1c0c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697196688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1697196688
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.375339740
Short name T26
Test name
Test status
Simulation time 12552178659 ps
CPU time 71.33 seconds
Started Aug 17 05:58:55 PM PDT 24
Finished Aug 17 06:00:06 PM PDT 24
Peak memory 257032 kb
Host smart-4ca2df48-c53d-4300-aa6d-028fdf3d2c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37533
9740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.375339740
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1410309756
Short name T337
Test name
Test status
Simulation time 9570162190 ps
CPU time 75.57 seconds
Started Aug 17 06:33:56 PM PDT 24
Finished Aug 17 06:35:11 PM PDT 24
Peak memory 237684 kb
Host smart-a9003f21-c791-4594-98eb-2d59aa92627f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1410309756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1410309756
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3803557080
Short name T769
Test name
Test status
Simulation time 8822188932 ps
CPU time 503.27 seconds
Started Aug 17 06:33:26 PM PDT 24
Finished Aug 17 06:41:50 PM PDT 24
Peak memory 237800 kb
Host smart-ddf96b46-36c5-4ce7-b7f3-ff4155414ae9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3803557080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3803557080
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1087168667
Short name T158
Test name
Test status
Simulation time 230613204 ps
CPU time 5.92 seconds
Started Aug 17 06:33:20 PM PDT 24
Finished Aug 17 06:33:26 PM PDT 24
Peak memory 248876 kb
Host smart-a5b2d2ce-df6a-4d3d-ac05-3a0011f4cded
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1087168667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1087168667
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3071783104
Short name T726
Test name
Test status
Simulation time 34342298 ps
CPU time 5.28 seconds
Started Aug 17 06:33:22 PM PDT 24
Finished Aug 17 06:33:28 PM PDT 24
Peak memory 240732 kb
Host smart-036222e6-005b-4888-87cd-32447cd095ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3071783104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3071783104
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.56137761
Short name T730
Test name
Test status
Simulation time 74827645 ps
CPU time 1.34 seconds
Started Aug 17 06:33:22 PM PDT 24
Finished Aug 17 06:33:24 PM PDT 24
Peak memory 237604 kb
Host smart-bc72633a-d25d-4729-a2c1-fbadfeb0a224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=56137761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.56137761
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3942446968
Short name T767
Test name
Test status
Simulation time 589771027 ps
CPU time 12.31 seconds
Started Aug 17 06:33:30 PM PDT 24
Finished Aug 17 06:33:42 PM PDT 24
Peak memory 249112 kb
Host smart-2ca87a91-ee23-4540-96d4-91881dda2b55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3942446968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3942446968
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3487229801
Short name T812
Test name
Test status
Simulation time 3291493676 ps
CPU time 98.87 seconds
Started Aug 17 06:33:19 PM PDT 24
Finished Aug 17 06:34:58 PM PDT 24
Peak memory 265668 kb
Host smart-23305dd6-f046-46ce-b84b-025ff19c6921
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3487229801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3487229801
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3216822253
Short name T734
Test name
Test status
Simulation time 826677151 ps
CPU time 11.15 seconds
Started Aug 17 06:33:21 PM PDT 24
Finished Aug 17 06:33:32 PM PDT 24
Peak memory 246100 kb
Host smart-a1fb565c-1006-4067-be80-71b8fdcd9486
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3216822253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3216822253
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.4168560954
Short name T765
Test name
Test status
Simulation time 5629986467 ps
CPU time 152.25 seconds
Started Aug 17 06:33:20 PM PDT 24
Finished Aug 17 06:35:52 PM PDT 24
Peak memory 239652 kb
Host smart-69dc9cde-f631-452c-9f51-72bf7e9cd136
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4168560954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.4168560954
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.240161582
Short name T329
Test name
Test status
Simulation time 17126894224 ps
CPU time 271.4 seconds
Started Aug 17 06:33:21 PM PDT 24
Finished Aug 17 06:37:52 PM PDT 24
Peak memory 237816 kb
Host smart-af885d68-c9a1-45f1-a8f9-815b60924dde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=240161582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.240161582
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3276197771
Short name T178
Test name
Test status
Simulation time 104481021 ps
CPU time 9.68 seconds
Started Aug 17 06:33:51 PM PDT 24
Finished Aug 17 06:34:01 PM PDT 24
Peak memory 248904 kb
Host smart-46fb86bf-6ca4-4b9e-a57d-6b3bae2b7a76
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3276197771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3276197771
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2470235706
Short name T753
Test name
Test status
Simulation time 757916925 ps
CPU time 4.55 seconds
Started Aug 17 06:33:19 PM PDT 24
Finished Aug 17 06:33:24 PM PDT 24
Peak memory 237596 kb
Host smart-9da7ac55-1415-45d8-a5cb-e90db67b16c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2470235706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2470235706
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3884043517
Short name T826
Test name
Test status
Simulation time 666431879 ps
CPU time 42 seconds
Started Aug 17 06:33:35 PM PDT 24
Finished Aug 17 06:34:17 PM PDT 24
Peak memory 245956 kb
Host smart-f898d877-2c02-4b67-b961-299cbe2a30be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3884043517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3884043517
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.724948021
Short name T766
Test name
Test status
Simulation time 155930447 ps
CPU time 11.17 seconds
Started Aug 17 06:33:17 PM PDT 24
Finished Aug 17 06:33:28 PM PDT 24
Peak memory 254708 kb
Host smart-82988430-571b-434f-bd93-b4733e069623
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=724948021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.724948021
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.777945245
Short name T803
Test name
Test status
Simulation time 306722160 ps
CPU time 36.84 seconds
Started Aug 17 06:33:24 PM PDT 24
Finished Aug 17 06:34:01 PM PDT 24
Peak memory 248848 kb
Host smart-0b4a79dd-12e6-4368-ab2c-9a0bfd4fcc61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=777945245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.777945245
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3383472155
Short name T760
Test name
Test status
Simulation time 65641179 ps
CPU time 6.12 seconds
Started Aug 17 06:33:46 PM PDT 24
Finished Aug 17 06:33:52 PM PDT 24
Peak memory 242492 kb
Host smart-b9702fdd-aa8b-493c-a152-d781823792af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383472155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3383472155
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.405343949
Short name T220
Test name
Test status
Simulation time 249072851 ps
CPU time 5.08 seconds
Started Aug 17 06:33:29 PM PDT 24
Finished Aug 17 06:33:34 PM PDT 24
Peak memory 240688 kb
Host smart-44c1a82c-95e4-4aa0-9752-8b268209f10a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=405343949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.405343949
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2486969960
Short name T720
Test name
Test status
Simulation time 6684407 ps
CPU time 1.49 seconds
Started Aug 17 06:33:42 PM PDT 24
Finished Aug 17 06:33:44 PM PDT 24
Peak memory 237772 kb
Host smart-5c2d17cb-7bad-45a1-8572-60dca9e535c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2486969960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2486969960
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3322381340
Short name T181
Test name
Test status
Simulation time 512118842 ps
CPU time 35.39 seconds
Started Aug 17 06:33:51 PM PDT 24
Finished Aug 17 06:34:27 PM PDT 24
Peak memory 245952 kb
Host smart-d6d0d617-3419-429d-82b7-148a198024a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3322381340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3322381340
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4234531792
Short name T333
Test name
Test status
Simulation time 4482115492 ps
CPU time 340.41 seconds
Started Aug 17 06:33:43 PM PDT 24
Finished Aug 17 06:39:23 PM PDT 24
Peak memory 265628 kb
Host smart-006ba707-f0ac-4d37-802a-0279e832436f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234531792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.4234531792
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.4223460723
Short name T813
Test name
Test status
Simulation time 2547175253 ps
CPU time 16.21 seconds
Started Aug 17 06:33:40 PM PDT 24
Finished Aug 17 06:33:56 PM PDT 24
Peak memory 249076 kb
Host smart-92c86312-ce40-4d24-a244-5dd792c40266
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4223460723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.4223460723
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.210223663
Short name T794
Test name
Test status
Simulation time 357842108 ps
CPU time 8.08 seconds
Started Aug 17 06:33:30 PM PDT 24
Finished Aug 17 06:33:38 PM PDT 24
Peak memory 240592 kb
Host smart-5cb293e2-582d-4bc3-ab46-6f0806a7129f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210223663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.210223663
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2159995504
Short name T825
Test name
Test status
Simulation time 203106769 ps
CPU time 8.1 seconds
Started Aug 17 06:33:42 PM PDT 24
Finished Aug 17 06:33:50 PM PDT 24
Peak memory 236856 kb
Host smart-b22ba0df-67ac-492f-9dba-5416376a5275
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2159995504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2159995504
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3218302396
Short name T776
Test name
Test status
Simulation time 10397377 ps
CPU time 1.63 seconds
Started Aug 17 06:33:52 PM PDT 24
Finished Aug 17 06:33:54 PM PDT 24
Peak memory 237784 kb
Host smart-dc37ded9-9dc3-4ad9-bd21-915555f9274b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3218302396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3218302396
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1629537054
Short name T721
Test name
Test status
Simulation time 692447368 ps
CPU time 26.27 seconds
Started Aug 17 06:33:42 PM PDT 24
Finished Aug 17 06:34:08 PM PDT 24
Peak memory 245900 kb
Host smart-756c6f58-ff75-4c3d-b409-5d9d9d7c686d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1629537054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1629537054
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1925823513
Short name T119
Test name
Test status
Simulation time 4699249874 ps
CPU time 155.96 seconds
Started Aug 17 06:33:36 PM PDT 24
Finished Aug 17 06:36:13 PM PDT 24
Peak memory 265672 kb
Host smart-a9e0faad-3e40-41cc-88a3-02385b74a896
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1925823513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1925823513
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3854259579
Short name T133
Test name
Test status
Simulation time 59531156788 ps
CPU time 979.33 seconds
Started Aug 17 06:33:43 PM PDT 24
Finished Aug 17 06:50:02 PM PDT 24
Peak memory 265788 kb
Host smart-37d0814e-4192-4347-bfa2-e34d227226e4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854259579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3854259579
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.596021167
Short name T763
Test name
Test status
Simulation time 177926059 ps
CPU time 12.95 seconds
Started Aug 17 06:33:40 PM PDT 24
Finished Aug 17 06:33:53 PM PDT 24
Peak memory 254660 kb
Host smart-ddf397c9-e3f4-46b5-a096-a725aa172d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=596021167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.596021167
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3279256677
Short name T799
Test name
Test status
Simulation time 24953894 ps
CPU time 2.43 seconds
Started Aug 17 06:33:52 PM PDT 24
Finished Aug 17 06:33:54 PM PDT 24
Peak memory 236844 kb
Host smart-159d8ec1-b48b-4bca-a1d2-90b01985f4bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3279256677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3279256677
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3209574807
Short name T790
Test name
Test status
Simulation time 66139863 ps
CPU time 5.48 seconds
Started Aug 17 06:33:36 PM PDT 24
Finished Aug 17 06:33:41 PM PDT 24
Peak memory 240648 kb
Host smart-eda6c103-7da2-48e7-a805-bbdb67f42de1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3209574807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3209574807
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1752961912
Short name T786
Test name
Test status
Simulation time 505594380 ps
CPU time 40.52 seconds
Started Aug 17 06:33:44 PM PDT 24
Finished Aug 17 06:34:25 PM PDT 24
Peak memory 248848 kb
Host smart-f4077267-3096-4817-ae53-354d0785bd56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1752961912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1752961912
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1895648686
Short name T153
Test name
Test status
Simulation time 112029502679 ps
CPU time 582.03 seconds
Started Aug 17 06:33:35 PM PDT 24
Finished Aug 17 06:43:17 PM PDT 24
Peak memory 265532 kb
Host smart-a17a4857-ba6f-4cd5-9fe5-60058670758a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895648686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1895648686
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4156464046
Short name T817
Test name
Test status
Simulation time 269968214 ps
CPU time 17.56 seconds
Started Aug 17 06:33:44 PM PDT 24
Finished Aug 17 06:34:01 PM PDT 24
Peak memory 249964 kb
Host smart-5ee0fdab-8b4f-465d-b159-2b9eccceebc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4156464046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.4156464046
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3860306410
Short name T785
Test name
Test status
Simulation time 430289767 ps
CPU time 8.42 seconds
Started Aug 17 06:33:46 PM PDT 24
Finished Aug 17 06:33:55 PM PDT 24
Peak memory 253676 kb
Host smart-a7e20b3c-d521-4f30-a0d7-388c0294191e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860306410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3860306410
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.563266169
Short name T778
Test name
Test status
Simulation time 354314000 ps
CPU time 7.21 seconds
Started Aug 17 06:33:54 PM PDT 24
Finished Aug 17 06:34:01 PM PDT 24
Peak memory 240640 kb
Host smart-47231b9b-5395-4bba-968a-4c091c8f469d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=563266169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.563266169
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3192231019
Short name T831
Test name
Test status
Simulation time 14685511 ps
CPU time 1.55 seconds
Started Aug 17 06:33:41 PM PDT 24
Finished Aug 17 06:33:42 PM PDT 24
Peak memory 237688 kb
Host smart-6a9858fd-cc6a-4af0-9665-6ad7cd8d4832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3192231019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3192231019
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1127089954
Short name T752
Test name
Test status
Simulation time 1073301072 ps
CPU time 40.83 seconds
Started Aug 17 06:33:48 PM PDT 24
Finished Aug 17 06:34:29 PM PDT 24
Peak memory 245900 kb
Host smart-fff6a39f-b511-413e-80ff-ddc77bbaf3e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1127089954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1127089954
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1496304354
Short name T152
Test name
Test status
Simulation time 50112787814 ps
CPU time 1052.89 seconds
Started Aug 17 06:33:51 PM PDT 24
Finished Aug 17 06:51:24 PM PDT 24
Peak memory 265696 kb
Host smart-34ff30de-67ce-40dd-86ca-9228dbd38820
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496304354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1496304354
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.63565174
Short name T820
Test name
Test status
Simulation time 267603494 ps
CPU time 9.5 seconds
Started Aug 17 06:33:44 PM PDT 24
Finished Aug 17 06:33:54 PM PDT 24
Peak memory 248956 kb
Host smart-77d09487-fd50-47de-a786-5e09460535e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=63565174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.63565174
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1105265372
Short name T797
Test name
Test status
Simulation time 180236352 ps
CPU time 9.42 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:16 PM PDT 24
Peak memory 257044 kb
Host smart-9614adf3-0ffa-4422-b16a-16e08ffb412b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105265372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1105265372
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2237985338
Short name T806
Test name
Test status
Simulation time 42274786 ps
CPU time 5.36 seconds
Started Aug 17 06:33:49 PM PDT 24
Finished Aug 17 06:33:54 PM PDT 24
Peak memory 237976 kb
Host smart-3cb8c10c-8a56-4fd5-9d47-2622adb27e1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2237985338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2237985338
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2086292773
Short name T213
Test name
Test status
Simulation time 8883133 ps
CPU time 1.63 seconds
Started Aug 17 06:33:51 PM PDT 24
Finished Aug 17 06:33:52 PM PDT 24
Peak memory 237768 kb
Host smart-8241b186-c6d5-4480-b988-a8b0befc0783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2086292773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2086292773
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2187360957
Short name T716
Test name
Test status
Simulation time 877999746 ps
CPU time 19.93 seconds
Started Aug 17 06:34:00 PM PDT 24
Finished Aug 17 06:34:20 PM PDT 24
Peak memory 248876 kb
Host smart-da4f0eb2-a616-48ce-a571-74b73be13084
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2187360957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2187360957
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2356172244
Short name T139
Test name
Test status
Simulation time 17816185611 ps
CPU time 285.14 seconds
Started Aug 17 06:33:35 PM PDT 24
Finished Aug 17 06:38:20 PM PDT 24
Peak memory 265640 kb
Host smart-837f60f7-a489-45d3-b615-21f4baa34d0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2356172244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2356172244
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2991354759
Short name T135
Test name
Test status
Simulation time 7915275533 ps
CPU time 515.64 seconds
Started Aug 17 06:33:35 PM PDT 24
Finished Aug 17 06:42:11 PM PDT 24
Peak memory 265632 kb
Host smart-2e5e04de-a134-4725-9c5e-87c40976cf9a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991354759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2991354759
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3413541265
Short name T717
Test name
Test status
Simulation time 739708375 ps
CPU time 32.89 seconds
Started Aug 17 06:33:32 PM PDT 24
Finished Aug 17 06:34:05 PM PDT 24
Peak memory 256208 kb
Host smart-bbd7d247-c10a-4ec3-bd92-e76ec0a417ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3413541265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3413541265
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2793790021
Short name T759
Test name
Test status
Simulation time 144242005 ps
CPU time 6.52 seconds
Started Aug 17 06:33:50 PM PDT 24
Finished Aug 17 06:33:57 PM PDT 24
Peak memory 240760 kb
Host smart-d2765344-6e1f-46ee-ac22-f8f6e27f9477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793790021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2793790021
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.264161598
Short name T804
Test name
Test status
Simulation time 35213188 ps
CPU time 6 seconds
Started Aug 17 06:33:52 PM PDT 24
Finished Aug 17 06:33:58 PM PDT 24
Peak memory 240700 kb
Host smart-588c01c8-9908-4e67-b374-72f3bf35beac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=264161598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.264161598
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.461690008
Short name T833
Test name
Test status
Simulation time 11715850 ps
CPU time 1.42 seconds
Started Aug 17 06:33:49 PM PDT 24
Finished Aug 17 06:33:51 PM PDT 24
Peak memory 236892 kb
Host smart-ed58b61b-3e68-48a5-b0ba-9a5342564e20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=461690008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.461690008
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2103807699
Short name T735
Test name
Test status
Simulation time 89572730 ps
CPU time 11.8 seconds
Started Aug 17 06:33:53 PM PDT 24
Finished Aug 17 06:34:05 PM PDT 24
Peak memory 245044 kb
Host smart-0047eaa2-101d-4f4e-93db-59d1dbd4b706
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2103807699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2103807699
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1398985076
Short name T764
Test name
Test status
Simulation time 118979690 ps
CPU time 4.54 seconds
Started Aug 17 06:33:44 PM PDT 24
Finished Aug 17 06:33:48 PM PDT 24
Peak memory 248680 kb
Host smart-71ced7df-6a3c-420a-ab3f-0e423ffee849
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1398985076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1398985076
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4161342109
Short name T741
Test name
Test status
Simulation time 44671024 ps
CPU time 5.55 seconds
Started Aug 17 06:33:49 PM PDT 24
Finished Aug 17 06:33:55 PM PDT 24
Peak memory 240708 kb
Host smart-f3629627-8a72-43e8-893c-c3fd3fe732f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161342109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.4161342109
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2943476546
Short name T751
Test name
Test status
Simulation time 19601312 ps
CPU time 3.69 seconds
Started Aug 17 06:33:44 PM PDT 24
Finished Aug 17 06:33:48 PM PDT 24
Peak memory 240676 kb
Host smart-5b558d27-5cfc-4f01-9e2f-338c81c7afb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2943476546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2943476546
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4212161755
Short name T834
Test name
Test status
Simulation time 10137160 ps
CPU time 1.66 seconds
Started Aug 17 06:33:50 PM PDT 24
Finished Aug 17 06:33:52 PM PDT 24
Peak memory 236716 kb
Host smart-01d5df8a-42f2-4ff4-bfb6-d0af98499782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4212161755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.4212161755
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3601881571
Short name T810
Test name
Test status
Simulation time 2795222116 ps
CPU time 49.5 seconds
Started Aug 17 06:33:54 PM PDT 24
Finished Aug 17 06:34:44 PM PDT 24
Peak memory 248940 kb
Host smart-3ece5318-a075-44b4-8f4b-6189d0f11b8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3601881571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3601881571
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3058395284
Short name T777
Test name
Test status
Simulation time 218837516 ps
CPU time 14.59 seconds
Started Aug 17 06:33:55 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 254124 kb
Host smart-4aab27ff-7dfc-4bf4-9c6f-17727d98b1b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3058395284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3058395284
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2109086773
Short name T809
Test name
Test status
Simulation time 170181715 ps
CPU time 7.57 seconds
Started Aug 17 06:33:52 PM PDT 24
Finished Aug 17 06:34:00 PM PDT 24
Peak memory 241160 kb
Host smart-df4b155f-1642-46e7-8c98-b495d1b7187e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109086773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2109086773
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2049818890
Short name T775
Test name
Test status
Simulation time 348694136 ps
CPU time 5.81 seconds
Started Aug 17 06:33:45 PM PDT 24
Finished Aug 17 06:33:51 PM PDT 24
Peak memory 237620 kb
Host smart-cdefa49f-39c6-4e01-8046-0548cf2b394a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2049818890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2049818890
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2025606433
Short name T326
Test name
Test status
Simulation time 25703423 ps
CPU time 1.4 seconds
Started Aug 17 06:33:54 PM PDT 24
Finished Aug 17 06:33:56 PM PDT 24
Peak memory 237756 kb
Host smart-36b6e08a-6eda-491e-8f74-792223667bde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2025606433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2025606433
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3625775939
Short name T770
Test name
Test status
Simulation time 513437718 ps
CPU time 19.02 seconds
Started Aug 17 06:33:40 PM PDT 24
Finished Aug 17 06:33:59 PM PDT 24
Peak memory 245976 kb
Host smart-13adc91c-4c3a-428d-99fd-e381dc45108c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3625775939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3625775939
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1416027876
Short name T137
Test name
Test status
Simulation time 2202469259 ps
CPU time 175.86 seconds
Started Aug 17 06:33:53 PM PDT 24
Finished Aug 17 06:36:49 PM PDT 24
Peak memory 265616 kb
Host smart-60e398d5-6b36-4337-ad92-49496fbcf4f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1416027876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1416027876
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3236535384
Short name T800
Test name
Test status
Simulation time 839859477 ps
CPU time 11.24 seconds
Started Aug 17 06:33:56 PM PDT 24
Finished Aug 17 06:34:07 PM PDT 24
Peak memory 250200 kb
Host smart-e77f1256-69c4-485d-bbdd-337434cec8c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3236535384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3236535384
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.520508930
Short name T743
Test name
Test status
Simulation time 56685632 ps
CPU time 5.03 seconds
Started Aug 17 06:33:39 PM PDT 24
Finished Aug 17 06:33:44 PM PDT 24
Peak memory 239768 kb
Host smart-b3f918cb-cc1e-4623-838c-407033df11f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520508930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.520508930
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3478929525
Short name T830
Test name
Test status
Simulation time 157469792 ps
CPU time 5.13 seconds
Started Aug 17 06:33:49 PM PDT 24
Finished Aug 17 06:33:55 PM PDT 24
Peak memory 236840 kb
Host smart-4fb879f3-1e79-452c-9b5f-8430bd280018
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3478929525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3478929525
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.455951522
Short name T814
Test name
Test status
Simulation time 10855914 ps
CPU time 1.25 seconds
Started Aug 17 06:33:51 PM PDT 24
Finished Aug 17 06:33:52 PM PDT 24
Peak memory 237716 kb
Host smart-d1248e74-41b5-49ea-81ed-b2d29300ec34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=455951522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.455951522
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.802071751
Short name T714
Test name
Test status
Simulation time 510564953 ps
CPU time 35.74 seconds
Started Aug 17 06:33:41 PM PDT 24
Finished Aug 17 06:34:17 PM PDT 24
Peak memory 245904 kb
Host smart-5a22520b-789f-4efe-8727-b74b626f4f54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=802071751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.802071751
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.743414001
Short name T122
Test name
Test status
Simulation time 855022116 ps
CPU time 107.95 seconds
Started Aug 17 06:33:43 PM PDT 24
Finished Aug 17 06:35:31 PM PDT 24
Peak memory 265584 kb
Host smart-5ec3ab0f-606d-41b8-89b3-01a556e51772
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=743414001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.743414001
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.4287770434
Short name T788
Test name
Test status
Simulation time 126467639 ps
CPU time 6.23 seconds
Started Aug 17 06:33:50 PM PDT 24
Finished Aug 17 06:33:57 PM PDT 24
Peak memory 249052 kb
Host smart-3e2be282-ab4a-41f2-ae1d-061f894bee9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4287770434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.4287770434
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1534057377
Short name T761
Test name
Test status
Simulation time 110645572 ps
CPU time 3.91 seconds
Started Aug 17 06:33:54 PM PDT 24
Finished Aug 17 06:33:58 PM PDT 24
Peak memory 237644 kb
Host smart-7faa36b8-dee5-42a5-8e54-600b0e6b2ef0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1534057377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1534057377
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2614689543
Short name T745
Test name
Test status
Simulation time 185419604 ps
CPU time 8.35 seconds
Started Aug 17 06:33:48 PM PDT 24
Finished Aug 17 06:33:56 PM PDT 24
Peak memory 239624 kb
Host smart-762489b5-98a4-4112-b019-0037aa8640b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614689543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2614689543
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.365452333
Short name T823
Test name
Test status
Simulation time 97536523 ps
CPU time 8.26 seconds
Started Aug 17 06:33:51 PM PDT 24
Finished Aug 17 06:33:59 PM PDT 24
Peak memory 240644 kb
Host smart-1aedeaa3-1b0a-4ef8-bba0-53ce53120953
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=365452333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.365452333
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2543891610
Short name T829
Test name
Test status
Simulation time 6785388 ps
CPU time 1.55 seconds
Started Aug 17 06:33:49 PM PDT 24
Finished Aug 17 06:33:51 PM PDT 24
Peak memory 237688 kb
Host smart-56d63978-4f8e-4fca-acad-33cf1a4b6474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2543891610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2543891610
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4100627021
Short name T781
Test name
Test status
Simulation time 712573560 ps
CPU time 49.36 seconds
Started Aug 17 06:34:00 PM PDT 24
Finished Aug 17 06:34:50 PM PDT 24
Peak memory 248904 kb
Host smart-2a095028-60a9-472f-83c2-597f3cbe3bbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4100627021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.4100627021
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3326227612
Short name T145
Test name
Test status
Simulation time 24888468682 ps
CPU time 558.12 seconds
Started Aug 17 06:33:57 PM PDT 24
Finished Aug 17 06:43:15 PM PDT 24
Peak memory 272920 kb
Host smart-c8ccddc6-407a-4685-8fe7-9c32385fa1d3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326227612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3326227612
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1203601004
Short name T789
Test name
Test status
Simulation time 417707469 ps
CPU time 12.88 seconds
Started Aug 17 06:33:46 PM PDT 24
Finished Aug 17 06:33:59 PM PDT 24
Peak memory 248968 kb
Host smart-778a0e7c-8984-4430-8166-aac7b8d003ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1203601004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1203601004
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3955311082
Short name T334
Test name
Test status
Simulation time 1137833468 ps
CPU time 80.95 seconds
Started Aug 17 06:33:26 PM PDT 24
Finished Aug 17 06:34:47 PM PDT 24
Peak memory 240696 kb
Host smart-b502c9d4-c2e1-40a9-8c55-4c1d9b09be70
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3955311082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3955311082
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.714352274
Short name T807
Test name
Test status
Simulation time 14621368523 ps
CPU time 375.6 seconds
Started Aug 17 06:33:27 PM PDT 24
Finished Aug 17 06:39:42 PM PDT 24
Peak memory 240760 kb
Host smart-163e1200-b23f-461c-b06f-7cf3bbcb3e6e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=714352274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.714352274
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3826063778
Short name T811
Test name
Test status
Simulation time 532771024 ps
CPU time 8.36 seconds
Started Aug 17 06:33:20 PM PDT 24
Finished Aug 17 06:33:29 PM PDT 24
Peak memory 248812 kb
Host smart-52b16994-4194-4173-bcea-4c37130a2526
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3826063778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3826063778
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3007454219
Short name T335
Test name
Test status
Simulation time 104750032 ps
CPU time 7.94 seconds
Started Aug 17 06:33:21 PM PDT 24
Finished Aug 17 06:33:29 PM PDT 24
Peak memory 240796 kb
Host smart-5669b74b-d4b0-4bd1-bc95-733108759566
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007454219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3007454219
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.898331880
Short name T805
Test name
Test status
Simulation time 437892430 ps
CPU time 7.51 seconds
Started Aug 17 06:33:25 PM PDT 24
Finished Aug 17 06:33:32 PM PDT 24
Peak memory 236720 kb
Host smart-e9283a1d-d303-4cba-b755-0f5a5305dea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=898331880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.898331880
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1394703988
Short name T801
Test name
Test status
Simulation time 7392492 ps
CPU time 1.37 seconds
Started Aug 17 06:33:18 PM PDT 24
Finished Aug 17 06:33:19 PM PDT 24
Peak memory 237764 kb
Host smart-a4b2e719-60b1-4541-8ab1-fe5cf35ed269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1394703988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1394703988
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.938325090
Short name T715
Test name
Test status
Simulation time 1713521938 ps
CPU time 25.35 seconds
Started Aug 17 06:33:21 PM PDT 24
Finished Aug 17 06:33:46 PM PDT 24
Peak memory 245972 kb
Host smart-ba1092ae-b214-46d6-94b0-bb507a957904
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=938325090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.938325090
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2467532647
Short name T718
Test name
Test status
Simulation time 84379992 ps
CPU time 5.37 seconds
Started Aug 17 06:33:20 PM PDT 24
Finished Aug 17 06:33:26 PM PDT 24
Peak memory 248932 kb
Host smart-748c93b2-61f6-4936-b7d7-ff6a218766e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2467532647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2467532647
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3226537835
Short name T802
Test name
Test status
Simulation time 12777975 ps
CPU time 1.74 seconds
Started Aug 17 06:33:46 PM PDT 24
Finished Aug 17 06:33:48 PM PDT 24
Peak memory 237712 kb
Host smart-86696e58-f60b-4476-905e-100770e10917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3226537835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3226537835
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1297464774
Short name T819
Test name
Test status
Simulation time 12361337 ps
CPU time 1.36 seconds
Started Aug 17 06:33:50 PM PDT 24
Finished Aug 17 06:33:52 PM PDT 24
Peak memory 236732 kb
Host smart-da666245-5a11-4617-8f81-86c1ad56ea72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1297464774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1297464774
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2941101158
Short name T327
Test name
Test status
Simulation time 16355097 ps
CPU time 1.45 seconds
Started Aug 17 06:33:53 PM PDT 24
Finished Aug 17 06:33:54 PM PDT 24
Peak memory 235788 kb
Host smart-c9368f5e-0e1c-47c5-8131-7f4b12c9c51e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2941101158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2941101158
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1783714709
Short name T780
Test name
Test status
Simulation time 11971284 ps
CPU time 1.49 seconds
Started Aug 17 06:33:51 PM PDT 24
Finished Aug 17 06:33:53 PM PDT 24
Peak memory 237716 kb
Host smart-774f68c3-4dd0-4ec1-ac0b-0095d3ea838f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1783714709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1783714709
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.4008573520
Short name T742
Test name
Test status
Simulation time 6813300 ps
CPU time 1.41 seconds
Started Aug 17 06:33:53 PM PDT 24
Finished Aug 17 06:33:54 PM PDT 24
Peak memory 235784 kb
Host smart-bef0b736-240b-4051-acc9-1a29761d02d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4008573520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.4008573520
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.74285077
Short name T323
Test name
Test status
Simulation time 22374807 ps
CPU time 1.3 seconds
Started Aug 17 06:33:50 PM PDT 24
Finished Aug 17 06:33:51 PM PDT 24
Peak memory 236824 kb
Host smart-d065e73c-0bf7-481d-8b23-846278bf7a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=74285077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.74285077
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3346590302
Short name T740
Test name
Test status
Simulation time 7947451 ps
CPU time 1.52 seconds
Started Aug 17 06:33:43 PM PDT 24
Finished Aug 17 06:33:45 PM PDT 24
Peak memory 237784 kb
Host smart-2315fab4-e273-4eae-8946-5dd7654f45b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3346590302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3346590302
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2955418831
Short name T822
Test name
Test status
Simulation time 10019258 ps
CPU time 1.34 seconds
Started Aug 17 06:33:52 PM PDT 24
Finished Aug 17 06:33:54 PM PDT 24
Peak memory 237744 kb
Host smart-bbe4cb8f-d98a-438f-a8c6-26b341a247ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2955418831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2955418831
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3735829133
Short name T782
Test name
Test status
Simulation time 6500897 ps
CPU time 1.47 seconds
Started Aug 17 06:33:38 PM PDT 24
Finished Aug 17 06:33:39 PM PDT 24
Peak memory 235824 kb
Host smart-26dbc78e-ec99-4a15-a69e-8539318345bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3735829133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3735829133
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.52504440
Short name T719
Test name
Test status
Simulation time 13838431 ps
CPU time 1.37 seconds
Started Aug 17 06:33:48 PM PDT 24
Finished Aug 17 06:33:50 PM PDT 24
Peak memory 237776 kb
Host smart-76ba838f-1702-4e1f-920e-665cee2d4636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=52504440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.52504440
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3700357043
Short name T727
Test name
Test status
Simulation time 13331421733 ps
CPU time 239.06 seconds
Started Aug 17 06:33:17 PM PDT 24
Finished Aug 17 06:37:16 PM PDT 24
Peak memory 240772 kb
Host smart-de10c60b-de81-4667-b614-a7e423886930
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3700357043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3700357043
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3912292345
Short name T774
Test name
Test status
Simulation time 714695306 ps
CPU time 5.96 seconds
Started Aug 17 06:33:24 PM PDT 24
Finished Aug 17 06:33:31 PM PDT 24
Peak memory 248740 kb
Host smart-d6731eac-7708-45ad-9b0d-4992ac4fddbb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3912292345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3912292345
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.379817120
Short name T832
Test name
Test status
Simulation time 1049693461 ps
CPU time 6.83 seconds
Started Aug 17 06:33:29 PM PDT 24
Finished Aug 17 06:33:36 PM PDT 24
Peak memory 240368 kb
Host smart-6c83bdda-0180-4e2b-9c7b-2ea9f904f9cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379817120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.379817120
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.378318285
Short name T731
Test name
Test status
Simulation time 247999164 ps
CPU time 8.82 seconds
Started Aug 17 06:33:23 PM PDT 24
Finished Aug 17 06:33:36 PM PDT 24
Peak memory 237632 kb
Host smart-fec46e68-4f13-4c73-a037-763ede5ff67e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=378318285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.378318285
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1056754374
Short name T159
Test name
Test status
Simulation time 15104628 ps
CPU time 1.32 seconds
Started Aug 17 06:33:35 PM PDT 24
Finished Aug 17 06:33:36 PM PDT 24
Peak memory 235772 kb
Host smart-2fbcb7a9-8f56-4718-ac3b-9c1edf7d5d94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1056754374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1056754374
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1450766023
Short name T748
Test name
Test status
Simulation time 252551361 ps
CPU time 18.86 seconds
Started Aug 17 06:33:22 PM PDT 24
Finished Aug 17 06:33:41 PM PDT 24
Peak memory 240712 kb
Host smart-4ffc3587-67d6-47b0-b978-26e38df6f85d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1450766023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1450766023
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2394974810
Short name T146
Test name
Test status
Simulation time 9743068021 ps
CPU time 151.03 seconds
Started Aug 17 06:33:19 PM PDT 24
Finished Aug 17 06:35:55 PM PDT 24
Peak memory 267496 kb
Host smart-a608559a-4fc7-4140-8dba-bf87d109d96b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2394974810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2394974810
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.536731643
Short name T120
Test name
Test status
Simulation time 11534105557 ps
CPU time 326.3 seconds
Started Aug 17 06:33:32 PM PDT 24
Finished Aug 17 06:38:59 PM PDT 24
Peak memory 270284 kb
Host smart-4537a34c-a61c-4322-817f-6f1d266b47ac
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536731643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.536731643
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4015566876
Short name T739
Test name
Test status
Simulation time 207060271 ps
CPU time 6.49 seconds
Started Aug 17 06:33:38 PM PDT 24
Finished Aug 17 06:33:44 PM PDT 24
Peak memory 248884 kb
Host smart-10c5588c-3d62-40b9-ace6-0a5d56fe6498
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4015566876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.4015566876
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.4144376262
Short name T772
Test name
Test status
Simulation time 8461972 ps
CPU time 1.63 seconds
Started Aug 17 06:33:57 PM PDT 24
Finished Aug 17 06:33:59 PM PDT 24
Peak memory 237732 kb
Host smart-3845fdc0-12d5-453a-bf81-ebff4dea9860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4144376262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.4144376262
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.34693704
Short name T815
Test name
Test status
Simulation time 32715636 ps
CPU time 1.38 seconds
Started Aug 17 06:33:56 PM PDT 24
Finished Aug 17 06:33:57 PM PDT 24
Peak memory 236776 kb
Host smart-20780ba3-4351-450f-802d-f063653221a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=34693704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.34693704
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3026623228
Short name T795
Test name
Test status
Simulation time 9103440 ps
CPU time 1.46 seconds
Started Aug 17 06:33:50 PM PDT 24
Finished Aug 17 06:33:52 PM PDT 24
Peak memory 237768 kb
Host smart-d27fd920-5dac-4ff6-8a97-1dfe2463daf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3026623228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3026623228
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2939205976
Short name T783
Test name
Test status
Simulation time 7340474 ps
CPU time 1.49 seconds
Started Aug 17 06:33:55 PM PDT 24
Finished Aug 17 06:33:57 PM PDT 24
Peak memory 236880 kb
Host smart-98aa71fe-f2df-43f4-8e44-b3e555d10e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2939205976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2939205976
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3374409716
Short name T827
Test name
Test status
Simulation time 22593207 ps
CPU time 1.4 seconds
Started Aug 17 06:33:48 PM PDT 24
Finished Aug 17 06:33:50 PM PDT 24
Peak memory 235768 kb
Host smart-29454543-6e99-4323-b4e4-7e3f549b3397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3374409716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3374409716
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1784513232
Short name T771
Test name
Test status
Simulation time 24733255 ps
CPU time 1.51 seconds
Started Aug 17 06:33:47 PM PDT 24
Finished Aug 17 06:33:49 PM PDT 24
Peak memory 235828 kb
Host smart-4f72de6c-4ccf-4c18-b0cb-688f67d9ca1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1784513232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1784513232
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.4227685322
Short name T723
Test name
Test status
Simulation time 20288559 ps
CPU time 1.4 seconds
Started Aug 17 06:33:35 PM PDT 24
Finished Aug 17 06:33:37 PM PDT 24
Peak memory 237612 kb
Host smart-3284f3d2-fc28-4a5e-97a7-755ecb9be61e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4227685322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.4227685322
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3363197057
Short name T818
Test name
Test status
Simulation time 10443780 ps
CPU time 1.44 seconds
Started Aug 17 06:33:44 PM PDT 24
Finished Aug 17 06:33:45 PM PDT 24
Peak memory 237776 kb
Host smart-a3bed3f3-7754-4adb-8809-b76507f8a61c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3363197057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3363197057
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1926612298
Short name T758
Test name
Test status
Simulation time 11486472 ps
CPU time 1.37 seconds
Started Aug 17 06:33:49 PM PDT 24
Finished Aug 17 06:33:51 PM PDT 24
Peak memory 237768 kb
Host smart-1e918e24-a1c5-4031-9b48-272dd78c42c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1926612298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1926612298
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2184451439
Short name T821
Test name
Test status
Simulation time 4061180209 ps
CPU time 246.24 seconds
Started Aug 17 06:33:34 PM PDT 24
Finished Aug 17 06:37:40 PM PDT 24
Peak memory 240716 kb
Host smart-6930ca34-fd98-4edb-ac22-b43168858304
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2184451439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2184451439
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4083933456
Short name T332
Test name
Test status
Simulation time 3406710283 ps
CPU time 105.23 seconds
Started Aug 17 06:33:25 PM PDT 24
Finished Aug 17 06:35:10 PM PDT 24
Peak memory 237676 kb
Host smart-30968833-7a43-4470-a6a7-098e99e6fb4a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4083933456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.4083933456
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1494219938
Short name T749
Test name
Test status
Simulation time 102512894 ps
CPU time 5.12 seconds
Started Aug 17 06:33:24 PM PDT 24
Finished Aug 17 06:33:29 PM PDT 24
Peak memory 248720 kb
Host smart-38d0a838-34db-4fb7-850a-52278c7490d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1494219938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1494219938
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2778653073
Short name T792
Test name
Test status
Simulation time 139791997 ps
CPU time 6.17 seconds
Started Aug 17 06:33:25 PM PDT 24
Finished Aug 17 06:33:31 PM PDT 24
Peak memory 240760 kb
Host smart-81181619-4d5f-407d-b453-15a41e4b26e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778653073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2778653073
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.642423490
Short name T180
Test name
Test status
Simulation time 108907339 ps
CPU time 3.21 seconds
Started Aug 17 06:33:22 PM PDT 24
Finished Aug 17 06:33:25 PM PDT 24
Peak memory 237744 kb
Host smart-66c6f506-53ab-446b-b09c-9e043a788ed4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=642423490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.642423490
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2017442383
Short name T722
Test name
Test status
Simulation time 13002449 ps
CPU time 1.41 seconds
Started Aug 17 06:33:21 PM PDT 24
Finished Aug 17 06:33:23 PM PDT 24
Peak memory 236836 kb
Host smart-f6e39d0a-e0cf-4ce8-b326-aa2ba31e35aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2017442383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2017442383
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2097151769
Short name T755
Test name
Test status
Simulation time 657192853 ps
CPU time 21.37 seconds
Started Aug 17 06:33:32 PM PDT 24
Finished Aug 17 06:33:53 PM PDT 24
Peak memory 246172 kb
Host smart-8f90803b-e0bd-4db4-9486-fd2cd30f510a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2097151769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2097151769
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3663815763
Short name T124
Test name
Test status
Simulation time 10250751344 ps
CPU time 195.68 seconds
Started Aug 17 06:33:44 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 273168 kb
Host smart-56434563-b8d5-4e94-8d01-693cd801e3e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3663815763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3663815763
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.721325324
Short name T816
Test name
Test status
Simulation time 1644634356 ps
CPU time 28.75 seconds
Started Aug 17 06:33:21 PM PDT 24
Finished Aug 17 06:33:50 PM PDT 24
Peak memory 248772 kb
Host smart-e44eece3-bd40-4526-b611-bebf2dc066a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=721325324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.721325324
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3096213919
Short name T754
Test name
Test status
Simulation time 19145385 ps
CPU time 1.37 seconds
Started Aug 17 06:33:52 PM PDT 24
Finished Aug 17 06:33:54 PM PDT 24
Peak memory 237788 kb
Host smart-d0c2ca6a-4e43-4602-acd6-bebf3df62773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3096213919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3096213919
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1641688326
Short name T787
Test name
Test status
Simulation time 9062870 ps
CPU time 1.4 seconds
Started Aug 17 06:33:59 PM PDT 24
Finished Aug 17 06:34:01 PM PDT 24
Peak memory 237784 kb
Host smart-2fb533c6-25c8-4a2e-ad88-139b648d8ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1641688326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1641688326
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.4011829480
Short name T738
Test name
Test status
Simulation time 12184846 ps
CPU time 1.35 seconds
Started Aug 17 06:33:58 PM PDT 24
Finished Aug 17 06:33:59 PM PDT 24
Peak memory 236916 kb
Host smart-7cc898fe-ce6b-4399-8a5c-973d24646d57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4011829480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.4011829480
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.4030596423
Short name T746
Test name
Test status
Simulation time 33922196 ps
CPU time 1.59 seconds
Started Aug 17 06:33:57 PM PDT 24
Finished Aug 17 06:33:58 PM PDT 24
Peak memory 236840 kb
Host smart-43d8cf5a-2db8-4d97-83c4-fda1206d9e26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4030596423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.4030596423
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2152711839
Short name T762
Test name
Test status
Simulation time 12579958 ps
CPU time 1.52 seconds
Started Aug 17 06:34:00 PM PDT 24
Finished Aug 17 06:34:02 PM PDT 24
Peak memory 236812 kb
Host smart-18689a2f-0cc1-4fce-bed7-941967189e81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2152711839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2152711839
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.4048194437
Short name T791
Test name
Test status
Simulation time 40955518 ps
CPU time 1.45 seconds
Started Aug 17 06:33:53 PM PDT 24
Finished Aug 17 06:33:55 PM PDT 24
Peak memory 237744 kb
Host smart-5a254071-6bd0-40c4-9245-81c89a8aae8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4048194437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.4048194437
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3044840412
Short name T744
Test name
Test status
Simulation time 7286812 ps
CPU time 1.55 seconds
Started Aug 17 06:33:58 PM PDT 24
Finished Aug 17 06:34:00 PM PDT 24
Peak memory 237764 kb
Host smart-a249ab84-845e-469d-a534-00f37aef4a6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3044840412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3044840412
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2696762957
Short name T747
Test name
Test status
Simulation time 7364968 ps
CPU time 1.47 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:08 PM PDT 24
Peak memory 235784 kb
Host smart-d48e39e3-297c-42d9-b287-32cd881dd61d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2696762957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2696762957
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2565434177
Short name T737
Test name
Test status
Simulation time 19313940 ps
CPU time 1.28 seconds
Started Aug 17 06:33:59 PM PDT 24
Finished Aug 17 06:34:01 PM PDT 24
Peak memory 237716 kb
Host smart-629afefe-303d-460f-a565-210fa0afea87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2565434177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2565434177
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2195306481
Short name T736
Test name
Test status
Simulation time 18521699 ps
CPU time 1.3 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 237612 kb
Host smart-27ba4a01-9e28-47c9-8a03-d2540ff503f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2195306481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2195306481
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.4203272373
Short name T732
Test name
Test status
Simulation time 165812467 ps
CPU time 10.95 seconds
Started Aug 17 06:33:35 PM PDT 24
Finished Aug 17 06:33:46 PM PDT 24
Peak memory 252036 kb
Host smart-0c77ce82-3b12-4d00-b547-84e2ba424b1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203272373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.4203272373
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.335951389
Short name T784
Test name
Test status
Simulation time 34974112 ps
CPU time 3.07 seconds
Started Aug 17 06:33:41 PM PDT 24
Finished Aug 17 06:33:44 PM PDT 24
Peak memory 236820 kb
Host smart-ea196037-aaaa-444e-819e-1810fc512d14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=335951389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.335951389
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.170166505
Short name T773
Test name
Test status
Simulation time 19527201 ps
CPU time 1.39 seconds
Started Aug 17 06:33:55 PM PDT 24
Finished Aug 17 06:33:57 PM PDT 24
Peak memory 235388 kb
Host smart-4b83b225-c9e0-44e9-aaf0-74189d3fe5d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=170166505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.170166505
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3857192082
Short name T779
Test name
Test status
Simulation time 168089672 ps
CPU time 22.34 seconds
Started Aug 17 06:33:25 PM PDT 24
Finished Aug 17 06:33:48 PM PDT 24
Peak memory 245872 kb
Host smart-8fe3b10c-fe9f-498f-a5d7-b93171e7f8e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3857192082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3857192082
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.68614522
Short name T148
Test name
Test status
Simulation time 38592172830 ps
CPU time 617.14 seconds
Started Aug 17 06:33:22 PM PDT 24
Finished Aug 17 06:43:39 PM PDT 24
Peak memory 272880 kb
Host smart-f236a260-dbc1-48f7-ab15-e60e7049205f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68614522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.68614522
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.4233282264
Short name T756
Test name
Test status
Simulation time 206690221 ps
CPU time 11.13 seconds
Started Aug 17 06:33:22 PM PDT 24
Finished Aug 17 06:33:33 PM PDT 24
Peak memory 253720 kb
Host smart-f72b15dd-b570-494e-be75-9fbaf0819bda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4233282264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.4233282264
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3112168260
Short name T171
Test name
Test status
Simulation time 400034519 ps
CPU time 9.12 seconds
Started Aug 17 06:33:42 PM PDT 24
Finished Aug 17 06:33:51 PM PDT 24
Peak memory 241096 kb
Host smart-fa25419c-2bc8-482b-8518-6650d4507ff5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112168260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3112168260
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3513870651
Short name T177
Test name
Test status
Simulation time 20035186 ps
CPU time 3.4 seconds
Started Aug 17 06:33:23 PM PDT 24
Finished Aug 17 06:33:27 PM PDT 24
Peak memory 237756 kb
Host smart-9539d35a-694d-4257-8046-5c293b0f0c21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3513870651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3513870651
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1915016583
Short name T757
Test name
Test status
Simulation time 12510079 ps
CPU time 1.59 seconds
Started Aug 17 06:33:20 PM PDT 24
Finished Aug 17 06:33:22 PM PDT 24
Peak memory 235740 kb
Host smart-4efb275a-09df-4c23-b796-1e77f4032ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1915016583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1915016583
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.506321432
Short name T729
Test name
Test status
Simulation time 166700380 ps
CPU time 20.92 seconds
Started Aug 17 06:33:42 PM PDT 24
Finished Aug 17 06:34:03 PM PDT 24
Peak memory 245952 kb
Host smart-b11f46df-9e84-4816-8b55-8e36c82042dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=506321432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.506321432
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.630902730
Short name T138
Test name
Test status
Simulation time 9978157013 ps
CPU time 189.55 seconds
Started Aug 17 06:33:20 PM PDT 24
Finished Aug 17 06:36:30 PM PDT 24
Peak memory 256992 kb
Host smart-66ec32a8-3485-4885-8af0-1beef06cc770
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=630902730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.630902730
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3751583782
Short name T798
Test name
Test status
Simulation time 909452373 ps
CPU time 7.64 seconds
Started Aug 17 06:33:22 PM PDT 24
Finished Aug 17 06:33:29 PM PDT 24
Peak memory 249988 kb
Host smart-4e814bed-5635-466e-bc9e-3923c9ba6535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3751583782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3751583782
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3892361499
Short name T725
Test name
Test status
Simulation time 122637970 ps
CPU time 9.81 seconds
Started Aug 17 06:33:29 PM PDT 24
Finished Aug 17 06:33:39 PM PDT 24
Peak memory 254128 kb
Host smart-5f526c07-d912-4088-88d8-9670fef6a55c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892361499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3892361499
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1340389140
Short name T338
Test name
Test status
Simulation time 63950246 ps
CPU time 3.41 seconds
Started Aug 17 06:33:30 PM PDT 24
Finished Aug 17 06:33:34 PM PDT 24
Peak memory 237692 kb
Host smart-419f13df-2391-4504-a6e6-680946b5a23f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1340389140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1340389140
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3260356887
Short name T835
Test name
Test status
Simulation time 11577164 ps
CPU time 1.42 seconds
Started Aug 17 06:33:39 PM PDT 24
Finished Aug 17 06:33:41 PM PDT 24
Peak memory 237712 kb
Host smart-144a9c60-704e-4fcc-bed3-a1a7bb2da370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3260356887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3260356887
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.4243504532
Short name T808
Test name
Test status
Simulation time 2835706811 ps
CPU time 50.6 seconds
Started Aug 17 06:33:38 PM PDT 24
Finished Aug 17 06:34:29 PM PDT 24
Peak memory 248960 kb
Host smart-2b04b140-ab33-43a2-8bb9-9696bc9085c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4243504532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.4243504532
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2949286772
Short name T147
Test name
Test status
Simulation time 7719692311 ps
CPU time 133.03 seconds
Started Aug 17 06:33:22 PM PDT 24
Finished Aug 17 06:35:35 PM PDT 24
Peak memory 265672 kb
Host smart-2ee507b9-dc25-4b35-b563-af78ba478daa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2949286772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2949286772
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3203173828
Short name T129
Test name
Test status
Simulation time 55051540903 ps
CPU time 972.17 seconds
Started Aug 17 06:33:39 PM PDT 24
Finished Aug 17 06:49:51 PM PDT 24
Peak memory 265628 kb
Host smart-370a7921-6a2d-49c1-9973-23800dba8898
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203173828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3203173828
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2138727085
Short name T796
Test name
Test status
Simulation time 200936090 ps
CPU time 7.15 seconds
Started Aug 17 06:33:40 PM PDT 24
Finished Aug 17 06:33:47 PM PDT 24
Peak memory 248904 kb
Host smart-fe61ce98-a72f-4d96-90d2-a7eeb2f603ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2138727085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2138727085
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3530957091
Short name T330
Test name
Test status
Simulation time 663108330 ps
CPU time 14.58 seconds
Started Aug 17 06:33:57 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 243844 kb
Host smart-c57c3405-4aba-4134-98e2-b6dfe4e0b0ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530957091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3530957091
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.103281378
Short name T793
Test name
Test status
Simulation time 515536278 ps
CPU time 8.95 seconds
Started Aug 17 06:33:45 PM PDT 24
Finished Aug 17 06:33:54 PM PDT 24
Peak memory 240920 kb
Host smart-81882c14-7997-4e8d-9fd0-2e70a3c6b34a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=103281378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.103281378
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2303836317
Short name T157
Test name
Test status
Simulation time 17749278 ps
CPU time 1.38 seconds
Started Aug 17 06:33:52 PM PDT 24
Finished Aug 17 06:33:53 PM PDT 24
Peak memory 235768 kb
Host smart-c00f7b25-1347-4b38-a8a4-ad286f798021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2303836317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2303836317
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4129240827
Short name T179
Test name
Test status
Simulation time 700315439 ps
CPU time 12.9 seconds
Started Aug 17 06:33:52 PM PDT 24
Finished Aug 17 06:34:04 PM PDT 24
Peak memory 245820 kb
Host smart-95b570f2-4dc3-485b-84a4-348258079b23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4129240827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.4129240827
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3936127654
Short name T140
Test name
Test status
Simulation time 6658196498 ps
CPU time 171.4 seconds
Started Aug 17 06:33:42 PM PDT 24
Finished Aug 17 06:36:34 PM PDT 24
Peak memory 265672 kb
Host smart-83b43bf9-e8ec-49b0-83e4-5b1c52c1bd49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3936127654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3936127654
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.49205994
Short name T724
Test name
Test status
Simulation time 126465809 ps
CPU time 7.61 seconds
Started Aug 17 06:33:50 PM PDT 24
Finished Aug 17 06:33:58 PM PDT 24
Peak memory 256972 kb
Host smart-d9bcd4e8-e540-441f-b853-43290044b993
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=49205994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.49205994
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3540214708
Short name T733
Test name
Test status
Simulation time 333584756 ps
CPU time 6.86 seconds
Started Aug 17 06:33:48 PM PDT 24
Finished Aug 17 06:33:55 PM PDT 24
Peak memory 240372 kb
Host smart-8aa635b1-a7e8-4d44-bccc-490cce8b3735
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540214708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3540214708
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.237330580
Short name T768
Test name
Test status
Simulation time 122555915 ps
CPU time 8.75 seconds
Started Aug 17 06:33:34 PM PDT 24
Finished Aug 17 06:33:43 PM PDT 24
Peak memory 237736 kb
Host smart-e283ce29-1e2e-4ea0-898f-a3af017dfeb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=237330580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.237330580
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1335477767
Short name T728
Test name
Test status
Simulation time 8064439 ps
CPU time 1.51 seconds
Started Aug 17 06:33:45 PM PDT 24
Finished Aug 17 06:33:46 PM PDT 24
Peak memory 236864 kb
Host smart-132e72c7-554c-4d8c-8a08-e8db4368107c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1335477767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1335477767
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1695890135
Short name T824
Test name
Test status
Simulation time 174241599 ps
CPU time 13.74 seconds
Started Aug 17 06:33:48 PM PDT 24
Finished Aug 17 06:34:02 PM PDT 24
Peak memory 248824 kb
Host smart-547d6d60-7f35-436f-aa70-d52be24490b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1695890135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1695890135
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.152444026
Short name T150
Test name
Test status
Simulation time 1004636110 ps
CPU time 96.59 seconds
Started Aug 17 06:33:26 PM PDT 24
Finished Aug 17 06:35:03 PM PDT 24
Peak memory 265552 kb
Host smart-7c2c48bd-333e-4a1b-a511-43f23836f7fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=152444026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.152444026
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4172020282
Short name T143
Test name
Test status
Simulation time 4589625556 ps
CPU time 335.94 seconds
Started Aug 17 06:33:51 PM PDT 24
Finished Aug 17 06:39:27 PM PDT 24
Peak memory 265624 kb
Host smart-e5b3fc42-4b9d-4c3c-8dae-8ebf45b6c0b5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172020282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.4172020282
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3433839670
Short name T828
Test name
Test status
Simulation time 169940678 ps
CPU time 10.61 seconds
Started Aug 17 06:33:22 PM PDT 24
Finished Aug 17 06:33:33 PM PDT 24
Peak memory 248996 kb
Host smart-7ab73ffd-2bf8-42c0-a7df-a3cd896b3915
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3433839670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3433839670
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1999834858
Short name T422
Test name
Test status
Simulation time 167775089066 ps
CPU time 1121.65 seconds
Started Aug 17 05:55:59 PM PDT 24
Finished Aug 17 06:14:41 PM PDT 24
Peak memory 288600 kb
Host smart-1fc5633a-2d86-4500-8b25-bfe6f1da1506
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999834858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1999834858
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.4284358904
Short name T454
Test name
Test status
Simulation time 1083600212 ps
CPU time 15.05 seconds
Started Aug 17 05:56:03 PM PDT 24
Finished Aug 17 05:56:18 PM PDT 24
Peak memory 248732 kb
Host smart-e953e448-cc5b-4deb-9cd3-c4dc51a80a39
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4284358904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.4284358904
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1205072278
Short name T578
Test name
Test status
Simulation time 57045352970 ps
CPU time 153.74 seconds
Started Aug 17 05:55:55 PM PDT 24
Finished Aug 17 05:58:29 PM PDT 24
Peak memory 256340 kb
Host smart-543d1004-394b-4db9-a39b-c7abdd1e694c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12050
72278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1205072278
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3509672136
Short name T82
Test name
Test status
Simulation time 337737484 ps
CPU time 8.82 seconds
Started Aug 17 05:55:54 PM PDT 24
Finished Aug 17 05:56:03 PM PDT 24
Peak memory 254568 kb
Host smart-49238433-4fe3-494b-85bf-ed3e75ac2e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35096
72136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3509672136
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.497939198
Short name T101
Test name
Test status
Simulation time 84707486596 ps
CPU time 1084.7 seconds
Started Aug 17 05:56:05 PM PDT 24
Finished Aug 17 06:14:10 PM PDT 24
Peak memory 265268 kb
Host smart-e4e5e459-593c-434c-8507-0d7c5916f19e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497939198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.497939198
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3290524416
Short name T285
Test name
Test status
Simulation time 6493767874 ps
CPU time 266.86 seconds
Started Aug 17 05:55:59 PM PDT 24
Finished Aug 17 06:00:26 PM PDT 24
Peak memory 248824 kb
Host smart-b05e8414-ec07-40df-92f9-390691f12943
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290524416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3290524416
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.828751701
Short name T339
Test name
Test status
Simulation time 297316211 ps
CPU time 16.2 seconds
Started Aug 17 05:56:00 PM PDT 24
Finished Aug 17 05:56:17 PM PDT 24
Peak memory 248784 kb
Host smart-fd67104d-e475-47f7-963c-6bee5aed0cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82875
1701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.828751701
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1839561528
Short name T557
Test name
Test status
Simulation time 818731052 ps
CPU time 52.34 seconds
Started Aug 17 05:55:55 PM PDT 24
Finished Aug 17 05:56:48 PM PDT 24
Peak memory 256112 kb
Host smart-a4bed240-aade-48d6-ba6f-153d614bbc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18395
61528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1839561528
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.4032030882
Short name T9
Test name
Test status
Simulation time 2436127728 ps
CPU time 26.67 seconds
Started Aug 17 05:56:05 PM PDT 24
Finished Aug 17 05:56:31 PM PDT 24
Peak memory 274160 kb
Host smart-f7c20bbb-e0b3-4ed3-8f2a-e0582e515e7b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4032030882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.4032030882
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.4169431553
Short name T631
Test name
Test status
Simulation time 437942969 ps
CPU time 28.6 seconds
Started Aug 17 05:55:57 PM PDT 24
Finished Aug 17 05:56:25 PM PDT 24
Peak memory 249268 kb
Host smart-5b1ced0a-e609-40b1-a31f-0892688c4bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41694
31553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.4169431553
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3167717450
Short name T413
Test name
Test status
Simulation time 523313783 ps
CPU time 9.15 seconds
Started Aug 17 05:55:58 PM PDT 24
Finished Aug 17 05:56:07 PM PDT 24
Peak memory 255340 kb
Host smart-40addb8f-ed5e-4b16-b5e3-09ec29f09dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31677
17450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3167717450
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3837093648
Short name T553
Test name
Test status
Simulation time 2334397367 ps
CPU time 272.43 seconds
Started Aug 17 05:56:02 PM PDT 24
Finished Aug 17 06:00:34 PM PDT 24
Peak memory 266440 kb
Host smart-72d16f3d-75ed-4223-9aba-18912b74659b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837093648 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3837093648
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3499354186
Short name T612
Test name
Test status
Simulation time 32439350301 ps
CPU time 1764.27 seconds
Started Aug 17 05:56:07 PM PDT 24
Finished Aug 17 06:25:32 PM PDT 24
Peak memory 273204 kb
Host smart-49931e72-7667-4539-807b-10d8e3b89606
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499354186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3499354186
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3710296888
Short name T214
Test name
Test status
Simulation time 500070400 ps
CPU time 24.18 seconds
Started Aug 17 05:56:05 PM PDT 24
Finished Aug 17 05:56:29 PM PDT 24
Peak memory 248808 kb
Host smart-20fe1cfe-d25d-4518-a6f5-cf8d381c9e3e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3710296888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3710296888
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3832921995
Short name T638
Test name
Test status
Simulation time 90958224 ps
CPU time 7.46 seconds
Started Aug 17 05:56:05 PM PDT 24
Finished Aug 17 05:56:12 PM PDT 24
Peak memory 254560 kb
Host smart-0db63e04-d877-44ec-b5c8-7b262ab7404a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38329
21995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3832921995
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2249933614
Short name T361
Test name
Test status
Simulation time 1060113370 ps
CPU time 27.58 seconds
Started Aug 17 05:56:03 PM PDT 24
Finished Aug 17 05:56:31 PM PDT 24
Peak memory 248840 kb
Host smart-76a87e56-82cc-490a-8b12-4a60fb2f537f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22499
33614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2249933614
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3488885116
Short name T93
Test name
Test status
Simulation time 37522268248 ps
CPU time 2183.53 seconds
Started Aug 17 05:56:03 PM PDT 24
Finished Aug 17 06:32:27 PM PDT 24
Peak memory 289700 kb
Host smart-860b74fc-0214-4964-b828-64b2c2e4cc2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488885116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3488885116
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1773486760
Short name T664
Test name
Test status
Simulation time 341214715 ps
CPU time 25.26 seconds
Started Aug 17 05:56:08 PM PDT 24
Finished Aug 17 05:56:34 PM PDT 24
Peak memory 256228 kb
Host smart-d69a00bf-e712-4329-bc38-1967fcb0e9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17734
86760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1773486760
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.549775189
Short name T72
Test name
Test status
Simulation time 669461813 ps
CPU time 27.02 seconds
Started Aug 17 05:56:05 PM PDT 24
Finished Aug 17 05:56:32 PM PDT 24
Peak memory 248708 kb
Host smart-1fb8dd46-b709-4863-94a7-bffd5bee1d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54977
5189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.549775189
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.444734461
Short name T388
Test name
Test status
Simulation time 1218074846 ps
CPU time 45.88 seconds
Started Aug 17 05:56:08 PM PDT 24
Finished Aug 17 05:56:54 PM PDT 24
Peak memory 256948 kb
Host smart-5c42a8c2-3e22-45c3-bb33-1a5ddaf7148a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44473
4461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.444734461
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3809410322
Short name T187
Test name
Test status
Simulation time 184432646 ps
CPU time 3.96 seconds
Started Aug 17 05:56:36 PM PDT 24
Finished Aug 17 05:56:40 PM PDT 24
Peak memory 248924 kb
Host smart-3158c38d-7eab-4933-809d-e120d0442745
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3809410322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3809410322
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3266685134
Short name T490
Test name
Test status
Simulation time 38010164611 ps
CPU time 1544.23 seconds
Started Aug 17 05:56:36 PM PDT 24
Finished Aug 17 06:22:21 PM PDT 24
Peak memory 289756 kb
Host smart-c71841e5-d678-4716-a1c2-07bb10de6086
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266685134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3266685134
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2577745635
Short name T390
Test name
Test status
Simulation time 650327355 ps
CPU time 11.46 seconds
Started Aug 17 05:56:38 PM PDT 24
Finished Aug 17 05:56:50 PM PDT 24
Peak memory 248644 kb
Host smart-dbfece4e-b8ef-4c34-9adf-956cd61425c0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2577745635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2577745635
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2174354734
Short name T491
Test name
Test status
Simulation time 481100454 ps
CPU time 38.14 seconds
Started Aug 17 05:56:37 PM PDT 24
Finished Aug 17 05:57:15 PM PDT 24
Peak memory 256548 kb
Host smart-172ace88-fdf5-412b-964e-0f9620dff3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21743
54734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2174354734
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2388387300
Short name T623
Test name
Test status
Simulation time 1164635488 ps
CPU time 33.45 seconds
Started Aug 17 05:56:39 PM PDT 24
Finished Aug 17 05:57:12 PM PDT 24
Peak memory 248624 kb
Host smart-b4c0b5ba-4112-4c7c-a23f-7354e156dcad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23883
87300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2388387300
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.611842386
Short name T318
Test name
Test status
Simulation time 19182574978 ps
CPU time 1593.53 seconds
Started Aug 17 05:56:37 PM PDT 24
Finished Aug 17 06:23:11 PM PDT 24
Peak memory 289300 kb
Host smart-fa435d9a-6309-4103-92f4-1e00c5f2b903
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611842386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.611842386
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2035766545
Short name T306
Test name
Test status
Simulation time 48180251790 ps
CPU time 1935.53 seconds
Started Aug 17 05:56:37 PM PDT 24
Finished Aug 17 06:28:53 PM PDT 24
Peak memory 289440 kb
Host smart-12f2ac88-6cd7-49ca-ae7c-404e93d6aad6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035766545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2035766545
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.332744629
Short name T685
Test name
Test status
Simulation time 7079036438 ps
CPU time 157.11 seconds
Started Aug 17 05:56:35 PM PDT 24
Finished Aug 17 05:59:12 PM PDT 24
Peak memory 248920 kb
Host smart-a6ea0674-4dbf-43f6-ad4c-ea1532574858
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332744629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.332744629
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2048940675
Short name T511
Test name
Test status
Simulation time 474663817 ps
CPU time 34.05 seconds
Started Aug 17 05:56:39 PM PDT 24
Finished Aug 17 05:57:13 PM PDT 24
Peak memory 256200 kb
Host smart-a56765c0-af4c-452a-946a-2c4b645c96df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20489
40675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2048940675
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.742958323
Short name T271
Test name
Test status
Simulation time 205530416 ps
CPU time 15.81 seconds
Started Aug 17 05:56:37 PM PDT 24
Finished Aug 17 05:56:53 PM PDT 24
Peak memory 248292 kb
Host smart-f67d8254-3f6c-4c72-91b2-7cd51c47b1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74295
8323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.742958323
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1541764919
Short name T596
Test name
Test status
Simulation time 906854322 ps
CPU time 9.37 seconds
Started Aug 17 05:56:38 PM PDT 24
Finished Aug 17 05:56:48 PM PDT 24
Peak memory 248360 kb
Host smart-d6ac612e-b67e-4e17-a6e5-95b0d3ae6c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15417
64919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1541764919
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.4254024771
Short name T344
Test name
Test status
Simulation time 2545415960 ps
CPU time 42.74 seconds
Started Aug 17 05:56:40 PM PDT 24
Finished Aug 17 05:57:22 PM PDT 24
Peak memory 248916 kb
Host smart-932c3409-87d7-4b8a-82cf-84bbca18387f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42540
24771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.4254024771
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1083470413
Short name T512
Test name
Test status
Simulation time 26864744658 ps
CPU time 505.98 seconds
Started Aug 17 05:56:38 PM PDT 24
Finished Aug 17 06:05:04 PM PDT 24
Peak memory 257100 kb
Host smart-7f840e7f-2469-4031-b56b-bf65eccbe6fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083470413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1083470413
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2322599273
Short name T543
Test name
Test status
Simulation time 213931490478 ps
CPU time 1640.91 seconds
Started Aug 17 05:56:43 PM PDT 24
Finished Aug 17 06:24:04 PM PDT 24
Peak memory 288844 kb
Host smart-2635baf0-fb94-46d9-92c9-75edc977b7ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322599273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2322599273
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2209895926
Short name T667
Test name
Test status
Simulation time 1064386853 ps
CPU time 15.18 seconds
Started Aug 17 05:56:44 PM PDT 24
Finished Aug 17 05:56:59 PM PDT 24
Peak memory 248800 kb
Host smart-78c9506d-88f0-47fa-8c31-8b191e8e71ce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2209895926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2209895926
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1478747696
Short name T474
Test name
Test status
Simulation time 7335247439 ps
CPU time 116.62 seconds
Started Aug 17 05:56:43 PM PDT 24
Finished Aug 17 05:58:40 PM PDT 24
Peak memory 257004 kb
Host smart-59b648a9-403b-4953-b079-39d9a14bb86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14787
47696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1478747696
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3863542735
Short name T99
Test name
Test status
Simulation time 2868152119 ps
CPU time 47.61 seconds
Started Aug 17 05:56:45 PM PDT 24
Finished Aug 17 05:57:32 PM PDT 24
Peak memory 257020 kb
Host smart-e03a3dc5-f46f-4be7-ae76-a8029ba22671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38635
42735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3863542735
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3641214256
Short name T624
Test name
Test status
Simulation time 218450593716 ps
CPU time 2994.28 seconds
Started Aug 17 05:56:42 PM PDT 24
Finished Aug 17 06:46:36 PM PDT 24
Peak memory 289444 kb
Host smart-3e50f0f3-e9c9-4d3c-8043-35d8b2aace87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641214256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3641214256
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3105428372
Short name T354
Test name
Test status
Simulation time 230853148754 ps
CPU time 3001.21 seconds
Started Aug 17 05:56:44 PM PDT 24
Finished Aug 17 06:46:45 PM PDT 24
Peak memory 287756 kb
Host smart-9f1445d4-7a27-4ac5-9eec-70ce6e1edbb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105428372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3105428372
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.4269775977
Short name T297
Test name
Test status
Simulation time 8557058975 ps
CPU time 365.92 seconds
Started Aug 17 05:56:43 PM PDT 24
Finished Aug 17 06:02:49 PM PDT 24
Peak memory 248816 kb
Host smart-5ba1143b-9e56-40b3-a68b-4cba783416f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269775977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.4269775977
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.325366714
Short name T88
Test name
Test status
Simulation time 3346453708 ps
CPU time 59.09 seconds
Started Aug 17 05:56:42 PM PDT 24
Finished Aug 17 05:57:41 PM PDT 24
Peak memory 256324 kb
Host smart-b84d49c8-e114-43ad-a4ca-60bbe962eb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32536
6714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.325366714
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2354861692
Short name T411
Test name
Test status
Simulation time 1905300271 ps
CPU time 39.25 seconds
Started Aug 17 05:56:41 PM PDT 24
Finished Aug 17 05:57:21 PM PDT 24
Peak memory 248748 kb
Host smart-d4225923-2c7b-449e-b2ef-27f55c8483a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23548
61692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2354861692
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.531538341
Short name T63
Test name
Test status
Simulation time 316143140 ps
CPU time 9.32 seconds
Started Aug 17 05:56:43 PM PDT 24
Finished Aug 17 05:56:52 PM PDT 24
Peak memory 254900 kb
Host smart-e6400f32-4b83-4b41-821e-2062ad8080ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53153
8341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.531538341
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2008607231
Short name T5
Test name
Test status
Simulation time 9180196372 ps
CPU time 877.89 seconds
Started Aug 17 05:56:42 PM PDT 24
Finished Aug 17 06:11:20 PM PDT 24
Peak memory 272492 kb
Host smart-85f3a2f1-4e8c-49a8-8802-bd069dc56b77
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008607231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2008607231
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2416782824
Short name T534
Test name
Test status
Simulation time 35050818549 ps
CPU time 2213.59 seconds
Started Aug 17 05:56:42 PM PDT 24
Finished Aug 17 06:33:36 PM PDT 24
Peak memory 282420 kb
Host smart-8f6e2fee-f283-4bda-85d8-28f0ebf656f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416782824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2416782824
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3919943096
Short name T46
Test name
Test status
Simulation time 1567744134 ps
CPU time 33.46 seconds
Started Aug 17 05:56:43 PM PDT 24
Finished Aug 17 05:57:16 PM PDT 24
Peak memory 248824 kb
Host smart-cde0cb1f-21af-487d-a3f0-2ce9100e8337
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3919943096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3919943096
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1693807328
Short name T410
Test name
Test status
Simulation time 4802544060 ps
CPU time 95.45 seconds
Started Aug 17 05:56:40 PM PDT 24
Finished Aug 17 05:58:16 PM PDT 24
Peak memory 256656 kb
Host smart-323749ba-3f02-43da-963e-0b1887edc300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16938
07328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1693807328
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3605072117
Short name T241
Test name
Test status
Simulation time 1320469850 ps
CPU time 41.25 seconds
Started Aug 17 05:56:44 PM PDT 24
Finished Aug 17 05:57:26 PM PDT 24
Peak memory 256428 kb
Host smart-ef0979d6-3a21-4bf5-add6-4d35eb76908c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36050
72117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3605072117
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2173719554
Short name T322
Test name
Test status
Simulation time 247365387773 ps
CPU time 2521.3 seconds
Started Aug 17 05:56:44 PM PDT 24
Finished Aug 17 06:38:45 PM PDT 24
Peak memory 289852 kb
Host smart-55b99ca1-f9ab-4476-8cbc-a98f818ed44f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173719554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2173719554
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.967021183
Short name T380
Test name
Test status
Simulation time 37105627708 ps
CPU time 1144.47 seconds
Started Aug 17 05:56:41 PM PDT 24
Finished Aug 17 06:15:46 PM PDT 24
Peak memory 286344 kb
Host smart-d36c8378-af73-428e-8150-545f4c93e202
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967021183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.967021183
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3825069756
Short name T517
Test name
Test status
Simulation time 3325620496 ps
CPU time 55.02 seconds
Started Aug 17 05:56:43 PM PDT 24
Finished Aug 17 05:57:38 PM PDT 24
Peak memory 256944 kb
Host smart-616cd33b-a9d6-415b-9b3d-dbf91e62215d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38250
69756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3825069756
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1810717812
Short name T522
Test name
Test status
Simulation time 283180602 ps
CPU time 26.15 seconds
Started Aug 17 05:56:41 PM PDT 24
Finished Aug 17 05:57:08 PM PDT 24
Peak memory 255300 kb
Host smart-60cfd239-b16d-4226-acc9-ff70921d838c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18107
17812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1810717812
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3761235550
Short name T248
Test name
Test status
Simulation time 218811725 ps
CPU time 12 seconds
Started Aug 17 05:56:43 PM PDT 24
Finished Aug 17 05:56:55 PM PDT 24
Peak memory 248812 kb
Host smart-826adee7-ec16-440b-8a7e-252431ab49c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37612
35550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3761235550
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.4086285251
Short name T357
Test name
Test status
Simulation time 656231051 ps
CPU time 21.29 seconds
Started Aug 17 05:56:43 PM PDT 24
Finished Aug 17 05:57:04 PM PDT 24
Peak memory 255876 kb
Host smart-da6dc386-e225-4232-887f-9407d13d028a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40862
85251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.4086285251
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.679228727
Short name T545
Test name
Test status
Simulation time 30120852496 ps
CPU time 1482.82 seconds
Started Aug 17 05:56:44 PM PDT 24
Finished Aug 17 06:21:27 PM PDT 24
Peak memory 289004 kb
Host smart-a226cd5c-2110-4eb2-8c44-ec825665eb17
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679228727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.679228727
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3431654927
Short name T186
Test name
Test status
Simulation time 21429049 ps
CPU time 2.79 seconds
Started Aug 17 05:56:52 PM PDT 24
Finished Aug 17 05:56:55 PM PDT 24
Peak memory 248852 kb
Host smart-ef1f213a-69b6-4b80-ae5c-9af1c7882baf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3431654927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3431654927
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3940764531
Short name T432
Test name
Test status
Simulation time 75581654508 ps
CPU time 1214.59 seconds
Started Aug 17 05:56:52 PM PDT 24
Finished Aug 17 06:17:07 PM PDT 24
Peak memory 273208 kb
Host smart-e0c1e3b6-81a4-47ad-968f-864322e23a4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940764531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3940764531
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3095073125
Short name T588
Test name
Test status
Simulation time 169140272 ps
CPU time 10.79 seconds
Started Aug 17 05:56:52 PM PDT 24
Finished Aug 17 05:57:03 PM PDT 24
Peak memory 248744 kb
Host smart-c43dbc06-a951-4af2-a779-936e74a731c3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3095073125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3095073125
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3610961964
Short name T407
Test name
Test status
Simulation time 857121429 ps
CPU time 87.86 seconds
Started Aug 17 05:56:51 PM PDT 24
Finished Aug 17 05:58:19 PM PDT 24
Peak memory 256140 kb
Host smart-0d52ffcb-c8ca-4ff5-a62d-87a4c7ad8523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36109
61964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3610961964
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.4054215494
Short name T585
Test name
Test status
Simulation time 363350286 ps
CPU time 22.82 seconds
Started Aug 17 05:56:50 PM PDT 24
Finished Aug 17 05:57:13 PM PDT 24
Peak memory 248320 kb
Host smart-ffac8e54-277b-4281-9f0c-9a7d91ed83f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40542
15494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.4054215494
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.27346457
Short name T564
Test name
Test status
Simulation time 47816079621 ps
CPU time 2699.55 seconds
Started Aug 17 05:56:50 PM PDT 24
Finished Aug 17 06:41:50 PM PDT 24
Peak memory 286152 kb
Host smart-7303e24b-338f-43f7-ab19-c4fd49dcb1c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27346457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.27346457
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1919229880
Short name T385
Test name
Test status
Simulation time 75937090566 ps
CPU time 2472.56 seconds
Started Aug 17 05:56:52 PM PDT 24
Finished Aug 17 06:38:04 PM PDT 24
Peak memory 281496 kb
Host smart-1083f016-a51a-45e6-87a0-0c90c0bca990
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919229880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1919229880
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2428434656
Short name T646
Test name
Test status
Simulation time 477598591 ps
CPU time 20.1 seconds
Started Aug 17 05:56:52 PM PDT 24
Finished Aug 17 05:57:12 PM PDT 24
Peak memory 248844 kb
Host smart-f1c59328-bb3a-4707-a6e4-10f0c71a8184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24284
34656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2428434656
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.42444220
Short name T649
Test name
Test status
Simulation time 3132771251 ps
CPU time 25.74 seconds
Started Aug 17 05:56:52 PM PDT 24
Finished Aug 17 05:57:17 PM PDT 24
Peak memory 256560 kb
Host smart-686a8e08-d324-478d-81e6-0576dd711a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42444
220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.42444220
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2113998511
Short name T376
Test name
Test status
Simulation time 85621865 ps
CPU time 6.98 seconds
Started Aug 17 05:56:50 PM PDT 24
Finished Aug 17 05:56:57 PM PDT 24
Peak memory 248824 kb
Host smart-555bc535-3a55-48e0-8ee8-c1de2520fe8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21139
98511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2113998511
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1539824538
Short name T393
Test name
Test status
Simulation time 906713978 ps
CPU time 55.06 seconds
Started Aug 17 05:56:51 PM PDT 24
Finished Aug 17 05:57:46 PM PDT 24
Peak memory 256956 kb
Host smart-1f06a0f7-bad7-4642-a638-4928910029bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15398
24538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1539824538
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1117691068
Short name T197
Test name
Test status
Simulation time 45222049 ps
CPU time 2.88 seconds
Started Aug 17 05:56:58 PM PDT 24
Finished Aug 17 05:57:01 PM PDT 24
Peak memory 248936 kb
Host smart-71d1155e-ae66-444e-886f-36277c585f3c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1117691068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1117691068
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3004898904
Short name T458
Test name
Test status
Simulation time 43491131321 ps
CPU time 1486.48 seconds
Started Aug 17 05:56:50 PM PDT 24
Finished Aug 17 06:21:37 PM PDT 24
Peak memory 273192 kb
Host smart-d4ce3869-2970-4423-b06e-f70b0c4a8c7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004898904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3004898904
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2011670166
Short name T382
Test name
Test status
Simulation time 19697644155 ps
CPU time 63.3 seconds
Started Aug 17 05:57:01 PM PDT 24
Finished Aug 17 05:58:04 PM PDT 24
Peak memory 248796 kb
Host smart-09927346-3546-4324-82c0-ddcaacedc350
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2011670166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2011670166
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1634091192
Short name T378
Test name
Test status
Simulation time 1660412438 ps
CPU time 105.42 seconds
Started Aug 17 05:56:51 PM PDT 24
Finished Aug 17 05:58:36 PM PDT 24
Peak memory 256964 kb
Host smart-23185b1b-14f1-4398-9333-f8ce63dd8ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16340
91192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1634091192
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.654482804
Short name T69
Test name
Test status
Simulation time 777141598 ps
CPU time 35.26 seconds
Started Aug 17 05:56:50 PM PDT 24
Finished Aug 17 05:57:25 PM PDT 24
Peak memory 256984 kb
Host smart-89416d56-9d23-4a48-835b-07740e5df555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65448
2804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.654482804
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.819771115
Short name T303
Test name
Test status
Simulation time 11549815366 ps
CPU time 915.49 seconds
Started Aug 17 05:56:56 PM PDT 24
Finished Aug 17 06:12:11 PM PDT 24
Peak memory 273324 kb
Host smart-b7560020-d361-49f2-8e78-8708bcd8de47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819771115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.819771115
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.288605486
Short name T460
Test name
Test status
Simulation time 136456970948 ps
CPU time 1285.84 seconds
Started Aug 17 05:56:59 PM PDT 24
Finished Aug 17 06:18:25 PM PDT 24
Peak memory 289184 kb
Host smart-27399eb8-b26c-4263-87f1-07c318fd2ff2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288605486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.288605486
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1463314449
Short name T300
Test name
Test status
Simulation time 36607812857 ps
CPU time 385.27 seconds
Started Aug 17 05:56:51 PM PDT 24
Finished Aug 17 06:03:17 PM PDT 24
Peak memory 248856 kb
Host smart-a214eec9-426b-442c-9298-0613090d0255
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463314449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1463314449
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2302162949
Short name T615
Test name
Test status
Simulation time 883220923 ps
CPU time 54.04 seconds
Started Aug 17 05:56:51 PM PDT 24
Finished Aug 17 05:57:45 PM PDT 24
Peak memory 256324 kb
Host smart-70b1ea49-bf4f-4c3a-9a74-982514a7d56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23021
62949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2302162949
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2029235796
Short name T44
Test name
Test status
Simulation time 349484877 ps
CPU time 26.28 seconds
Started Aug 17 05:56:55 PM PDT 24
Finished Aug 17 05:57:21 PM PDT 24
Peak memory 255996 kb
Host smart-c387d632-aec1-4aa1-b8d6-d8477252b18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20292
35796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2029235796
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1553033343
Short name T678
Test name
Test status
Simulation time 116609753 ps
CPU time 15.95 seconds
Started Aug 17 05:56:52 PM PDT 24
Finished Aug 17 05:57:08 PM PDT 24
Peak memory 249416 kb
Host smart-7e633433-87fc-44e9-b42c-2bf1a5108da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15530
33343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1553033343
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1713016554
Short name T508
Test name
Test status
Simulation time 668767812 ps
CPU time 13.28 seconds
Started Aug 17 05:56:51 PM PDT 24
Finished Aug 17 05:57:04 PM PDT 24
Peak memory 256932 kb
Host smart-6b5d34c9-61df-4c8f-8274-6376af4f0a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17130
16554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1713016554
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1193973232
Short name T464
Test name
Test status
Simulation time 42324599738 ps
CPU time 2645.67 seconds
Started Aug 17 05:57:00 PM PDT 24
Finished Aug 17 06:41:06 PM PDT 24
Peak memory 289656 kb
Host smart-f8b86de7-f562-416a-9d14-78edf1e7a9e9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193973232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1193973232
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2843374911
Short name T185
Test name
Test status
Simulation time 157499615 ps
CPU time 4.25 seconds
Started Aug 17 05:56:58 PM PDT 24
Finished Aug 17 05:57:02 PM PDT 24
Peak memory 248932 kb
Host smart-91f23789-e883-4eb3-ad24-26ec20f185c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2843374911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2843374911
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3796943828
Short name T672
Test name
Test status
Simulation time 3145914118 ps
CPU time 67.08 seconds
Started Aug 17 05:56:57 PM PDT 24
Finished Aug 17 05:58:04 PM PDT 24
Peak memory 257096 kb
Host smart-589dfdf9-d842-43f3-a90b-27988e108bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37969
43828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3796943828
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.136137285
Short name T479
Test name
Test status
Simulation time 225013535 ps
CPU time 11.16 seconds
Started Aug 17 05:56:59 PM PDT 24
Finished Aug 17 05:57:10 PM PDT 24
Peak memory 248760 kb
Host smart-3bfa0f32-0460-4e2b-9b75-483265829a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13613
7285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.136137285
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1357951140
Short name T702
Test name
Test status
Simulation time 188024365428 ps
CPU time 2400.15 seconds
Started Aug 17 05:56:58 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 288072 kb
Host smart-25e4d2a7-2291-4813-809d-664f3172f31f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357951140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1357951140
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.792833201
Short name T367
Test name
Test status
Simulation time 48159429244 ps
CPU time 2295.82 seconds
Started Aug 17 05:56:58 PM PDT 24
Finished Aug 17 06:35:14 PM PDT 24
Peak memory 287024 kb
Host smart-0689e674-7d3e-4587-804d-d0403184960f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792833201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.792833201
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2731496114
Short name T288
Test name
Test status
Simulation time 13023062304 ps
CPU time 539.42 seconds
Started Aug 17 05:56:58 PM PDT 24
Finished Aug 17 06:05:58 PM PDT 24
Peak memory 246312 kb
Host smart-50b811ee-02f4-46c1-98e1-16b4faef2c10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731496114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2731496114
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.297256832
Short name T358
Test name
Test status
Simulation time 1099427275 ps
CPU time 15.8 seconds
Started Aug 17 05:56:59 PM PDT 24
Finished Aug 17 05:57:15 PM PDT 24
Peak memory 255004 kb
Host smart-f57631e3-5ef3-4ccc-a47d-fe6c2d9dd569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29725
6832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.297256832
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2498183722
Short name T209
Test name
Test status
Simulation time 167335631 ps
CPU time 15.68 seconds
Started Aug 17 05:56:59 PM PDT 24
Finished Aug 17 05:57:15 PM PDT 24
Peak memory 247988 kb
Host smart-c5f89f81-4b3c-4782-b388-89f0dca8304d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24981
83722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2498183722
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1197556452
Short name T569
Test name
Test status
Simulation time 1647946398 ps
CPU time 29.41 seconds
Started Aug 17 05:56:57 PM PDT 24
Finished Aug 17 05:57:26 PM PDT 24
Peak memory 248220 kb
Host smart-141792a8-000e-4c3e-b4a5-59751a926af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11975
56452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1197556452
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.4066358077
Short name T389
Test name
Test status
Simulation time 562368825 ps
CPU time 15.33 seconds
Started Aug 17 05:56:59 PM PDT 24
Finished Aug 17 05:57:14 PM PDT 24
Peak memory 248788 kb
Host smart-6071b299-a54f-41ec-8da3-36a034e4f4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40663
58077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.4066358077
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.300429141
Short name T190
Test name
Test status
Simulation time 123724371 ps
CPU time 3.36 seconds
Started Aug 17 05:57:06 PM PDT 24
Finished Aug 17 05:57:10 PM PDT 24
Peak memory 249004 kb
Host smart-30e90f0c-33c3-46ac-99d6-9c6102e4e7f5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=300429141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.300429141
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1746380681
Short name T498
Test name
Test status
Simulation time 144452122673 ps
CPU time 2277.02 seconds
Started Aug 17 05:57:06 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 289528 kb
Host smart-9e1525de-d331-4aa6-9cb0-295bed9e1ba1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746380681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1746380681
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.593640935
Short name T349
Test name
Test status
Simulation time 757913624 ps
CPU time 33.77 seconds
Started Aug 17 05:57:09 PM PDT 24
Finished Aug 17 05:57:43 PM PDT 24
Peak memory 248692 kb
Host smart-00fe3804-d3db-413a-b215-f4406dfa882b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=593640935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.593640935
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1701184846
Short name T351
Test name
Test status
Simulation time 306696038 ps
CPU time 22.15 seconds
Started Aug 17 05:57:06 PM PDT 24
Finished Aug 17 05:57:28 PM PDT 24
Peak memory 256308 kb
Host smart-90bfa9bc-d74d-4f0e-a920-78117d7b2e4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17011
84846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1701184846
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3776769182
Short name T447
Test name
Test status
Simulation time 590245223 ps
CPU time 10.43 seconds
Started Aug 17 05:57:07 PM PDT 24
Finished Aug 17 05:57:18 PM PDT 24
Peak memory 248756 kb
Host smart-275302c3-f005-46d4-bd9f-f8eb6b6366f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37767
69182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3776769182
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.143744103
Short name T542
Test name
Test status
Simulation time 17867706468 ps
CPU time 1428.8 seconds
Started Aug 17 05:57:07 PM PDT 24
Finished Aug 17 06:20:56 PM PDT 24
Peak memory 287728 kb
Host smart-44163611-ea3f-46e0-bb72-c04889a505bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143744103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.143744103
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2308581269
Short name T260
Test name
Test status
Simulation time 78920325654 ps
CPU time 1551.18 seconds
Started Aug 17 05:57:08 PM PDT 24
Finished Aug 17 06:23:00 PM PDT 24
Peak memory 289724 kb
Host smart-1372d647-bcac-4221-8957-12b24eb86e43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308581269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2308581269
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3737893137
Short name T282
Test name
Test status
Simulation time 6781572806 ps
CPU time 285.52 seconds
Started Aug 17 05:57:07 PM PDT 24
Finished Aug 17 06:01:52 PM PDT 24
Peak memory 248864 kb
Host smart-3c3a0651-6698-41ad-9425-d794ee790c8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737893137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3737893137
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2591492502
Short name T466
Test name
Test status
Simulation time 1368337883 ps
CPU time 24.31 seconds
Started Aug 17 05:57:07 PM PDT 24
Finished Aug 17 05:57:31 PM PDT 24
Peak memory 256024 kb
Host smart-ead1b27a-6951-4432-b4ae-e9b36b13b483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25914
92502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2591492502
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.108119439
Short name T112
Test name
Test status
Simulation time 353338633 ps
CPU time 23.5 seconds
Started Aug 17 05:57:06 PM PDT 24
Finished Aug 17 05:57:30 PM PDT 24
Peak memory 248144 kb
Host smart-71773b42-6abe-4d58-915f-3eccfeea3088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10811
9439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.108119439
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1563252778
Short name T20
Test name
Test status
Simulation time 492532592 ps
CPU time 8.27 seconds
Started Aug 17 05:57:06 PM PDT 24
Finished Aug 17 05:57:14 PM PDT 24
Peak memory 248772 kb
Host smart-bca31d42-73ba-419e-87fb-638d0d0e3cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15632
52778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1563252778
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3591603505
Short name T395
Test name
Test status
Simulation time 2767381555 ps
CPU time 47.33 seconds
Started Aug 17 05:57:07 PM PDT 24
Finished Aug 17 05:57:55 PM PDT 24
Peak memory 256924 kb
Host smart-4e358f24-bf66-4bb3-a419-fb33f752f8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35916
03505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3591603505
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1803836104
Short name T60
Test name
Test status
Simulation time 3525359137 ps
CPU time 60.19 seconds
Started Aug 17 05:57:05 PM PDT 24
Finished Aug 17 05:58:06 PM PDT 24
Peak memory 256816 kb
Host smart-0b9dd29b-9531-455e-b42e-9954ce61e60a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803836104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1803836104
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3806475690
Short name T188
Test name
Test status
Simulation time 15187140 ps
CPU time 2.95 seconds
Started Aug 17 05:57:19 PM PDT 24
Finished Aug 17 05:57:22 PM PDT 24
Peak memory 249028 kb
Host smart-4bdf9726-cb8a-4883-8753-d865dfe85e05
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3806475690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3806475690
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.860675215
Short name T713
Test name
Test status
Simulation time 539474213 ps
CPU time 16.37 seconds
Started Aug 17 05:57:16 PM PDT 24
Finished Aug 17 05:57:33 PM PDT 24
Peak memory 248788 kb
Host smart-637a9bcb-09dc-4cda-9c2d-9381111b5a87
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=860675215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.860675215
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.612489448
Short name T544
Test name
Test status
Simulation time 605986179 ps
CPU time 29.04 seconds
Started Aug 17 05:57:07 PM PDT 24
Finished Aug 17 05:57:36 PM PDT 24
Peak memory 255948 kb
Host smart-3d4b6bc6-1794-475f-b94b-dcf0a7f5c2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61248
9448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.612489448
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1423692336
Short name T444
Test name
Test status
Simulation time 656318868 ps
CPU time 36.57 seconds
Started Aug 17 05:57:09 PM PDT 24
Finished Aug 17 05:57:46 PM PDT 24
Peak memory 256960 kb
Host smart-85b866e9-5ab3-4097-be13-a287e588d871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14236
92336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1423692336
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3951056015
Short name T648
Test name
Test status
Simulation time 12306622696 ps
CPU time 1432.95 seconds
Started Aug 17 05:57:06 PM PDT 24
Finished Aug 17 06:20:59 PM PDT 24
Peak memory 289664 kb
Host smart-ce4b3c51-da84-419d-abd7-a1543efa3b6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951056015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3951056015
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3351352449
Short name T480
Test name
Test status
Simulation time 15571576646 ps
CPU time 1405.54 seconds
Started Aug 17 05:57:06 PM PDT 24
Finished Aug 17 06:20:32 PM PDT 24
Peak memory 288908 kb
Host smart-d507153d-9e6a-40a9-8a41-23dbac815948
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351352449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3351352449
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.4047274268
Short name T15
Test name
Test status
Simulation time 8519688410 ps
CPU time 188.62 seconds
Started Aug 17 05:57:04 PM PDT 24
Finished Aug 17 06:00:13 PM PDT 24
Peak memory 255460 kb
Host smart-9e59600d-4cc5-4a9b-af19-5414b6b25436
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047274268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.4047274268
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.550835608
Short name T430
Test name
Test status
Simulation time 2077875601 ps
CPU time 25.55 seconds
Started Aug 17 05:57:07 PM PDT 24
Finished Aug 17 05:57:32 PM PDT 24
Peak memory 256112 kb
Host smart-4491cf7b-48a2-4f26-8ed3-3cefb536c91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55083
5608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.550835608
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2766293350
Short name T507
Test name
Test status
Simulation time 595945952 ps
CPU time 10.67 seconds
Started Aug 17 05:57:07 PM PDT 24
Finished Aug 17 05:57:18 PM PDT 24
Peak memory 248840 kb
Host smart-02c1fab5-c9a0-46a3-a5b9-fc7d413ae2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27662
93350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2766293350
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3304849102
Short name T504
Test name
Test status
Simulation time 7369969470 ps
CPU time 28.02 seconds
Started Aug 17 05:57:06 PM PDT 24
Finished Aug 17 05:57:34 PM PDT 24
Peak memory 255940 kb
Host smart-da7d919a-3a3f-45f4-aa73-263505038ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33048
49102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3304849102
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3434376512
Short name T427
Test name
Test status
Simulation time 40200362 ps
CPU time 5.53 seconds
Started Aug 17 05:57:05 PM PDT 24
Finished Aug 17 05:57:11 PM PDT 24
Peak memory 253108 kb
Host smart-1ddee1dc-283a-4b80-9840-8a25e20f2862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34343
76512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3434376512
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3645632996
Short name T70
Test name
Test status
Simulation time 796587410 ps
CPU time 105.78 seconds
Started Aug 17 05:57:14 PM PDT 24
Finished Aug 17 05:59:00 PM PDT 24
Peak memory 256944 kb
Host smart-6b2c4c38-982e-41bf-a86d-1a515f5924da
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645632996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3645632996
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3853527316
Short name T199
Test name
Test status
Simulation time 593910818 ps
CPU time 3.3 seconds
Started Aug 17 05:57:17 PM PDT 24
Finished Aug 17 05:57:21 PM PDT 24
Peak memory 249032 kb
Host smart-26863584-c1bd-418d-8098-d60784c52489
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3853527316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3853527316
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3642447738
Short name T102
Test name
Test status
Simulation time 48392968291 ps
CPU time 2873.92 seconds
Started Aug 17 05:57:13 PM PDT 24
Finished Aug 17 06:45:08 PM PDT 24
Peak memory 281496 kb
Host smart-07beef1b-94d8-4acd-bd44-b9049280c1ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642447738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3642447738
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3225639682
Short name T651
Test name
Test status
Simulation time 212615722 ps
CPU time 12.71 seconds
Started Aug 17 05:57:16 PM PDT 24
Finished Aug 17 05:57:29 PM PDT 24
Peak memory 248776 kb
Host smart-37539cb9-0330-47d6-9aa0-822572123167
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3225639682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3225639682
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1036888940
Short name T547
Test name
Test status
Simulation time 1163195895 ps
CPU time 101.08 seconds
Started Aug 17 05:57:16 PM PDT 24
Finished Aug 17 05:58:57 PM PDT 24
Peak memory 256528 kb
Host smart-fb7b2465-7b3e-4cdc-b475-808c4ee3f58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10368
88940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1036888940
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2303107918
Short name T689
Test name
Test status
Simulation time 1101889704 ps
CPU time 38.66 seconds
Started Aug 17 05:57:13 PM PDT 24
Finished Aug 17 05:57:52 PM PDT 24
Peak memory 248812 kb
Host smart-47ee6ae7-73f2-4073-8d51-b0ff31917fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23031
07918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2303107918
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2627710535
Short name T47
Test name
Test status
Simulation time 46751903706 ps
CPU time 2816.9 seconds
Started Aug 17 05:57:15 PM PDT 24
Finished Aug 17 06:44:12 PM PDT 24
Peak memory 289028 kb
Host smart-3bb494f1-1916-4340-8e41-6ba201100c4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627710535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2627710535
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.153423999
Short name T442
Test name
Test status
Simulation time 48684562783 ps
CPU time 2805.9 seconds
Started Aug 17 05:57:16 PM PDT 24
Finished Aug 17 06:44:02 PM PDT 24
Peak memory 288936 kb
Host smart-5354e420-a750-4400-abb7-8a7d10b06980
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153423999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.153423999
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3699690600
Short name T286
Test name
Test status
Simulation time 15121712036 ps
CPU time 606.05 seconds
Started Aug 17 05:57:12 PM PDT 24
Finished Aug 17 06:07:19 PM PDT 24
Peak memory 248804 kb
Host smart-ee91d5f6-39ac-440a-8989-13466db5256b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699690600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3699690600
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.158366292
Short name T695
Test name
Test status
Simulation time 16242064 ps
CPU time 2.51 seconds
Started Aug 17 05:57:17 PM PDT 24
Finished Aug 17 05:57:20 PM PDT 24
Peak memory 248824 kb
Host smart-34dc77aa-e899-4610-b9d9-97ac5322ab1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15836
6292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.158366292
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2712874500
Short name T703
Test name
Test status
Simulation time 1555749067 ps
CPU time 53.04 seconds
Started Aug 17 05:57:15 PM PDT 24
Finished Aug 17 05:58:08 PM PDT 24
Peak memory 256988 kb
Host smart-493e3ea9-4512-4a8a-b1b8-18441bc0c175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27128
74500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2712874500
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2551103074
Short name T666
Test name
Test status
Simulation time 1230257336 ps
CPU time 17.09 seconds
Started Aug 17 05:57:14 PM PDT 24
Finished Aug 17 05:57:31 PM PDT 24
Peak memory 248328 kb
Host smart-47d80f2e-1304-4f16-9966-fba4d39d511b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25511
03074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2551103074
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.4051804243
Short name T618
Test name
Test status
Simulation time 483837938 ps
CPU time 15.02 seconds
Started Aug 17 05:57:14 PM PDT 24
Finished Aug 17 05:57:29 PM PDT 24
Peak memory 256856 kb
Host smart-354d69f3-f2b3-47b6-9989-fcf2826cb257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40518
04243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.4051804243
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3903207593
Short name T536
Test name
Test status
Simulation time 17315141366 ps
CPU time 1705.73 seconds
Started Aug 17 05:57:15 PM PDT 24
Finished Aug 17 06:25:41 PM PDT 24
Peak memory 289792 kb
Host smart-0d6b4263-e64b-4804-85fe-9b70e886058e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903207593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3903207593
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1589801640
Short name T616
Test name
Test status
Simulation time 12794956814 ps
CPU time 237.91 seconds
Started Aug 17 05:57:13 PM PDT 24
Finished Aug 17 06:01:11 PM PDT 24
Peak memory 265388 kb
Host smart-f8887033-3b8d-4f90-83fc-20c6f2e84c2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589801640 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1589801640
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2523583315
Short name T192
Test name
Test status
Simulation time 63415805 ps
CPU time 4.29 seconds
Started Aug 17 05:57:23 PM PDT 24
Finished Aug 17 05:57:28 PM PDT 24
Peak memory 249008 kb
Host smart-514c6310-b937-4f46-9c82-d03c24b2bf46
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2523583315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2523583315
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3198473850
Short name T515
Test name
Test status
Simulation time 130654323525 ps
CPU time 2186.09 seconds
Started Aug 17 05:57:12 PM PDT 24
Finished Aug 17 06:33:39 PM PDT 24
Peak memory 289780 kb
Host smart-ba844888-90ca-4d10-bb7d-7fd0c5264286
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198473850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3198473850
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2826709942
Short name T345
Test name
Test status
Simulation time 1488099521 ps
CPU time 14.42 seconds
Started Aug 17 05:57:23 PM PDT 24
Finished Aug 17 05:57:37 PM PDT 24
Peak memory 248804 kb
Host smart-e154b00c-05c6-4de0-837d-0bc09b2c46eb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2826709942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2826709942
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.4032706069
Short name T706
Test name
Test status
Simulation time 526784676 ps
CPU time 19.38 seconds
Started Aug 17 05:57:14 PM PDT 24
Finished Aug 17 05:57:33 PM PDT 24
Peak memory 256256 kb
Host smart-ce7d79e8-4721-4a43-b43d-afed9f7c935c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40327
06069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.4032706069
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1157762829
Short name T546
Test name
Test status
Simulation time 471375159 ps
CPU time 25.01 seconds
Started Aug 17 05:57:14 PM PDT 24
Finished Aug 17 05:57:39 PM PDT 24
Peak memory 248772 kb
Host smart-39af8929-d2e0-4020-9f87-4643bfa9fb19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11577
62829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1157762829
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2965883437
Short name T352
Test name
Test status
Simulation time 29093083653 ps
CPU time 1568.29 seconds
Started Aug 17 05:57:18 PM PDT 24
Finished Aug 17 06:23:26 PM PDT 24
Peak memory 268344 kb
Host smart-78d22c46-bbeb-44d7-8a08-2e7e03cc0513
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965883437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2965883437
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3489557088
Short name T640
Test name
Test status
Simulation time 8136347809 ps
CPU time 334.36 seconds
Started Aug 17 05:57:15 PM PDT 24
Finished Aug 17 06:02:49 PM PDT 24
Peak memory 248820 kb
Host smart-01325d67-9c37-49b9-8fc3-9a9d2b879b85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489557088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3489557088
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2019111052
Short name T346
Test name
Test status
Simulation time 1698980743 ps
CPU time 46.78 seconds
Started Aug 17 05:57:15 PM PDT 24
Finished Aug 17 05:58:02 PM PDT 24
Peak memory 254672 kb
Host smart-d80b5195-bd4b-4152-bf1c-9f27ffb73aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20191
11052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2019111052
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1367126493
Short name T527
Test name
Test status
Simulation time 567933962 ps
CPU time 34.86 seconds
Started Aug 17 05:57:15 PM PDT 24
Finished Aug 17 05:57:50 PM PDT 24
Peak memory 256336 kb
Host smart-7982755b-3e51-4868-9c13-e18d4ba6cb98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13671
26493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1367126493
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2828564624
Short name T225
Test name
Test status
Simulation time 220117496 ps
CPU time 8.78 seconds
Started Aug 17 05:57:12 PM PDT 24
Finished Aug 17 05:57:21 PM PDT 24
Peak memory 253960 kb
Host smart-dee20785-1895-4243-a02f-5c26eb10b18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28285
64624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2828564624
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1167800875
Short name T255
Test name
Test status
Simulation time 276885182 ps
CPU time 27.47 seconds
Started Aug 17 05:57:16 PM PDT 24
Finished Aug 17 05:57:44 PM PDT 24
Peak memory 257008 kb
Host smart-8d548d49-1555-4307-9386-ab5004b27173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11678
00875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1167800875
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1523716620
Short name T500
Test name
Test status
Simulation time 17709409591 ps
CPU time 1603.72 seconds
Started Aug 17 05:57:21 PM PDT 24
Finished Aug 17 06:24:05 PM PDT 24
Peak memory 289176 kb
Host smart-65338889-fd08-40b4-93ab-c3dee4d0d54e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523716620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1523716620
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.838248525
Short name T194
Test name
Test status
Simulation time 29061624 ps
CPU time 3.15 seconds
Started Aug 17 05:56:14 PM PDT 24
Finished Aug 17 05:56:17 PM PDT 24
Peak memory 249012 kb
Host smart-b41c5a04-adab-42cb-a94b-11257ad1c4e5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=838248525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.838248525
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1705205915
Short name T582
Test name
Test status
Simulation time 38799462193 ps
CPU time 2206.11 seconds
Started Aug 17 05:56:14 PM PDT 24
Finished Aug 17 06:33:00 PM PDT 24
Peak memory 288784 kb
Host smart-62df5b7d-c093-47a2-9b8c-438d82c61324
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705205915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1705205915
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3489498371
Short name T586
Test name
Test status
Simulation time 267940740 ps
CPU time 14 seconds
Started Aug 17 05:56:13 PM PDT 24
Finished Aug 17 05:56:27 PM PDT 24
Peak memory 248784 kb
Host smart-305bdfcb-fb35-40d5-b4ee-192abd8cdd3b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3489498371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3489498371
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.846356347
Short name T587
Test name
Test status
Simulation time 5326687319 ps
CPU time 108.33 seconds
Started Aug 17 05:56:11 PM PDT 24
Finished Aug 17 05:57:59 PM PDT 24
Peak memory 256560 kb
Host smart-20034286-c52b-4f2b-a44f-6a988811d699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84635
6347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.846356347
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.258944990
Short name T421
Test name
Test status
Simulation time 82330320 ps
CPU time 8.62 seconds
Started Aug 17 05:56:11 PM PDT 24
Finished Aug 17 05:56:20 PM PDT 24
Peak memory 256952 kb
Host smart-69f3d987-e28a-4d6b-b900-f04c2d7e3969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25894
4990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.258944990
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2931389184
Short name T537
Test name
Test status
Simulation time 52654793191 ps
CPU time 1185.14 seconds
Started Aug 17 05:56:13 PM PDT 24
Finished Aug 17 06:15:59 PM PDT 24
Peak memory 282628 kb
Host smart-60cb993e-61ba-4fc9-aeba-3062d331e109
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931389184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2931389184
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.396391245
Short name T208
Test name
Test status
Simulation time 49939549467 ps
CPU time 1306.14 seconds
Started Aug 17 05:56:13 PM PDT 24
Finished Aug 17 06:17:59 PM PDT 24
Peak memory 289136 kb
Host smart-d4f8db72-b548-4e7b-ba33-b4744b181819
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396391245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.396391245
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2433779086
Short name T486
Test name
Test status
Simulation time 20354334442 ps
CPU time 519.47 seconds
Started Aug 17 05:56:12 PM PDT 24
Finished Aug 17 06:04:52 PM PDT 24
Peak memory 248892 kb
Host smart-82c2a440-d648-4d5b-9b97-fbb67a7eae47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433779086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2433779086
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.4203310240
Short name T559
Test name
Test status
Simulation time 2199447570 ps
CPU time 40.11 seconds
Started Aug 17 05:56:13 PM PDT 24
Finished Aug 17 05:56:53 PM PDT 24
Peak memory 248848 kb
Host smart-5d3b82ba-690d-476f-a7ff-252b2ba6dd28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42033
10240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.4203310240
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3736297283
Short name T449
Test name
Test status
Simulation time 682893230 ps
CPU time 14.06 seconds
Started Aug 17 05:56:13 PM PDT 24
Finished Aug 17 05:56:27 PM PDT 24
Peak memory 248132 kb
Host smart-4788a61c-4e86-4c43-a0fc-601fa39e9af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37362
97283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3736297283
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.386099045
Short name T10
Test name
Test status
Simulation time 706063261 ps
CPU time 21.3 seconds
Started Aug 17 05:56:12 PM PDT 24
Finished Aug 17 05:56:33 PM PDT 24
Peak memory 270952 kb
Host smart-d49819fb-3617-4140-b5a1-9b07196d4db1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=386099045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.386099045
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.240394133
Short name T700
Test name
Test status
Simulation time 1135010024 ps
CPU time 38.69 seconds
Started Aug 17 05:56:13 PM PDT 24
Finished Aug 17 05:56:51 PM PDT 24
Peak memory 248228 kb
Host smart-1015578e-81f3-48a3-9e6c-88851e0409f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24039
4133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.240394133
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.840180910
Short name T356
Test name
Test status
Simulation time 4584292099 ps
CPU time 71.38 seconds
Started Aug 17 05:56:10 PM PDT 24
Finished Aug 17 05:57:22 PM PDT 24
Peak memory 256960 kb
Host smart-b125c125-b219-4717-b60b-a56b5b96067d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84018
0910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.840180910
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3249505197
Short name T36
Test name
Test status
Simulation time 469183322295 ps
CPU time 2987.8 seconds
Started Aug 17 05:56:12 PM PDT 24
Finished Aug 17 06:46:01 PM PDT 24
Peak memory 289520 kb
Host smart-ee2299a5-fa84-4988-b299-23670096fe43
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249505197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3249505197
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2224593351
Short name T73
Test name
Test status
Simulation time 207919282663 ps
CPU time 2321.37 seconds
Started Aug 17 05:57:26 PM PDT 24
Finished Aug 17 06:36:07 PM PDT 24
Peak memory 272976 kb
Host smart-d90160c5-d0f4-434d-b04d-b861404e4780
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224593351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2224593351
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.4290181856
Short name T551
Test name
Test status
Simulation time 5680095055 ps
CPU time 82.12 seconds
Started Aug 17 05:57:25 PM PDT 24
Finished Aug 17 05:58:47 PM PDT 24
Peak memory 256012 kb
Host smart-f470cd05-0660-4fef-a3a7-5ba2909c5504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42901
81856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.4290181856
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.305493007
Short name T642
Test name
Test status
Simulation time 374367704 ps
CPU time 28.38 seconds
Started Aug 17 05:57:23 PM PDT 24
Finished Aug 17 05:57:51 PM PDT 24
Peak memory 255244 kb
Host smart-c432aff4-debe-4a86-99f9-799fb849ed24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30549
3007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.305493007
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2776027299
Short name T272
Test name
Test status
Simulation time 34707433452 ps
CPU time 1012.43 seconds
Started Aug 17 05:57:23 PM PDT 24
Finished Aug 17 06:14:16 PM PDT 24
Peak memory 282656 kb
Host smart-2c891549-660f-4b1a-8a73-581bf49c10ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776027299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2776027299
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3615394195
Short name T264
Test name
Test status
Simulation time 247033166 ps
CPU time 20.91 seconds
Started Aug 17 05:57:23 PM PDT 24
Finished Aug 17 05:57:44 PM PDT 24
Peak memory 248864 kb
Host smart-50ce97e8-e18c-4cf0-b737-d389135ee934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36153
94195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3615394195
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1183073249
Short name T645
Test name
Test status
Simulation time 1136606603 ps
CPU time 21 seconds
Started Aug 17 05:57:24 PM PDT 24
Finished Aug 17 05:57:45 PM PDT 24
Peak memory 248360 kb
Host smart-3f388510-8b99-4165-b488-b87553ffbe82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11830
73249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1183073249
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1983236463
Short name T236
Test name
Test status
Simulation time 901699357 ps
CPU time 61.75 seconds
Started Aug 17 05:57:22 PM PDT 24
Finished Aug 17 05:58:24 PM PDT 24
Peak memory 248760 kb
Host smart-58ea41a4-00f3-4d8a-b9fd-7041e1427163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19832
36463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1983236463
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2634094211
Short name T341
Test name
Test status
Simulation time 1665147354 ps
CPU time 25.3 seconds
Started Aug 17 05:57:23 PM PDT 24
Finished Aug 17 05:57:49 PM PDT 24
Peak memory 256988 kb
Host smart-921d6003-c9ec-4626-967e-8ade4ddd1cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26340
94211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2634094211
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.586284331
Short name T259
Test name
Test status
Simulation time 4115002448 ps
CPU time 285.34 seconds
Started Aug 17 05:57:21 PM PDT 24
Finished Aug 17 06:02:07 PM PDT 24
Peak memory 253100 kb
Host smart-a74e07b6-2dd0-4cd2-8654-5a0eb56c63a6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586284331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.586284331
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.851484397
Short name T12
Test name
Test status
Simulation time 5634125175 ps
CPU time 120.76 seconds
Started Aug 17 05:57:23 PM PDT 24
Finished Aug 17 05:59:24 PM PDT 24
Peak memory 256992 kb
Host smart-ebfd9200-f943-4bdd-b818-8470f573028a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85148
4397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.851484397
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.123788305
Short name T437
Test name
Test status
Simulation time 959000778 ps
CPU time 18.89 seconds
Started Aug 17 05:57:24 PM PDT 24
Finished Aug 17 05:57:43 PM PDT 24
Peak memory 256940 kb
Host smart-a58cc4a8-6297-4724-b399-2abcceb67d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12378
8305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.123788305
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3609850128
Short name T296
Test name
Test status
Simulation time 19790078581 ps
CPU time 1090.25 seconds
Started Aug 17 05:57:24 PM PDT 24
Finished Aug 17 06:15:35 PM PDT 24
Peak memory 265148 kb
Host smart-c0cb0cd1-5a07-44c8-83a2-480cf4df9331
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609850128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3609850128
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2561881766
Short name T249
Test name
Test status
Simulation time 49680981259 ps
CPU time 2827.68 seconds
Started Aug 17 05:57:23 PM PDT 24
Finished Aug 17 06:44:31 PM PDT 24
Peak memory 289680 kb
Host smart-bdd24024-4684-4e30-9f0b-a94b47ac5612
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561881766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2561881766
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.629349174
Short name T580
Test name
Test status
Simulation time 2837055592 ps
CPU time 124.94 seconds
Started Aug 17 05:57:24 PM PDT 24
Finished Aug 17 05:59:29 PM PDT 24
Peak memory 248836 kb
Host smart-84978417-ce6b-4e6f-a206-b0f866d55547
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629349174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.629349174
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.980582521
Short name T21
Test name
Test status
Simulation time 1610877482 ps
CPU time 25.14 seconds
Started Aug 17 05:57:24 PM PDT 24
Finished Aug 17 05:57:49 PM PDT 24
Peak memory 255532 kb
Host smart-85a818c3-cf14-4034-8eb6-88ae136a6204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98058
2521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.980582521
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1673596288
Short name T679
Test name
Test status
Simulation time 1507402650 ps
CPU time 23.86 seconds
Started Aug 17 05:57:20 PM PDT 24
Finished Aug 17 05:57:44 PM PDT 24
Peak memory 257024 kb
Host smart-d6681507-ea55-48ac-91ee-39532fd440f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16735
96288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1673596288
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3590110684
Short name T686
Test name
Test status
Simulation time 3279187769 ps
CPU time 46.06 seconds
Started Aug 17 05:57:23 PM PDT 24
Finished Aug 17 05:58:09 PM PDT 24
Peak memory 256028 kb
Host smart-6c8bbf43-3a59-4828-9fac-585e216c30b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35901
10684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3590110684
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1356598084
Short name T218
Test name
Test status
Simulation time 264059233 ps
CPU time 30.07 seconds
Started Aug 17 05:57:24 PM PDT 24
Finished Aug 17 05:57:54 PM PDT 24
Peak memory 256944 kb
Host smart-8da20ddb-a84a-4a2d-8d10-59e3f199fd21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13565
98084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1356598084
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1299653896
Short name T92
Test name
Test status
Simulation time 173348404450 ps
CPU time 2613.52 seconds
Started Aug 17 05:57:30 PM PDT 24
Finished Aug 17 06:41:03 PM PDT 24
Peak memory 289780 kb
Host smart-f50e169b-f2ac-46e7-97b9-9fd877996d2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299653896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1299653896
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1305737023
Short name T396
Test name
Test status
Simulation time 911543053 ps
CPU time 50.45 seconds
Started Aug 17 05:57:30 PM PDT 24
Finished Aug 17 05:58:21 PM PDT 24
Peak memory 256972 kb
Host smart-44a8c5e8-298a-4775-b495-6a31afbea19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13057
37023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1305737023
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2715755900
Short name T665
Test name
Test status
Simulation time 787904892 ps
CPU time 47.12 seconds
Started Aug 17 05:57:31 PM PDT 24
Finished Aug 17 05:58:18 PM PDT 24
Peak memory 248888 kb
Host smart-4a577269-5788-4e47-a581-0ccac9a664d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27157
55900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2715755900
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.899519264
Short name T18
Test name
Test status
Simulation time 43068791930 ps
CPU time 2473.44 seconds
Started Aug 17 05:57:33 PM PDT 24
Finished Aug 17 06:38:47 PM PDT 24
Peak memory 288844 kb
Host smart-5be3c5a2-dbd5-4a71-8cbb-62cf1fac8131
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899519264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.899519264
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3542453055
Short name T643
Test name
Test status
Simulation time 128361705550 ps
CPU time 2137.32 seconds
Started Aug 17 05:57:29 PM PDT 24
Finished Aug 17 06:33:07 PM PDT 24
Peak memory 288748 kb
Host smart-a8767900-0134-438d-b253-cb3a7386673f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542453055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3542453055
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2932347471
Short name T591
Test name
Test status
Simulation time 5964379856 ps
CPU time 242.8 seconds
Started Aug 17 05:57:30 PM PDT 24
Finished Aug 17 06:01:33 PM PDT 24
Peak memory 248832 kb
Host smart-9a960f9f-cb26-45b5-aecb-5ca29973ad42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932347471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2932347471
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3822917985
Short name T532
Test name
Test status
Simulation time 148045143 ps
CPU time 4.39 seconds
Started Aug 17 05:57:30 PM PDT 24
Finished Aug 17 05:57:35 PM PDT 24
Peak memory 248812 kb
Host smart-51df3258-5124-4a3f-b2fa-c113ed1291cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38229
17985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3822917985
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.805826156
Short name T227
Test name
Test status
Simulation time 953487383 ps
CPU time 31.65 seconds
Started Aug 17 05:57:27 PM PDT 24
Finished Aug 17 05:57:59 PM PDT 24
Peak memory 248256 kb
Host smart-c9dbcb83-b60a-4939-9690-261435aa1db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80582
6156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.805826156
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4088294316
Short name T710
Test name
Test status
Simulation time 547540258 ps
CPU time 30.55 seconds
Started Aug 17 05:57:32 PM PDT 24
Finished Aug 17 05:58:03 PM PDT 24
Peak memory 256904 kb
Host smart-b4118e37-fb16-45bd-acb5-ec18dfb094ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40882
94316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4088294316
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1165800904
Short name T62
Test name
Test status
Simulation time 36983239349 ps
CPU time 2400.31 seconds
Started Aug 17 05:57:29 PM PDT 24
Finished Aug 17 06:37:30 PM PDT 24
Peak memory 289420 kb
Host smart-ed02e32e-37d5-497a-9b44-e8ee73c2014d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165800904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1165800904
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3352088111
Short name T510
Test name
Test status
Simulation time 1755570815 ps
CPU time 141.93 seconds
Started Aug 17 05:57:28 PM PDT 24
Finished Aug 17 05:59:51 PM PDT 24
Peak memory 256964 kb
Host smart-ddef8e6d-ca9d-4127-85b9-fc3b7ca2f8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33520
88111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3352088111
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.365777586
Short name T394
Test name
Test status
Simulation time 8313390263 ps
CPU time 74.03 seconds
Started Aug 17 05:57:28 PM PDT 24
Finished Aug 17 05:58:42 PM PDT 24
Peak memory 248584 kb
Host smart-22886a16-9e1c-470f-aaf1-fa48dc3118f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36577
7586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.365777586
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.721747108
Short name T535
Test name
Test status
Simulation time 319454251876 ps
CPU time 1539.76 seconds
Started Aug 17 05:57:28 PM PDT 24
Finished Aug 17 06:23:08 PM PDT 24
Peak memory 272940 kb
Host smart-cfe4a90a-5f60-4b14-99da-61ea57dafc38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721747108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.721747108
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1420346823
Short name T647
Test name
Test status
Simulation time 1708592089 ps
CPU time 70.49 seconds
Started Aug 17 05:57:29 PM PDT 24
Finished Aug 17 05:58:39 PM PDT 24
Peak memory 254168 kb
Host smart-1466377b-2190-4ad8-862f-7c95946cee2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420346823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1420346823
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1440578101
Short name T570
Test name
Test status
Simulation time 2461765772 ps
CPU time 37.74 seconds
Started Aug 17 05:57:29 PM PDT 24
Finished Aug 17 05:58:07 PM PDT 24
Peak memory 257044 kb
Host smart-7afbab42-7104-483e-98f9-5a5e76cda2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14405
78101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1440578101
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3326020177
Short name T502
Test name
Test status
Simulation time 607089043 ps
CPU time 43.3 seconds
Started Aug 17 05:57:29 PM PDT 24
Finished Aug 17 05:58:12 PM PDT 24
Peak memory 248864 kb
Host smart-a7626a85-3cb7-4a42-bfec-526d7bdaab44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33260
20177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3326020177
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2253887593
Short name T232
Test name
Test status
Simulation time 1546397345 ps
CPU time 32.75 seconds
Started Aug 17 05:57:32 PM PDT 24
Finished Aug 17 05:58:05 PM PDT 24
Peak memory 248792 kb
Host smart-92259593-1aef-48c5-837a-534f15eb4a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22538
87593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2253887593
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3237525887
Short name T370
Test name
Test status
Simulation time 1090386071 ps
CPU time 15.6 seconds
Started Aug 17 05:57:30 PM PDT 24
Finished Aug 17 05:57:45 PM PDT 24
Peak memory 256776 kb
Host smart-bb1d702d-dd40-4e35-9f2f-42e316d7904c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32375
25887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3237525887
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1354602599
Short name T660
Test name
Test status
Simulation time 24021043859 ps
CPU time 1572 seconds
Started Aug 17 05:57:42 PM PDT 24
Finished Aug 17 06:23:54 PM PDT 24
Peak memory 273332 kb
Host smart-84e9d38b-647f-4720-98f1-98a03b799075
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354602599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1354602599
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.819338395
Short name T528
Test name
Test status
Simulation time 7517705966 ps
CPU time 278.28 seconds
Started Aug 17 05:57:38 PM PDT 24
Finished Aug 17 06:02:16 PM PDT 24
Peak memory 256296 kb
Host smart-ac8534d2-6020-44f6-bbcc-88ca860dc47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81933
8395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.819338395
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.4262794453
Short name T568
Test name
Test status
Simulation time 2852105502 ps
CPU time 45.88 seconds
Started Aug 17 05:57:37 PM PDT 24
Finished Aug 17 05:58:23 PM PDT 24
Peak memory 257092 kb
Host smart-12213c20-3736-4d42-852c-4f3bea28fb87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42627
94453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.4262794453
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.315136033
Short name T565
Test name
Test status
Simulation time 25813419622 ps
CPU time 1564.95 seconds
Started Aug 17 05:57:38 PM PDT 24
Finished Aug 17 06:23:43 PM PDT 24
Peak memory 273424 kb
Host smart-bee828a3-87b3-4eb7-adb0-e445603fb62b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315136033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.315136033
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1416109125
Short name T381
Test name
Test status
Simulation time 30432498625 ps
CPU time 897.44 seconds
Started Aug 17 05:57:39 PM PDT 24
Finished Aug 17 06:12:37 PM PDT 24
Peak memory 269252 kb
Host smart-353e42bc-88e9-4874-afb4-bd4d48eb0d66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416109125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1416109125
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3626190152
Short name T468
Test name
Test status
Simulation time 8848244723 ps
CPU time 363.21 seconds
Started Aug 17 05:57:36 PM PDT 24
Finished Aug 17 06:03:40 PM PDT 24
Peak memory 247768 kb
Host smart-4b9363c2-0f7d-4ab0-9a96-a117feef62de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626190152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3626190152
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1258115063
Short name T634
Test name
Test status
Simulation time 788217390 ps
CPU time 46.23 seconds
Started Aug 17 05:57:41 PM PDT 24
Finished Aug 17 05:58:27 PM PDT 24
Peak memory 248772 kb
Host smart-59dfc4f4-dda0-48da-89e6-c26a0525049f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12581
15063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1258115063
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3989073823
Short name T245
Test name
Test status
Simulation time 948600290 ps
CPU time 15.04 seconds
Started Aug 17 05:57:39 PM PDT 24
Finished Aug 17 05:57:54 PM PDT 24
Peak memory 248316 kb
Host smart-bf9e28fc-c860-4aa3-947c-3510dad0c272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39890
73823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3989073823
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1712344741
Short name T561
Test name
Test status
Simulation time 131717958 ps
CPU time 14.78 seconds
Started Aug 17 05:57:38 PM PDT 24
Finished Aug 17 05:57:53 PM PDT 24
Peak memory 256964 kb
Host smart-a8824011-1558-44aa-9a48-3723b8d0fe3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17123
44741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1712344741
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.925064490
Short name T549
Test name
Test status
Simulation time 3487502952 ps
CPU time 263.14 seconds
Started Aug 17 05:57:39 PM PDT 24
Finished Aug 17 06:02:02 PM PDT 24
Peak memory 267004 kb
Host smart-1344a608-095c-4b2b-b630-5a1438ef6797
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925064490 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.925064490
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1591566933
Short name T7
Test name
Test status
Simulation time 48295585744 ps
CPU time 2525.54 seconds
Started Aug 17 05:57:41 PM PDT 24
Finished Aug 17 06:39:47 PM PDT 24
Peak memory 284668 kb
Host smart-aa05cd97-0e75-4d54-bd73-5ab8ca9e0b0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591566933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1591566933
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1013103012
Short name T265
Test name
Test status
Simulation time 3929217392 ps
CPU time 212.4 seconds
Started Aug 17 05:57:39 PM PDT 24
Finished Aug 17 06:01:12 PM PDT 24
Peak memory 256260 kb
Host smart-65a23c1b-17c6-456c-9f16-57b9eaaa0c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10131
03012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1013103012
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.403469439
Short name T373
Test name
Test status
Simulation time 675818273 ps
CPU time 32.21 seconds
Started Aug 17 05:57:40 PM PDT 24
Finished Aug 17 05:58:13 PM PDT 24
Peak memory 256964 kb
Host smart-c70a51f4-671d-4ee2-8c8e-af57ce371e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40346
9439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.403469439
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2026943835
Short name T469
Test name
Test status
Simulation time 15159155455 ps
CPU time 1421.04 seconds
Started Aug 17 05:57:40 PM PDT 24
Finished Aug 17 06:21:21 PM PDT 24
Peak memory 281624 kb
Host smart-bc0c117c-44ef-47d8-93ab-033f5f14b62b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026943835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2026943835
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3215948558
Short name T516
Test name
Test status
Simulation time 31749729710 ps
CPU time 1935.05 seconds
Started Aug 17 05:57:38 PM PDT 24
Finished Aug 17 06:29:53 PM PDT 24
Peak memory 273464 kb
Host smart-0cf687a2-fc9f-4481-a1e7-8c09b5fdcf3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215948558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3215948558
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3110176804
Short name T16
Test name
Test status
Simulation time 4755856171 ps
CPU time 201.56 seconds
Started Aug 17 05:57:40 PM PDT 24
Finished Aug 17 06:01:02 PM PDT 24
Peak memory 254560 kb
Host smart-55d6c5c7-1534-469e-a462-a9887cde302b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110176804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3110176804
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2706756752
Short name T692
Test name
Test status
Simulation time 4019983577 ps
CPU time 21.05 seconds
Started Aug 17 05:57:40 PM PDT 24
Finished Aug 17 05:58:01 PM PDT 24
Peak memory 248944 kb
Host smart-66e69ad9-dff2-4aba-8277-d7d69dfc8b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27067
56752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2706756752
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1491264883
Short name T659
Test name
Test status
Simulation time 3765112872 ps
CPU time 62.11 seconds
Started Aug 17 05:57:40 PM PDT 24
Finished Aug 17 05:58:42 PM PDT 24
Peak memory 257072 kb
Host smart-88e74137-e6b3-46a7-95e6-f9c02d45a63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14912
64883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1491264883
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1291227328
Short name T576
Test name
Test status
Simulation time 1309929013 ps
CPU time 52.23 seconds
Started Aug 17 05:57:38 PM PDT 24
Finished Aug 17 05:58:30 PM PDT 24
Peak memory 248312 kb
Host smart-7485aa54-f5dc-406a-b66a-3cd328996294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12912
27328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1291227328
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3693334620
Short name T567
Test name
Test status
Simulation time 1926768513 ps
CPU time 34.3 seconds
Started Aug 17 05:57:41 PM PDT 24
Finished Aug 17 05:58:15 PM PDT 24
Peak memory 256356 kb
Host smart-3d8d8691-5525-43af-ba97-de614ffca3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36933
34620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3693334620
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2036106957
Short name T698
Test name
Test status
Simulation time 189714319501 ps
CPU time 2751.77 seconds
Started Aug 17 05:57:39 PM PDT 24
Finished Aug 17 06:43:31 PM PDT 24
Peak memory 287892 kb
Host smart-10a37988-0b26-4e76-b314-8d8ae4a2d79a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036106957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2036106957
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3144489403
Short name T95
Test name
Test status
Simulation time 51855795286 ps
CPU time 3009.95 seconds
Started Aug 17 05:57:47 PM PDT 24
Finished Aug 17 06:47:57 PM PDT 24
Peak memory 289772 kb
Host smart-5d0e8848-9d5f-4b82-ad07-f41c2008c51e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144489403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3144489403
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3928874433
Short name T471
Test name
Test status
Simulation time 822912353 ps
CPU time 20.82 seconds
Started Aug 17 05:57:48 PM PDT 24
Finished Aug 17 05:58:09 PM PDT 24
Peak memory 256548 kb
Host smart-ab4c4ec7-74eb-4610-9c93-aa944af2b4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39288
74433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3928874433
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.755028005
Short name T205
Test name
Test status
Simulation time 1391439557 ps
CPU time 50.44 seconds
Started Aug 17 05:57:46 PM PDT 24
Finished Aug 17 05:58:37 PM PDT 24
Peak memory 248856 kb
Host smart-c3848efe-a63b-4b1e-a6c6-a5556479cf6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75502
8005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.755028005
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1144271906
Short name T305
Test name
Test status
Simulation time 44053302876 ps
CPU time 2522.14 seconds
Started Aug 17 05:57:47 PM PDT 24
Finished Aug 17 06:39:50 PM PDT 24
Peak memory 288976 kb
Host smart-e285d6a5-6a92-4830-83b6-89f413dfdc19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144271906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1144271906
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3638287785
Short name T497
Test name
Test status
Simulation time 15454081177 ps
CPU time 1206.38 seconds
Started Aug 17 05:57:46 PM PDT 24
Finished Aug 17 06:17:53 PM PDT 24
Peak memory 272732 kb
Host smart-d7394583-7b7e-49b0-a391-a9e8fa05bc18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638287785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3638287785
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2414078223
Short name T443
Test name
Test status
Simulation time 320723218 ps
CPU time 13.04 seconds
Started Aug 17 05:57:55 PM PDT 24
Finished Aug 17 05:58:09 PM PDT 24
Peak memory 248768 kb
Host smart-b797da12-cd28-41c9-bb7b-64ecd504e32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24140
78223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2414078223
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.578748940
Short name T50
Test name
Test status
Simulation time 681851256 ps
CPU time 34.57 seconds
Started Aug 17 05:57:56 PM PDT 24
Finished Aug 17 05:58:31 PM PDT 24
Peak memory 248176 kb
Host smart-e1d5becf-edfa-41e2-8858-d30b0630bacd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57874
8940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.578748940
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2925675797
Short name T525
Test name
Test status
Simulation time 312361519 ps
CPU time 10.83 seconds
Started Aug 17 05:57:47 PM PDT 24
Finished Aug 17 05:57:58 PM PDT 24
Peak memory 256048 kb
Host smart-54d61f77-52e8-4073-9d3a-2f88ebb66004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29256
75797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2925675797
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3764994712
Short name T375
Test name
Test status
Simulation time 608616801 ps
CPU time 44.53 seconds
Started Aug 17 05:57:38 PM PDT 24
Finished Aug 17 05:58:23 PM PDT 24
Peak memory 256964 kb
Host smart-10f248d5-cb7f-43f4-8db9-1a140f732d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37649
94712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3764994712
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2028789309
Short name T29
Test name
Test status
Simulation time 7627181419 ps
CPU time 69.81 seconds
Started Aug 17 05:57:48 PM PDT 24
Finished Aug 17 05:58:58 PM PDT 24
Peak memory 265464 kb
Host smart-473cb9fe-52d3-4a02-b7a8-6178cd2b8bc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028789309 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2028789309
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3912712651
Short name T91
Test name
Test status
Simulation time 175539891439 ps
CPU time 1662.86 seconds
Started Aug 17 05:57:47 PM PDT 24
Finished Aug 17 06:25:31 PM PDT 24
Peak memory 273280 kb
Host smart-675d2de9-ad49-4978-80e7-a0f3119e438e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912712651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3912712651
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2151985265
Short name T531
Test name
Test status
Simulation time 1024108475 ps
CPU time 33.76 seconds
Started Aug 17 05:57:46 PM PDT 24
Finished Aug 17 05:58:20 PM PDT 24
Peak memory 256112 kb
Host smart-68f85339-af36-4205-bc22-5f1472d0d722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21519
85265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2151985265
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2169758308
Short name T68
Test name
Test status
Simulation time 371063447 ps
CPU time 28.07 seconds
Started Aug 17 05:57:55 PM PDT 24
Finished Aug 17 05:58:23 PM PDT 24
Peak memory 248780 kb
Host smart-2af07ab1-ba90-4b94-997d-1e3693fdc18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21697
58308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2169758308
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.708992883
Short name T704
Test name
Test status
Simulation time 39610964347 ps
CPU time 964.04 seconds
Started Aug 17 05:57:47 PM PDT 24
Finished Aug 17 06:13:51 PM PDT 24
Peak memory 289512 kb
Host smart-cd8ed1aa-53a3-4939-98bc-54d06a6a2114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708992883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.708992883
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2415893142
Short name T386
Test name
Test status
Simulation time 118988549411 ps
CPU time 3556.93 seconds
Started Aug 17 05:57:49 PM PDT 24
Finished Aug 17 06:57:06 PM PDT 24
Peak memory 289824 kb
Host smart-03de85df-16e2-4ded-b0bf-96575a06ba79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415893142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2415893142
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3612004011
Short name T541
Test name
Test status
Simulation time 821229179 ps
CPU time 66.82 seconds
Started Aug 17 05:57:49 PM PDT 24
Finished Aug 17 05:58:56 PM PDT 24
Peak memory 255916 kb
Host smart-3bcde74f-f084-4bd0-9e59-d0af707a79e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36120
04011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3612004011
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2573246662
Short name T606
Test name
Test status
Simulation time 171205918 ps
CPU time 9.91 seconds
Started Aug 17 05:57:54 PM PDT 24
Finished Aug 17 05:58:04 PM PDT 24
Peak memory 248248 kb
Host smart-720b5399-07e5-4340-a63e-4e4e2d5feaad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25732
46662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2573246662
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.708637972
Short name T78
Test name
Test status
Simulation time 107717087 ps
CPU time 12.19 seconds
Started Aug 17 05:57:49 PM PDT 24
Finished Aug 17 05:58:01 PM PDT 24
Peak memory 248152 kb
Host smart-b4c846e7-e41b-4b54-9c75-a29461531490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70863
7972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.708637972
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2343414961
Short name T584
Test name
Test status
Simulation time 29029664 ps
CPU time 4.46 seconds
Started Aug 17 05:57:47 PM PDT 24
Finished Aug 17 05:57:52 PM PDT 24
Peak memory 251700 kb
Host smart-0c561d7f-1f0e-4677-87da-2f57de8f6531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23434
14961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2343414961
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2609133079
Short name T533
Test name
Test status
Simulation time 80611121634 ps
CPU time 1451.44 seconds
Started Aug 17 05:57:47 PM PDT 24
Finished Aug 17 06:21:59 PM PDT 24
Peak memory 288008 kb
Host smart-246ad3f5-278d-4d84-a69f-50f1fc5e2c5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609133079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2609133079
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2736062036
Short name T494
Test name
Test status
Simulation time 577117322 ps
CPU time 35.13 seconds
Started Aug 17 05:57:48 PM PDT 24
Finished Aug 17 05:58:23 PM PDT 24
Peak memory 256196 kb
Host smart-e7bd0158-7b3f-46ba-8264-12aa8a4fdc4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27360
62036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2736062036
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2164708660
Short name T673
Test name
Test status
Simulation time 4999708683 ps
CPU time 71 seconds
Started Aug 17 05:57:47 PM PDT 24
Finished Aug 17 05:58:58 PM PDT 24
Peak memory 248676 kb
Host smart-a2ab8471-258c-4baa-bf73-52b03c03d2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21647
08660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2164708660
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.217899124
Short name T655
Test name
Test status
Simulation time 178779059333 ps
CPU time 888.65 seconds
Started Aug 17 05:58:06 PM PDT 24
Finished Aug 17 06:12:54 PM PDT 24
Peak memory 273088 kb
Host smart-44de4218-0855-478c-9067-fbda5f495a9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217899124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.217899124
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.334931843
Short name T207
Test name
Test status
Simulation time 116136707478 ps
CPU time 1801.72 seconds
Started Aug 17 05:57:56 PM PDT 24
Finished Aug 17 06:27:58 PM PDT 24
Peak memory 273424 kb
Host smart-a4217e87-462d-4028-83ac-b52b62e5661e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334931843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.334931843
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.777296263
Short name T212
Test name
Test status
Simulation time 6831118679 ps
CPU time 292.93 seconds
Started Aug 17 05:57:55 PM PDT 24
Finished Aug 17 06:02:48 PM PDT 24
Peak memory 248848 kb
Host smart-42f24996-f20f-4b8d-befe-61f2f072158c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777296263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.777296263
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.4161445614
Short name T374
Test name
Test status
Simulation time 1589550949 ps
CPU time 27.64 seconds
Started Aug 17 05:57:46 PM PDT 24
Finished Aug 17 05:58:14 PM PDT 24
Peak memory 248780 kb
Host smart-e28015ed-b0ad-4e44-bae2-0a856f4161a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41614
45614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.4161445614
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3339495775
Short name T24
Test name
Test status
Simulation time 2622161642 ps
CPU time 26.5 seconds
Started Aug 17 05:57:46 PM PDT 24
Finished Aug 17 05:58:13 PM PDT 24
Peak memory 256096 kb
Host smart-0fffec0a-7f7c-4b7f-848e-8f27e6f0a716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33394
95775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3339495775
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1596971729
Short name T80
Test name
Test status
Simulation time 536848496 ps
CPU time 37.88 seconds
Started Aug 17 05:57:47 PM PDT 24
Finished Aug 17 05:58:25 PM PDT 24
Peak memory 256208 kb
Host smart-0e705a70-e15b-49ef-ad08-122e4a696e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15969
71729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1596971729
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2839957522
Short name T11
Test name
Test status
Simulation time 359195283 ps
CPU time 37.95 seconds
Started Aug 17 05:57:49 PM PDT 24
Finished Aug 17 05:58:27 PM PDT 24
Peak memory 256868 kb
Host smart-4511a1b4-9e12-49f6-83ee-16314b82d66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28399
57522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2839957522
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.728326389
Short name T448
Test name
Test status
Simulation time 135088204522 ps
CPU time 1923.49 seconds
Started Aug 17 05:57:55 PM PDT 24
Finished Aug 17 06:29:59 PM PDT 24
Peak memory 273392 kb
Host smart-fb512d96-5358-4cdc-8445-f3dcb90bcc1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728326389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.728326389
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3096329148
Short name T455
Test name
Test status
Simulation time 7599447600 ps
CPU time 176.31 seconds
Started Aug 17 05:57:56 PM PDT 24
Finished Aug 17 06:00:53 PM PDT 24
Peak memory 256352 kb
Host smart-2ce2cfce-7f19-4196-8204-00e59c3552cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30963
29148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3096329148
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3770375229
Short name T562
Test name
Test status
Simulation time 1234109279 ps
CPU time 28.66 seconds
Started Aug 17 05:57:55 PM PDT 24
Finished Aug 17 05:58:24 PM PDT 24
Peak memory 248852 kb
Host smart-279b3f85-0ced-46ee-8722-2aee385e2091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37703
75229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3770375229
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1538382232
Short name T14
Test name
Test status
Simulation time 36880809037 ps
CPU time 2012.34 seconds
Started Aug 17 05:57:56 PM PDT 24
Finished Aug 17 06:31:28 PM PDT 24
Peak memory 273308 kb
Host smart-1d3a3044-f4ac-4a1e-8931-d47ae867b8db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538382232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1538382232
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3438321477
Short name T635
Test name
Test status
Simulation time 52201619210 ps
CPU time 3217.27 seconds
Started Aug 17 05:57:57 PM PDT 24
Finished Aug 17 06:51:34 PM PDT 24
Peak memory 289780 kb
Host smart-d55e304d-faef-4d22-af5b-6f2dde6b155d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438321477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3438321477
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3887557630
Short name T284
Test name
Test status
Simulation time 8006965059 ps
CPU time 162.47 seconds
Started Aug 17 05:57:54 PM PDT 24
Finished Aug 17 06:00:36 PM PDT 24
Peak memory 248872 kb
Host smart-7f5bdea2-fc6f-43bd-925e-4cac3ac38a91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887557630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3887557630
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3829323315
Short name T526
Test name
Test status
Simulation time 1000398289 ps
CPU time 63.38 seconds
Started Aug 17 05:57:51 PM PDT 24
Finished Aug 17 05:58:55 PM PDT 24
Peak memory 256284 kb
Host smart-ea06419a-e630-42ea-9115-f5b1166809f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38293
23315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3829323315
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.4264732314
Short name T399
Test name
Test status
Simulation time 4665969010 ps
CPU time 69.01 seconds
Started Aug 17 05:57:57 PM PDT 24
Finished Aug 17 05:59:06 PM PDT 24
Peak memory 257084 kb
Host smart-d5fbcb5b-b803-4c70-b37d-d23543ac3dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42647
32314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.4264732314
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.90799086
Short name T597
Test name
Test status
Simulation time 1046573310 ps
CPU time 59.72 seconds
Started Aug 17 05:58:06 PM PDT 24
Finished Aug 17 05:59:06 PM PDT 24
Peak memory 256352 kb
Host smart-0b10719b-e304-407f-b268-cbd3a61aa99d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90799
086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.90799086
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2272974094
Short name T677
Test name
Test status
Simulation time 1495567662 ps
CPU time 38.09 seconds
Started Aug 17 05:57:55 PM PDT 24
Finished Aug 17 05:58:34 PM PDT 24
Peak memory 256948 kb
Host smart-b6cd87af-cfb5-4548-ab2f-25147ee055af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22729
74094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2272974094
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3375964363
Short name T683
Test name
Test status
Simulation time 5129466959 ps
CPU time 283.61 seconds
Started Aug 17 05:57:57 PM PDT 24
Finished Aug 17 06:02:41 PM PDT 24
Peak memory 257032 kb
Host smart-2e498a58-d6af-4d05-ad06-a15ddac2a69c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375964363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3375964363
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2664367796
Short name T216
Test name
Test status
Simulation time 5267755027 ps
CPU time 233.36 seconds
Started Aug 17 05:57:53 PM PDT 24
Finished Aug 17 06:01:47 PM PDT 24
Peak memory 266424 kb
Host smart-37e09940-aa47-4f1f-9e8a-70e9275b7cac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664367796 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2664367796
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1439471722
Short name T184
Test name
Test status
Simulation time 140536611 ps
CPU time 3.47 seconds
Started Aug 17 05:56:22 PM PDT 24
Finished Aug 17 05:56:26 PM PDT 24
Peak memory 249028 kb
Host smart-7bcf02c4-cf56-434e-8ec7-d12dac2d5f1e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1439471722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1439471722
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1975598171
Short name T574
Test name
Test status
Simulation time 39123520785 ps
CPU time 2104.86 seconds
Started Aug 17 05:56:19 PM PDT 24
Finished Aug 17 06:31:24 PM PDT 24
Peak memory 273144 kb
Host smart-7d9c6781-17ba-44ec-95d9-6f281f417af2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975598171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1975598171
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2854624652
Short name T17
Test name
Test status
Simulation time 22511514788 ps
CPU time 67.45 seconds
Started Aug 17 05:56:19 PM PDT 24
Finished Aug 17 05:57:27 PM PDT 24
Peak memory 248832 kb
Host smart-11fc8628-9c9c-45c4-a874-d8292ee13d95
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2854624652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2854624652
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2530305640
Short name T257
Test name
Test status
Simulation time 2362804299 ps
CPU time 86.18 seconds
Started Aug 17 05:56:19 PM PDT 24
Finished Aug 17 05:57:45 PM PDT 24
Peak memory 256624 kb
Host smart-ae62e905-e227-4bc3-b2a5-e034a13ed784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25303
05640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2530305640
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2682360215
Short name T519
Test name
Test status
Simulation time 900996763 ps
CPU time 28.43 seconds
Started Aug 17 05:56:11 PM PDT 24
Finished Aug 17 05:56:40 PM PDT 24
Peak memory 248752 kb
Host smart-fc8b903f-2854-49b9-9200-1399dd530d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26823
60215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2682360215
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2437021099
Short name T656
Test name
Test status
Simulation time 126019628611 ps
CPU time 1682.61 seconds
Started Aug 17 05:56:19 PM PDT 24
Finished Aug 17 06:24:22 PM PDT 24
Peak memory 273092 kb
Host smart-082fecc2-2cf7-43a6-9035-fcbb8b8c5c99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437021099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2437021099
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.4226390868
Short name T478
Test name
Test status
Simulation time 190751468628 ps
CPU time 2169.35 seconds
Started Aug 17 05:56:20 PM PDT 24
Finished Aug 17 06:32:29 PM PDT 24
Peak memory 287100 kb
Host smart-37cc6ad5-8748-4a33-8ea6-5c584725a960
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226390868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.4226390868
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3522260539
Short name T592
Test name
Test status
Simulation time 28004535152 ps
CPU time 654.25 seconds
Started Aug 17 05:56:22 PM PDT 24
Finished Aug 17 06:07:17 PM PDT 24
Peak memory 248864 kb
Host smart-b761eb7a-844d-4767-a49b-ff588973fa5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522260539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3522260539
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2886729101
Short name T383
Test name
Test status
Simulation time 3247147223 ps
CPU time 54.07 seconds
Started Aug 17 05:56:13 PM PDT 24
Finished Aug 17 05:57:07 PM PDT 24
Peak memory 256492 kb
Host smart-3efae2f8-f900-4972-b955-30763ccb9efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28867
29101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2886729101
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2305045300
Short name T108
Test name
Test status
Simulation time 259635560 ps
CPU time 19.52 seconds
Started Aug 17 05:56:12 PM PDT 24
Finished Aug 17 05:56:31 PM PDT 24
Peak memory 248620 kb
Host smart-a28f2515-e5a5-43e9-8665-e9f2406e777a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23050
45300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2305045300
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3988004083
Short name T39
Test name
Test status
Simulation time 316241320 ps
CPU time 11.94 seconds
Started Aug 17 05:56:19 PM PDT 24
Finished Aug 17 05:56:31 PM PDT 24
Peak memory 266780 kb
Host smart-5dd94419-7ccc-4c41-8792-3f2d36d97b53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3988004083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3988004083
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2129141965
Short name T397
Test name
Test status
Simulation time 1337049443 ps
CPU time 22.07 seconds
Started Aug 17 05:56:18 PM PDT 24
Finished Aug 17 05:56:40 PM PDT 24
Peak memory 256280 kb
Host smart-21e058a3-38e3-45cc-b1eb-e8cd8dae322e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21291
41965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2129141965
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.671531287
Short name T424
Test name
Test status
Simulation time 221745098 ps
CPU time 15.62 seconds
Started Aug 17 05:56:12 PM PDT 24
Finished Aug 17 05:56:28 PM PDT 24
Peak memory 255028 kb
Host smart-778016b5-f5b5-4ef4-88b1-2893996f9bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67153
1287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.671531287
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1689324241
Short name T550
Test name
Test status
Simulation time 1989991560 ps
CPU time 122.08 seconds
Started Aug 17 05:56:20 PM PDT 24
Finished Aug 17 05:58:22 PM PDT 24
Peak memory 256968 kb
Host smart-7762f94d-15bb-44bb-a7ac-0c6c46195d27
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689324241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1689324241
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.486372306
Short name T593
Test name
Test status
Simulation time 45653256467 ps
CPU time 2645.17 seconds
Started Aug 17 05:58:06 PM PDT 24
Finished Aug 17 06:42:11 PM PDT 24
Peak memory 285504 kb
Host smart-de4f602a-658f-4cce-92fc-6cc734a8eb33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486372306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.486372306
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1252417468
Short name T629
Test name
Test status
Simulation time 3731782626 ps
CPU time 259.76 seconds
Started Aug 17 05:57:55 PM PDT 24
Finished Aug 17 06:02:15 PM PDT 24
Peak memory 256900 kb
Host smart-fb67eec5-8d74-4b43-bb3d-c7a9a361c7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12524
17468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1252417468
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3024488494
Short name T489
Test name
Test status
Simulation time 1993304471 ps
CPU time 52.23 seconds
Started Aug 17 05:57:54 PM PDT 24
Finished Aug 17 05:58:46 PM PDT 24
Peak memory 248200 kb
Host smart-5fd06ac6-1cc3-403f-954c-241f0c93efa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30244
88494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3024488494
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.72957520
Short name T274
Test name
Test status
Simulation time 113162262165 ps
CPU time 1295.01 seconds
Started Aug 17 05:57:56 PM PDT 24
Finished Aug 17 06:19:31 PM PDT 24
Peak memory 272952 kb
Host smart-6477a25f-b54b-4853-b5cb-eb89ab074d17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72957520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.72957520
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3341730552
Short name T599
Test name
Test status
Simulation time 188784651162 ps
CPU time 1248.85 seconds
Started Aug 17 05:57:57 PM PDT 24
Finished Aug 17 06:18:46 PM PDT 24
Peak memory 270392 kb
Host smart-88491f08-3e76-4998-bb1b-f61a2970ff03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341730552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3341730552
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3711418125
Short name T290
Test name
Test status
Simulation time 28995711506 ps
CPU time 279.09 seconds
Started Aug 17 05:57:54 PM PDT 24
Finished Aug 17 06:02:33 PM PDT 24
Peak memory 248608 kb
Host smart-9b806398-7ccf-48b6-ae08-1c78502dbf9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711418125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3711418125
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.4247017390
Short name T441
Test name
Test status
Simulation time 942670212 ps
CPU time 41.53 seconds
Started Aug 17 05:57:57 PM PDT 24
Finished Aug 17 05:58:39 PM PDT 24
Peak memory 256924 kb
Host smart-f30107ca-acc8-450c-98d5-ce805a34a610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42470
17390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4247017390
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3301198619
Short name T85
Test name
Test status
Simulation time 2848732855 ps
CPU time 23.4 seconds
Started Aug 17 05:57:58 PM PDT 24
Finished Aug 17 05:58:22 PM PDT 24
Peak memory 256336 kb
Host smart-f91453c7-e126-4ad3-8848-8afdd6f02eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33011
98619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3301198619
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.997280513
Short name T377
Test name
Test status
Simulation time 52533623 ps
CPU time 7.01 seconds
Started Aug 17 05:57:56 PM PDT 24
Finished Aug 17 05:58:03 PM PDT 24
Peak memory 252596 kb
Host smart-5d714bc1-6454-4265-bd08-3d6d44f6a988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99728
0513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.997280513
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3597326983
Short name T261
Test name
Test status
Simulation time 2568712066 ps
CPU time 84.25 seconds
Started Aug 17 05:57:54 PM PDT 24
Finished Aug 17 05:59:19 PM PDT 24
Peak memory 256976 kb
Host smart-44097cfe-8576-479d-b66b-18179a75c3de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597326983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3597326983
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2830955040
Short name T697
Test name
Test status
Simulation time 6349807978 ps
CPU time 282.25 seconds
Started Aug 17 05:57:57 PM PDT 24
Finished Aug 17 06:02:40 PM PDT 24
Peak memory 266756 kb
Host smart-590f70c9-5fe9-4d12-afbd-9c766544a6fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830955040 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2830955040
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.511778610
Short name T521
Test name
Test status
Simulation time 186344690064 ps
CPU time 1454.1 seconds
Started Aug 17 05:58:06 PM PDT 24
Finished Aug 17 06:22:20 PM PDT 24
Peak memory 273460 kb
Host smart-2d06fdc1-f92b-4338-9665-a8088cf6a27d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511778610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.511778610
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.868052271
Short name T204
Test name
Test status
Simulation time 6312805818 ps
CPU time 51.95 seconds
Started Aug 17 05:58:03 PM PDT 24
Finished Aug 17 05:58:55 PM PDT 24
Peak memory 256392 kb
Host smart-f4f762eb-2699-4d84-9d1f-0a0f4a022a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86805
2271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.868052271
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3623879103
Short name T86
Test name
Test status
Simulation time 155119015 ps
CPU time 19.65 seconds
Started Aug 17 05:58:00 PM PDT 24
Finished Aug 17 05:58:20 PM PDT 24
Peak memory 248848 kb
Host smart-8144f425-e431-40c3-8a35-bc7722324e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36238
79103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3623879103
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1551659909
Short name T688
Test name
Test status
Simulation time 53562022226 ps
CPU time 1826.43 seconds
Started Aug 17 05:57:59 PM PDT 24
Finished Aug 17 06:28:25 PM PDT 24
Peak memory 272784 kb
Host smart-f4206c80-5d68-4cef-8794-a176442db52b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551659909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1551659909
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2011707038
Short name T384
Test name
Test status
Simulation time 169111537503 ps
CPU time 2289.01 seconds
Started Aug 17 05:58:03 PM PDT 24
Finished Aug 17 06:36:12 PM PDT 24
Peak memory 283592 kb
Host smart-c1934ecb-dee1-42bf-a7bf-fc7b56bd7e2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011707038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2011707038
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.155099557
Short name T277
Test name
Test status
Simulation time 13204101962 ps
CPU time 507.38 seconds
Started Aug 17 05:57:58 PM PDT 24
Finished Aug 17 06:06:25 PM PDT 24
Peak memory 248700 kb
Host smart-d8e44c13-3681-4cf8-82f2-80964713f784
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155099557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.155099557
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3860685874
Short name T668
Test name
Test status
Simulation time 1507975828 ps
CPU time 17.52 seconds
Started Aug 17 05:57:56 PM PDT 24
Finished Aug 17 05:58:13 PM PDT 24
Peak memory 256452 kb
Host smart-e2168228-89aa-4197-ba3a-7b66f8f01be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38606
85874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3860685874
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1627317960
Short name T604
Test name
Test status
Simulation time 655481534 ps
CPU time 41.47 seconds
Started Aug 17 05:58:06 PM PDT 24
Finished Aug 17 05:58:47 PM PDT 24
Peak memory 248860 kb
Host smart-0cf792bd-5c29-4140-b359-3e06e5cefc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16273
17960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1627317960
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.4187415283
Short name T238
Test name
Test status
Simulation time 4719628996 ps
CPU time 58.27 seconds
Started Aug 17 05:57:59 PM PDT 24
Finished Aug 17 05:58:58 PM PDT 24
Peak memory 256144 kb
Host smart-926f9b49-f7ad-46f4-b749-04b2f2b3b405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41874
15283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.4187415283
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3553131615
Short name T203
Test name
Test status
Simulation time 1226924985 ps
CPU time 63.86 seconds
Started Aug 17 05:57:56 PM PDT 24
Finished Aug 17 05:59:00 PM PDT 24
Peak memory 256956 kb
Host smart-ee51fdf3-8d41-4e3a-8234-3021ee8d998f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35531
31615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3553131615
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3023321233
Short name T366
Test name
Test status
Simulation time 54920977597 ps
CPU time 3171.93 seconds
Started Aug 17 05:58:02 PM PDT 24
Finished Aug 17 06:50:55 PM PDT 24
Peak memory 289740 kb
Host smart-c4575982-105d-421a-8ebd-064d7129758f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023321233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3023321233
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.3778039258
Short name T556
Test name
Test status
Simulation time 19347921077 ps
CPU time 350.41 seconds
Started Aug 17 05:57:59 PM PDT 24
Finished Aug 17 06:03:50 PM PDT 24
Peak memory 268772 kb
Host smart-a86e12c7-9533-4ad6-ad70-6a736ecd123f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778039258 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.3778039258
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.4250417217
Short name T628
Test name
Test status
Simulation time 124468468261 ps
CPU time 2232.24 seconds
Started Aug 17 05:58:09 PM PDT 24
Finished Aug 17 06:35:22 PM PDT 24
Peak memory 289256 kb
Host smart-aa67bee0-b413-46c1-b33c-090b95ae6e04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250417217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.4250417217
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3263523417
Short name T398
Test name
Test status
Simulation time 2289870752 ps
CPU time 70.92 seconds
Started Aug 17 05:58:00 PM PDT 24
Finished Aug 17 05:59:11 PM PDT 24
Peak memory 257020 kb
Host smart-8cdd0987-af37-4c7e-8625-8f4dcb102e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32635
23417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3263523417
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.983833543
Short name T81
Test name
Test status
Simulation time 6061871311 ps
CPU time 18.02 seconds
Started Aug 17 05:58:04 PM PDT 24
Finished Aug 17 05:58:22 PM PDT 24
Peak memory 248360 kb
Host smart-83250349-4a96-49bc-a163-e748e91fd050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98383
3543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.983833543
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.4144386655
Short name T428
Test name
Test status
Simulation time 17814366056 ps
CPU time 773.65 seconds
Started Aug 17 05:58:11 PM PDT 24
Finished Aug 17 06:11:05 PM PDT 24
Peak memory 273428 kb
Host smart-f75bc2d1-c0ab-4d64-b509-d0307d157002
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144386655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4144386655
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2377301380
Short name T368
Test name
Test status
Simulation time 10773912020 ps
CPU time 1373.06 seconds
Started Aug 17 05:58:08 PM PDT 24
Finished Aug 17 06:21:02 PM PDT 24
Peak memory 281496 kb
Host smart-77357b9c-f9db-4121-aabd-a61217081d9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377301380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2377301380
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3328662346
Short name T548
Test name
Test status
Simulation time 54535061800 ps
CPU time 483.65 seconds
Started Aug 17 05:58:09 PM PDT 24
Finished Aug 17 06:06:13 PM PDT 24
Peak memory 248864 kb
Host smart-1cc22b77-ffeb-4290-982f-9333977a40cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328662346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3328662346
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1039946765
Short name T219
Test name
Test status
Simulation time 1488197552 ps
CPU time 22.43 seconds
Started Aug 17 05:58:04 PM PDT 24
Finished Aug 17 05:58:26 PM PDT 24
Peak memory 256308 kb
Host smart-1a5a57d6-6d09-4be7-a937-3a9f896145ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10399
46765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1039946765
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1491573363
Short name T350
Test name
Test status
Simulation time 1869300710 ps
CPU time 31.28 seconds
Started Aug 17 05:58:06 PM PDT 24
Finished Aug 17 05:58:38 PM PDT 24
Peak memory 257008 kb
Host smart-60a7d28b-b881-4e06-89f4-9f3aa48e2d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14915
73363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1491573363
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2991547904
Short name T230
Test name
Test status
Simulation time 133902355 ps
CPU time 11.61 seconds
Started Aug 17 05:58:12 PM PDT 24
Finished Aug 17 05:58:24 PM PDT 24
Peak memory 248328 kb
Host smart-aed6be51-1242-42df-9d85-0b990eed0578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29915
47904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2991547904
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1833547237
Short name T669
Test name
Test status
Simulation time 677250114 ps
CPU time 43.79 seconds
Started Aug 17 05:57:59 PM PDT 24
Finished Aug 17 05:58:43 PM PDT 24
Peak memory 256084 kb
Host smart-820530c6-ea9a-4207-b2f5-c2325f33c99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18335
47237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1833547237
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.376702590
Short name T57
Test name
Test status
Simulation time 21756448617 ps
CPU time 492.55 seconds
Started Aug 17 05:58:10 PM PDT 24
Finished Aug 17 06:06:23 PM PDT 24
Peak memory 257092 kb
Host smart-4a599bd7-20a6-4221-979f-dd390c65975a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376702590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.376702590
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2616651907
Short name T113
Test name
Test status
Simulation time 264545029174 ps
CPU time 2943.91 seconds
Started Aug 17 05:58:10 PM PDT 24
Finished Aug 17 06:47:15 PM PDT 24
Peak memory 289452 kb
Host smart-4dd7ad29-6a1e-4e97-aabb-bae30508bbe8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616651907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2616651907
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2670555820
Short name T684
Test name
Test status
Simulation time 3246728620 ps
CPU time 142.35 seconds
Started Aug 17 05:58:11 PM PDT 24
Finished Aug 17 06:00:33 PM PDT 24
Peak memory 256352 kb
Host smart-f14f375c-1ae8-482e-819d-fbaf789c6a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26705
55820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2670555820
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3813764606
Short name T699
Test name
Test status
Simulation time 177425016 ps
CPU time 7.65 seconds
Started Aug 17 05:58:09 PM PDT 24
Finished Aug 17 05:58:17 PM PDT 24
Peak memory 251176 kb
Host smart-861f764d-d603-4bb1-8393-0caf861fa767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38137
64606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3813764606
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1806700754
Short name T308
Test name
Test status
Simulation time 21956624721 ps
CPU time 1195.68 seconds
Started Aug 17 05:58:09 PM PDT 24
Finished Aug 17 06:18:05 PM PDT 24
Peak memory 285184 kb
Host smart-f5addd41-c39e-43cb-97e6-df66afdcf679
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806700754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1806700754
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.93986567
Short name T607
Test name
Test status
Simulation time 19425826975 ps
CPU time 1114.98 seconds
Started Aug 17 05:58:13 PM PDT 24
Finished Aug 17 06:16:48 PM PDT 24
Peak memory 272708 kb
Host smart-54616a55-30e9-472d-ad5c-3208480c22f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93986567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.93986567
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1246494939
Short name T708
Test name
Test status
Simulation time 15181343482 ps
CPU time 611.93 seconds
Started Aug 17 05:58:09 PM PDT 24
Finished Aug 17 06:08:21 PM PDT 24
Peak memory 248872 kb
Host smart-4402b75b-6e04-4898-bc6f-1288e5e635f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246494939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1246494939
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.34030445
Short name T402
Test name
Test status
Simulation time 86685669 ps
CPU time 7.92 seconds
Started Aug 17 05:58:12 PM PDT 24
Finished Aug 17 05:58:20 PM PDT 24
Peak memory 248832 kb
Host smart-a6df35a9-8ac5-4d80-947f-65b4efc5229b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34030
445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.34030445
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1670501483
Short name T353
Test name
Test status
Simulation time 172160685 ps
CPU time 14.78 seconds
Started Aug 17 05:58:10 PM PDT 24
Finished Aug 17 05:58:25 PM PDT 24
Peak memory 248352 kb
Host smart-157579b0-b163-4347-bff6-5c509180ecc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16705
01483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1670501483
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1904745482
Short name T501
Test name
Test status
Simulation time 373035882 ps
CPU time 24.53 seconds
Started Aug 17 05:58:11 PM PDT 24
Finished Aug 17 05:58:36 PM PDT 24
Peak memory 248772 kb
Host smart-0f05aa35-ceff-4556-9fa0-a5599ee6b6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19047
45482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1904745482
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1187015945
Short name T663
Test name
Test status
Simulation time 675753646 ps
CPU time 43.46 seconds
Started Aug 17 05:58:10 PM PDT 24
Finished Aug 17 05:58:53 PM PDT 24
Peak memory 256940 kb
Host smart-56e7aecc-f78c-4400-916a-6e33f941b430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11870
15945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1187015945
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.4227228635
Short name T94
Test name
Test status
Simulation time 18031941059 ps
CPU time 1771.93 seconds
Started Aug 17 05:58:08 PM PDT 24
Finished Aug 17 06:27:40 PM PDT 24
Peak memory 305408 kb
Host smart-5d6d56da-6271-4d84-b753-d0cdd5cf6525
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227228635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.4227228635
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2185011
Short name T637
Test name
Test status
Simulation time 469557909955 ps
CPU time 2943.86 seconds
Started Aug 17 05:58:16 PM PDT 24
Finished Aug 17 06:47:21 PM PDT 24
Peak memory 289840 kb
Host smart-6f9a1c72-4cee-4d7f-8360-5f1d3512086d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2185011
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1117068008
Short name T221
Test name
Test status
Simulation time 23454147819 ps
CPU time 84.76 seconds
Started Aug 17 05:58:10 PM PDT 24
Finished Aug 17 05:59:35 PM PDT 24
Peak memory 257020 kb
Host smart-de39f0f1-237d-41b4-a59a-3e1d80225487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11170
68008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1117068008
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2272058078
Short name T472
Test name
Test status
Simulation time 789212373 ps
CPU time 48.61 seconds
Started Aug 17 05:58:12 PM PDT 24
Finished Aug 17 05:59:00 PM PDT 24
Peak memory 256592 kb
Host smart-a3157c22-40dd-4132-9e94-d9aa52de8b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22720
58078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2272058078
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.877287537
Short name T314
Test name
Test status
Simulation time 27925512302 ps
CPU time 1588.29 seconds
Started Aug 17 05:58:18 PM PDT 24
Finished Aug 17 06:24:47 PM PDT 24
Peak memory 271380 kb
Host smart-57b2a232-542a-49b7-8bf5-34a9698549da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877287537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.877287537
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2582992337
Short name T438
Test name
Test status
Simulation time 233458736886 ps
CPU time 2420.74 seconds
Started Aug 17 05:58:18 PM PDT 24
Finished Aug 17 06:38:39 PM PDT 24
Peak memory 288988 kb
Host smart-92c1bb52-0976-483c-8c30-3609fe7b3e3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582992337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2582992337
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1460220144
Short name T602
Test name
Test status
Simulation time 5004374132 ps
CPU time 214.41 seconds
Started Aug 17 05:58:19 PM PDT 24
Finished Aug 17 06:01:53 PM PDT 24
Peak memory 247744 kb
Host smart-c93d05a4-5952-4906-a24b-fcfae301ba16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460220144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1460220144
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.21744624
Short name T340
Test name
Test status
Simulation time 1347485602 ps
CPU time 22.64 seconds
Started Aug 17 05:58:10 PM PDT 24
Finished Aug 17 05:58:33 PM PDT 24
Peak memory 248792 kb
Host smart-75f98078-94a4-4bbb-a061-97d5e0399887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21744
624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.21744624
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1092478253
Short name T435
Test name
Test status
Simulation time 1817391873 ps
CPU time 35.72 seconds
Started Aug 17 05:58:10 PM PDT 24
Finished Aug 17 05:58:46 PM PDT 24
Peak memory 256364 kb
Host smart-b4a8b530-ff97-49a7-9545-90540b1c1bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10924
78253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1092478253
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3794814718
Short name T431
Test name
Test status
Simulation time 754030255 ps
CPU time 36.53 seconds
Started Aug 17 05:58:07 PM PDT 24
Finished Aug 17 05:58:44 PM PDT 24
Peak memory 248828 kb
Host smart-1d831bc0-2c2a-4630-8f7a-53566fec9108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37948
14718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3794814718
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1768147931
Short name T364
Test name
Test status
Simulation time 5394176881 ps
CPU time 52.45 seconds
Started Aug 17 05:58:10 PM PDT 24
Finished Aug 17 05:59:03 PM PDT 24
Peak memory 257032 kb
Host smart-2799661f-9b17-4228-84fb-8f1bcaa4cfd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17681
47931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1768147931
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2343938413
Short name T709
Test name
Test status
Simulation time 78873474774 ps
CPU time 1193.24 seconds
Started Aug 17 05:58:16 PM PDT 24
Finished Aug 17 06:18:10 PM PDT 24
Peak memory 289756 kb
Host smart-18b24434-9502-4241-9bdf-01523090e8fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343938413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2343938413
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3719479900
Short name T342
Test name
Test status
Simulation time 463391189 ps
CPU time 10.59 seconds
Started Aug 17 05:58:15 PM PDT 24
Finished Aug 17 05:58:26 PM PDT 24
Peak memory 254976 kb
Host smart-1ade064b-e072-488a-ae65-70fd514fdd67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37194
79900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3719479900
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3799679732
Short name T403
Test name
Test status
Simulation time 175610940 ps
CPU time 14.61 seconds
Started Aug 17 05:58:18 PM PDT 24
Finished Aug 17 05:58:33 PM PDT 24
Peak memory 248216 kb
Host smart-c9252f5e-d49d-466c-8860-8d57f02352f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37996
79732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3799679732
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.416735802
Short name T32
Test name
Test status
Simulation time 57501096155 ps
CPU time 3417.58 seconds
Started Aug 17 05:58:17 PM PDT 24
Finished Aug 17 06:55:15 PM PDT 24
Peak memory 289040 kb
Host smart-eb5b2e8d-54c6-4350-bbb0-8da26fcd4d10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416735802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.416735802
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2169642482
Short name T6
Test name
Test status
Simulation time 10987860704 ps
CPU time 383.82 seconds
Started Aug 17 05:58:23 PM PDT 24
Finished Aug 17 06:04:47 PM PDT 24
Peak memory 247992 kb
Host smart-c7a08b2e-3a36-4149-a280-20f957fdce97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169642482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2169642482
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.291330250
Short name T495
Test name
Test status
Simulation time 160284471 ps
CPU time 19.53 seconds
Started Aug 17 05:58:16 PM PDT 24
Finished Aug 17 05:58:36 PM PDT 24
Peak memory 248808 kb
Host smart-0581f503-0db2-4e93-9f80-c71ca0165706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29133
0250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.291330250
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3546300398
Short name T23
Test name
Test status
Simulation time 849799196 ps
CPU time 61.5 seconds
Started Aug 17 05:58:16 PM PDT 24
Finished Aug 17 05:59:17 PM PDT 24
Peak memory 248728 kb
Host smart-a41e8464-a933-4928-9944-4ec4d1368ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35463
00398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3546300398
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3105826682
Short name T412
Test name
Test status
Simulation time 511831379 ps
CPU time 5.48 seconds
Started Aug 17 05:58:17 PM PDT 24
Finished Aug 17 05:58:22 PM PDT 24
Peak memory 239772 kb
Host smart-403723a9-bf4b-4781-94c9-f5ced909534f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31058
26682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3105826682
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3585178955
Short name T457
Test name
Test status
Simulation time 57177974 ps
CPU time 6.72 seconds
Started Aug 17 05:58:17 PM PDT 24
Finished Aug 17 05:58:24 PM PDT 24
Peak memory 248820 kb
Host smart-968a453a-2315-449e-8075-ce89edde929e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35851
78955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3585178955
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1599148001
Short name T54
Test name
Test status
Simulation time 44994885559 ps
CPU time 1266.82 seconds
Started Aug 17 05:58:17 PM PDT 24
Finished Aug 17 06:19:24 PM PDT 24
Peak memory 289716 kb
Host smart-05a1dc1a-7dc6-47a2-b1d9-a760eefd12ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599148001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1599148001
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2978415417
Short name T641
Test name
Test status
Simulation time 33868563879 ps
CPU time 2131.55 seconds
Started Aug 17 05:58:25 PM PDT 24
Finished Aug 17 06:33:57 PM PDT 24
Peak memory 289736 kb
Host smart-41ff61cb-ec8b-4b65-aae6-61d5b0b1c20c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978415417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2978415417
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2131865129
Short name T577
Test name
Test status
Simulation time 5697060550 ps
CPU time 269.45 seconds
Started Aug 17 05:58:23 PM PDT 24
Finished Aug 17 06:02:53 PM PDT 24
Peak memory 256628 kb
Host smart-344c91e8-3660-4424-96ee-947159b47616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21318
65129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2131865129
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.246992258
Short name T653
Test name
Test status
Simulation time 659462436 ps
CPU time 29.14 seconds
Started Aug 17 05:58:25 PM PDT 24
Finished Aug 17 05:58:54 PM PDT 24
Peak memory 256960 kb
Host smart-968e70ae-538d-44a5-8955-2d26d587213f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24699
2258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.246992258
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.874853310
Short name T309
Test name
Test status
Simulation time 52134083070 ps
CPU time 2407.43 seconds
Started Aug 17 05:58:24 PM PDT 24
Finished Aug 17 06:38:31 PM PDT 24
Peak memory 289816 kb
Host smart-789e28a9-d4e7-4546-b33b-a6f402367076
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874853310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.874853310
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1698827889
Short name T513
Test name
Test status
Simulation time 146953224761 ps
CPU time 2309.68 seconds
Started Aug 17 05:58:26 PM PDT 24
Finished Aug 17 06:36:56 PM PDT 24
Peak memory 288924 kb
Host smart-dd18b0b8-4293-4e22-984c-519dcf99d95b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698827889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1698827889
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.4163227565
Short name T295
Test name
Test status
Simulation time 16178861776 ps
CPU time 191.57 seconds
Started Aug 17 05:58:24 PM PDT 24
Finished Aug 17 06:01:36 PM PDT 24
Peak memory 248764 kb
Host smart-e0810eb9-3a49-4370-8b2d-8161efc4b057
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163227565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.4163227565
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3321166870
Short name T608
Test name
Test status
Simulation time 28117031 ps
CPU time 6.34 seconds
Started Aug 17 05:58:24 PM PDT 24
Finished Aug 17 05:58:30 PM PDT 24
Peak memory 251672 kb
Host smart-1d742fb6-d993-44e2-b867-08b167119eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33211
66870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3321166870
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3534818790
Short name T450
Test name
Test status
Simulation time 250847466 ps
CPU time 10.09 seconds
Started Aug 17 05:58:25 PM PDT 24
Finished Aug 17 05:58:35 PM PDT 24
Peak memory 248304 kb
Host smart-150329ad-74f8-4c2d-af5e-4d8cac1ddfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35348
18790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3534818790
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.834473234
Short name T100
Test name
Test status
Simulation time 785696129 ps
CPU time 33.74 seconds
Started Aug 17 05:58:27 PM PDT 24
Finished Aug 17 05:59:01 PM PDT 24
Peak memory 248780 kb
Host smart-abc8b08a-e400-4335-b242-4346d56a0f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83447
3234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.834473234
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1921907426
Short name T360
Test name
Test status
Simulation time 60923766 ps
CPU time 10.92 seconds
Started Aug 17 05:58:14 PM PDT 24
Finished Aug 17 05:58:25 PM PDT 24
Peak memory 253576 kb
Host smart-50891d36-c61e-4d8a-9b90-57fcda909197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19219
07426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1921907426
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.808543678
Short name T496
Test name
Test status
Simulation time 32253779845 ps
CPU time 1659.75 seconds
Started Aug 17 05:58:23 PM PDT 24
Finished Aug 17 06:26:03 PM PDT 24
Peak memory 273268 kb
Host smart-271aa5ae-07f5-4520-9a92-fd4bea66b224
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808543678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.808543678
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.753513212
Short name T712
Test name
Test status
Simulation time 10154214946 ps
CPU time 160.84 seconds
Started Aug 17 05:58:40 PM PDT 24
Finished Aug 17 06:01:21 PM PDT 24
Peak memory 256996 kb
Host smart-9494c482-644c-4a5c-b7b9-53ce4f5e3617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75351
3212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.753513212
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.865330950
Short name T654
Test name
Test status
Simulation time 5182215083 ps
CPU time 37.08 seconds
Started Aug 17 05:58:25 PM PDT 24
Finished Aug 17 05:59:02 PM PDT 24
Peak memory 256956 kb
Host smart-6d9e3286-3f6b-4042-a90c-6600edf79d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86533
0950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.865330950
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.688358537
Short name T320
Test name
Test status
Simulation time 8575102609 ps
CPU time 792.45 seconds
Started Aug 17 05:58:33 PM PDT 24
Finished Aug 17 06:11:45 PM PDT 24
Peak memory 273356 kb
Host smart-5729754e-f48e-493c-8648-8f7a238c4bc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688358537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.688358537
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3347023709
Short name T566
Test name
Test status
Simulation time 34166573728 ps
CPU time 1583.45 seconds
Started Aug 17 05:58:45 PM PDT 24
Finished Aug 17 06:25:08 PM PDT 24
Peak memory 289572 kb
Host smart-7bbf2e7a-dd79-4367-8fe8-d9776068b560
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347023709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3347023709
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1892395809
Short name T301
Test name
Test status
Simulation time 45472646969 ps
CPU time 450.59 seconds
Started Aug 17 05:58:32 PM PDT 24
Finished Aug 17 06:06:03 PM PDT 24
Peak memory 255924 kb
Host smart-c82205ab-af24-4a04-b10f-259bf2670952
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892395809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1892395809
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2432004150
Short name T575
Test name
Test status
Simulation time 257262150 ps
CPU time 20.71 seconds
Started Aug 17 05:58:27 PM PDT 24
Finished Aug 17 05:58:48 PM PDT 24
Peak memory 256672 kb
Host smart-a176aff2-d677-470d-9a9e-1ecb1e79060b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24320
04150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2432004150
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.675763493
Short name T436
Test name
Test status
Simulation time 1078657853 ps
CPU time 63.75 seconds
Started Aug 17 05:58:24 PM PDT 24
Finished Aug 17 05:59:28 PM PDT 24
Peak memory 256984 kb
Host smart-29d1561e-f727-4975-80e1-be8414be538b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67576
3493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.675763493
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2067129256
Short name T250
Test name
Test status
Simulation time 568873331 ps
CPU time 9.9 seconds
Started Aug 17 05:58:40 PM PDT 24
Finished Aug 17 05:58:50 PM PDT 24
Peak memory 248088 kb
Host smart-f1f681db-df31-4f73-b6d4-67f1a0d645d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20671
29256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2067129256
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3785099041
Short name T650
Test name
Test status
Simulation time 405883979 ps
CPU time 13.82 seconds
Started Aug 17 05:58:25 PM PDT 24
Finished Aug 17 05:58:39 PM PDT 24
Peak memory 248844 kb
Host smart-f5db6165-3982-4df6-adb6-fe6974c835cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37850
99041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3785099041
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.1148541420
Short name T392
Test name
Test status
Simulation time 14722547366 ps
CPU time 451.46 seconds
Started Aug 17 05:58:32 PM PDT 24
Finished Aug 17 06:06:04 PM PDT 24
Peak memory 269604 kb
Host smart-4e365a6f-e7f3-4fa6-b3e6-3006fadf515c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148541420 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.1148541420
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3539656080
Short name T636
Test name
Test status
Simulation time 36924828324 ps
CPU time 2166.13 seconds
Started Aug 17 05:58:32 PM PDT 24
Finished Aug 17 06:34:38 PM PDT 24
Peak memory 273248 kb
Host smart-c67752d2-5e9d-4577-a93e-f243a0209871
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539656080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3539656080
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2231302959
Short name T520
Test name
Test status
Simulation time 4320476038 ps
CPU time 79.53 seconds
Started Aug 17 05:58:30 PM PDT 24
Finished Aug 17 05:59:49 PM PDT 24
Peak memory 257176 kb
Host smart-344309c1-c803-4631-8d5f-8a9ad6cd270c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22313
02959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2231302959
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3371987539
Short name T409
Test name
Test status
Simulation time 235813626 ps
CPU time 24.91 seconds
Started Aug 17 05:58:40 PM PDT 24
Finished Aug 17 05:59:05 PM PDT 24
Peak memory 256788 kb
Host smart-af7c54b2-04e7-47a3-a2b1-187b2c59394f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33719
87539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3371987539
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1251195313
Short name T674
Test name
Test status
Simulation time 187526895804 ps
CPU time 2855.4 seconds
Started Aug 17 05:58:35 PM PDT 24
Finished Aug 17 06:46:11 PM PDT 24
Peak memory 285744 kb
Host smart-1c56643c-3779-489d-9819-613e61e1d3bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251195313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1251195313
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1014717620
Short name T291
Test name
Test status
Simulation time 4241252975 ps
CPU time 167.65 seconds
Started Aug 17 05:58:44 PM PDT 24
Finished Aug 17 06:01:32 PM PDT 24
Peak memory 248636 kb
Host smart-decfe476-5c10-4053-8e49-f40e7621729d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014717620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1014717620
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2954922930
Short name T696
Test name
Test status
Simulation time 3277733558 ps
CPU time 32.85 seconds
Started Aug 17 05:58:40 PM PDT 24
Finished Aug 17 05:59:13 PM PDT 24
Peak memory 257040 kb
Host smart-2fac2748-91bd-43ec-b899-04ddc5eac6b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29549
22930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2954922930
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2178208421
Short name T456
Test name
Test status
Simulation time 1335072109 ps
CPU time 42.13 seconds
Started Aug 17 05:58:33 PM PDT 24
Finished Aug 17 05:59:15 PM PDT 24
Peak memory 256884 kb
Host smart-9cc3b069-8300-46ea-b300-69f5af0a8ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21782
08421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2178208421
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1283505169
Short name T681
Test name
Test status
Simulation time 52841003 ps
CPU time 4.83 seconds
Started Aug 17 05:58:40 PM PDT 24
Finished Aug 17 05:58:45 PM PDT 24
Peak memory 239832 kb
Host smart-d82fb16a-15ac-4ffd-8337-2d46f32a3d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12835
05169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1283505169
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3766096236
Short name T711
Test name
Test status
Simulation time 231384416 ps
CPU time 16.69 seconds
Started Aug 17 05:58:44 PM PDT 24
Finished Aug 17 05:59:01 PM PDT 24
Peak memory 256204 kb
Host smart-42c35777-1f1d-4e80-b461-a63b8198ccc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37660
96236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3766096236
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.359175808
Short name T477
Test name
Test status
Simulation time 189868475958 ps
CPU time 2568.65 seconds
Started Aug 17 05:58:32 PM PDT 24
Finished Aug 17 06:41:21 PM PDT 24
Peak memory 289848 kb
Host smart-9ed10231-8b09-4eb5-b7da-c6842ee70f36
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359175808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.359175808
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.211993991
Short name T266
Test name
Test status
Simulation time 47770730362 ps
CPU time 345.37 seconds
Started Aug 17 05:58:33 PM PDT 24
Finished Aug 17 06:04:18 PM PDT 24
Peak memory 273548 kb
Host smart-04ce7bd0-4785-448e-bd38-4635afea7c39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211993991 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.211993991
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3866979882
Short name T552
Test name
Test status
Simulation time 57858830648 ps
CPU time 1119.01 seconds
Started Aug 17 05:58:41 PM PDT 24
Finished Aug 17 06:17:20 PM PDT 24
Peak memory 289508 kb
Host smart-24fac9d4-2128-4f88-857d-4844fbc452a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866979882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3866979882
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3149325837
Short name T707
Test name
Test status
Simulation time 5797404689 ps
CPU time 58.43 seconds
Started Aug 17 05:58:40 PM PDT 24
Finished Aug 17 05:59:39 PM PDT 24
Peak memory 256408 kb
Host smart-59b2af21-a2f2-4666-8cee-41c70f89c086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31493
25837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3149325837
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3555059424
Short name T670
Test name
Test status
Simulation time 1812605996 ps
CPU time 32.35 seconds
Started Aug 17 05:58:42 PM PDT 24
Finished Aug 17 05:59:15 PM PDT 24
Peak memory 248072 kb
Host smart-07415c28-a1c1-431b-a913-0e2d673ecd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35550
59424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3555059424
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2689156632
Short name T312
Test name
Test status
Simulation time 42463718534 ps
CPU time 2430.94 seconds
Started Aug 17 05:58:38 PM PDT 24
Finished Aug 17 06:39:10 PM PDT 24
Peak memory 288480 kb
Host smart-ce8432dd-c4c7-440e-a097-1dcfb61c17f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689156632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2689156632
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3898280831
Short name T644
Test name
Test status
Simulation time 237156165355 ps
CPU time 1521.6 seconds
Started Aug 17 05:58:39 PM PDT 24
Finished Aug 17 06:24:01 PM PDT 24
Peak memory 273320 kb
Host smart-be79a782-92c3-4207-b255-f47a590ccc18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898280831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3898280831
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.401567608
Short name T293
Test name
Test status
Simulation time 12363097126 ps
CPU time 517.1 seconds
Started Aug 17 05:58:40 PM PDT 24
Finished Aug 17 06:07:17 PM PDT 24
Peak memory 247760 kb
Host smart-40e9db30-9eca-429f-a04f-a101072065da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401567608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.401567608
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.4113040132
Short name T387
Test name
Test status
Simulation time 319554462 ps
CPU time 30.15 seconds
Started Aug 17 05:58:38 PM PDT 24
Finished Aug 17 05:59:08 PM PDT 24
Peak memory 256168 kb
Host smart-b71a76ec-a6e4-4ce4-8cf3-cc2251baf7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41130
40132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.4113040132
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2061825060
Short name T71
Test name
Test status
Simulation time 961149356 ps
CPU time 57.51 seconds
Started Aug 17 05:58:41 PM PDT 24
Finished Aug 17 05:59:39 PM PDT 24
Peak memory 248336 kb
Host smart-36d1711b-8b96-462f-851d-992ef5c6f5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20618
25060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2061825060
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1612481215
Short name T617
Test name
Test status
Simulation time 746693088 ps
CPU time 59.19 seconds
Started Aug 17 05:58:41 PM PDT 24
Finished Aug 17 05:59:41 PM PDT 24
Peak memory 248776 kb
Host smart-3a37898f-f262-4131-82bb-ad10a4b02222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16124
81215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1612481215
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2670555693
Short name T639
Test name
Test status
Simulation time 839746582 ps
CPU time 47.6 seconds
Started Aug 17 05:58:40 PM PDT 24
Finished Aug 17 05:59:28 PM PDT 24
Peak memory 248832 kb
Host smart-d21ff85d-3f8a-435f-af8a-b4f002d23b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26705
55693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2670555693
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1398717290
Short name T231
Test name
Test status
Simulation time 17328661163 ps
CPU time 298.44 seconds
Started Aug 17 05:58:38 PM PDT 24
Finished Aug 17 06:03:37 PM PDT 24
Peak memory 257020 kb
Host smart-294683f8-5632-4bc8-af8b-3d642752bec1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398717290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1398717290
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.3793931027
Short name T619
Test name
Test status
Simulation time 7587254303 ps
CPU time 411.23 seconds
Started Aug 17 05:58:39 PM PDT 24
Finished Aug 17 06:05:31 PM PDT 24
Peak memory 270936 kb
Host smart-9c5a4f97-9424-40da-aff5-4e41da1b1033
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793931027 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.3793931027
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1089892298
Short name T48
Test name
Test status
Simulation time 47336158 ps
CPU time 2.67 seconds
Started Aug 17 05:56:21 PM PDT 24
Finished Aug 17 05:56:24 PM PDT 24
Peak memory 248936 kb
Host smart-dd701137-a123-4775-a023-c8ac7ba69401
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1089892298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1089892298
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.412659593
Short name T114
Test name
Test status
Simulation time 93061447364 ps
CPU time 1603.02 seconds
Started Aug 17 05:56:16 PM PDT 24
Finished Aug 17 06:22:59 PM PDT 24
Peak memory 272768 kb
Host smart-3bad74c1-f5f0-4668-bd3d-fa725f116b13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412659593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.412659593
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2522878524
Short name T626
Test name
Test status
Simulation time 372968201 ps
CPU time 19.11 seconds
Started Aug 17 05:56:20 PM PDT 24
Finished Aug 17 05:56:39 PM PDT 24
Peak memory 248828 kb
Host smart-30cd82ce-a855-4564-8a08-889fedc311f9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2522878524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2522878524
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1599397620
Short name T3
Test name
Test status
Simulation time 118294086 ps
CPU time 8.01 seconds
Started Aug 17 05:56:20 PM PDT 24
Finished Aug 17 05:56:28 PM PDT 24
Peak memory 248280 kb
Host smart-cde8a845-98bc-48ec-a139-32ed30ed714b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15993
97620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1599397620
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.4212027177
Short name T476
Test name
Test status
Simulation time 886544794 ps
CPU time 48.22 seconds
Started Aug 17 05:56:22 PM PDT 24
Finished Aug 17 05:57:11 PM PDT 24
Peak memory 248556 kb
Host smart-cee6ef62-94c5-43ee-ab15-d9b1ee3b618d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42120
27177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.4212027177
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2941632724
Short name T317
Test name
Test status
Simulation time 129117685877 ps
CPU time 2009.47 seconds
Started Aug 17 05:56:20 PM PDT 24
Finished Aug 17 06:29:49 PM PDT 24
Peak memory 266324 kb
Host smart-bce02658-8716-4284-835e-719e66b6ab98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941632724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2941632724
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3695837889
Short name T415
Test name
Test status
Simulation time 24600162665 ps
CPU time 1683.92 seconds
Started Aug 17 05:56:19 PM PDT 24
Finished Aug 17 06:24:24 PM PDT 24
Peak memory 273432 kb
Host smart-ab23fd9f-8792-44b3-8211-44c6943e5704
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695837889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3695837889
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.45098328
Short name T473
Test name
Test status
Simulation time 462503876 ps
CPU time 8.37 seconds
Started Aug 17 05:56:21 PM PDT 24
Finished Aug 17 05:56:29 PM PDT 24
Peak memory 248832 kb
Host smart-915f20ae-7ae8-4f69-abbe-8a2e58cf76f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45098
328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.45098328
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1771125656
Short name T484
Test name
Test status
Simulation time 3509378792 ps
CPU time 41.25 seconds
Started Aug 17 05:56:22 PM PDT 24
Finished Aug 17 05:57:03 PM PDT 24
Peak memory 248832 kb
Host smart-ddb8bbad-994d-4637-a3ef-484e545c5b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17711
25656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1771125656
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3431398180
Short name T40
Test name
Test status
Simulation time 815164765 ps
CPU time 12.21 seconds
Started Aug 17 05:56:21 PM PDT 24
Finished Aug 17 05:56:34 PM PDT 24
Peak memory 271040 kb
Host smart-2d50ae2f-a614-4437-a1c5-30496d85de37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3431398180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3431398180
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.4069327685
Short name T226
Test name
Test status
Simulation time 937213698 ps
CPU time 16.42 seconds
Started Aug 17 05:56:20 PM PDT 24
Finished Aug 17 05:56:37 PM PDT 24
Peak memory 254456 kb
Host smart-ae4ed5a7-0f78-4cee-91ef-5ff1ca889f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40693
27685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.4069327685
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2903693103
Short name T509
Test name
Test status
Simulation time 2250010873 ps
CPU time 38.34 seconds
Started Aug 17 05:56:16 PM PDT 24
Finished Aug 17 05:56:55 PM PDT 24
Peak memory 256120 kb
Host smart-275b2dd2-fcfc-45a5-b7c3-a1e94a5ce013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29036
93103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2903693103
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2391019333
Short name T105
Test name
Test status
Simulation time 4230527963 ps
CPU time 455.23 seconds
Started Aug 17 05:56:17 PM PDT 24
Finished Aug 17 06:03:52 PM PDT 24
Peak memory 270008 kb
Host smart-67d2bd70-2e94-4073-b7b5-be46eada3dc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391019333 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2391019333
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3039126379
Short name T613
Test name
Test status
Simulation time 375917663175 ps
CPU time 2434.54 seconds
Started Aug 17 05:58:39 PM PDT 24
Finished Aug 17 06:39:14 PM PDT 24
Peak memory 288788 kb
Host smart-9675674a-c0d1-4a7b-9dc9-0c8b15d1eae1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039126379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3039126379
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.791001022
Short name T2
Test name
Test status
Simulation time 523012737 ps
CPU time 45.65 seconds
Started Aug 17 05:58:41 PM PDT 24
Finished Aug 17 05:59:27 PM PDT 24
Peak memory 256540 kb
Host smart-1b330a81-85cb-4c10-bf81-d441aaebba66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79100
1022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.791001022
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2183279045
Short name T75
Test name
Test status
Simulation time 14919153161 ps
CPU time 57.12 seconds
Started Aug 17 05:58:41 PM PDT 24
Finished Aug 17 05:59:38 PM PDT 24
Peak memory 248908 kb
Host smart-c044cb9e-f688-4067-85cf-6eab73eb3392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21832
79045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2183279045
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.95625447
Short name T310
Test name
Test status
Simulation time 18075894518 ps
CPU time 1206.26 seconds
Started Aug 17 05:58:47 PM PDT 24
Finished Aug 17 06:18:54 PM PDT 24
Peak memory 265140 kb
Host smart-662e213c-e376-438e-908f-0c0c6cf9d170
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95625447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.95625447
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3796209233
Short name T514
Test name
Test status
Simulation time 216773219766 ps
CPU time 2740.81 seconds
Started Aug 17 05:58:47 PM PDT 24
Finished Aug 17 06:44:28 PM PDT 24
Peak memory 281596 kb
Host smart-e3ba8e90-1d9f-46a9-9291-5cb0b68aa6ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796209233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3796209233
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.542931299
Short name T281
Test name
Test status
Simulation time 9927424115 ps
CPU time 373.74 seconds
Started Aug 17 05:58:39 PM PDT 24
Finished Aug 17 06:04:53 PM PDT 24
Peak memory 247448 kb
Host smart-a1ca2974-1843-4bd1-acfd-e25849da6ee4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542931299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.542931299
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3457080040
Short name T439
Test name
Test status
Simulation time 576906032 ps
CPU time 42.74 seconds
Started Aug 17 05:58:41 PM PDT 24
Finished Aug 17 05:59:24 PM PDT 24
Peak memory 255552 kb
Host smart-bc32652d-e06c-4fdf-aca5-c9e1d3aaa590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34570
80040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3457080040
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.137908309
Short name T359
Test name
Test status
Simulation time 825995492 ps
CPU time 26.75 seconds
Started Aug 17 05:58:41 PM PDT 24
Finished Aug 17 05:59:08 PM PDT 24
Peak memory 248084 kb
Host smart-a3b1b567-5147-45fd-b8a3-b6c42d2fe2e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13790
8309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.137908309
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1015848404
Short name T235
Test name
Test status
Simulation time 3168500791 ps
CPU time 65.96 seconds
Started Aug 17 05:58:40 PM PDT 24
Finished Aug 17 05:59:46 PM PDT 24
Peak memory 257128 kb
Host smart-ce44d96a-2cc1-4267-adc2-ddc113f5bc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10158
48404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1015848404
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1567904054
Short name T217
Test name
Test status
Simulation time 1759689714 ps
CPU time 24.99 seconds
Started Aug 17 05:58:42 PM PDT 24
Finished Aug 17 05:59:07 PM PDT 24
Peak memory 256920 kb
Host smart-a01c2e73-f4ac-4dfd-878b-b89491a8d41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15679
04054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1567904054
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1984114424
Short name T483
Test name
Test status
Simulation time 1252642313 ps
CPU time 53.85 seconds
Started Aug 17 05:58:47 PM PDT 24
Finished Aug 17 05:59:41 PM PDT 24
Peak memory 256328 kb
Host smart-8767e006-ec23-4c55-9eb3-8f0478b4d109
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984114424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1984114424
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1693137400
Short name T267
Test name
Test status
Simulation time 21045632824 ps
CPU time 513.09 seconds
Started Aug 17 05:58:46 PM PDT 24
Finished Aug 17 06:07:19 PM PDT 24
Peak memory 271396 kb
Host smart-26957dbd-d638-4808-bd13-54ff251f948a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693137400 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1693137400
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2954123533
Short name T429
Test name
Test status
Simulation time 4699725032 ps
CPU time 94.12 seconds
Started Aug 17 05:58:49 PM PDT 24
Finished Aug 17 06:00:23 PM PDT 24
Peak memory 256984 kb
Host smart-4a7a24b8-2785-4c09-9c03-2627598bae9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29541
23533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2954123533
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1418461867
Short name T84
Test name
Test status
Simulation time 410665858 ps
CPU time 25.66 seconds
Started Aug 17 05:58:48 PM PDT 24
Finished Aug 17 05:59:13 PM PDT 24
Peak memory 248304 kb
Host smart-6353d040-6b22-4383-9fb9-dae9e779aaa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14184
61867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1418461867
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1137776971
Short name T275
Test name
Test status
Simulation time 8427300531 ps
CPU time 812.98 seconds
Started Aug 17 05:58:45 PM PDT 24
Finished Aug 17 06:12:19 PM PDT 24
Peak memory 273240 kb
Host smart-d7e1b200-1eb4-44c0-b2ba-92d6c533f751
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137776971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1137776971
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2650177354
Short name T540
Test name
Test status
Simulation time 37414585364 ps
CPU time 852.81 seconds
Started Aug 17 05:58:46 PM PDT 24
Finished Aug 17 06:12:59 PM PDT 24
Peak memory 270384 kb
Host smart-41909eb8-b5e7-49fc-98f0-50fe0ef04893
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650177354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2650177354
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2857683719
Short name T523
Test name
Test status
Simulation time 16461814264 ps
CPU time 181.38 seconds
Started Aug 17 05:58:47 PM PDT 24
Finished Aug 17 06:01:48 PM PDT 24
Peak memory 248788 kb
Host smart-a89836a0-ba2c-4022-b472-7050a94f280b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857683719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2857683719
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2988188182
Short name T400
Test name
Test status
Simulation time 828396463 ps
CPU time 58.81 seconds
Started Aug 17 05:58:48 PM PDT 24
Finished Aug 17 05:59:47 PM PDT 24
Peak memory 248684 kb
Host smart-b58ce674-300f-41cd-95a8-488ceffb413c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29881
88182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2988188182
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.989911602
Short name T621
Test name
Test status
Simulation time 3216551491 ps
CPU time 60.47 seconds
Started Aug 17 05:58:45 PM PDT 24
Finished Aug 17 05:59:46 PM PDT 24
Peak memory 256356 kb
Host smart-58a9c7e0-1b0d-433d-ac34-54d836b1c678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98991
1602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.989911602
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.602470605
Short name T620
Test name
Test status
Simulation time 1196732533 ps
CPU time 17.15 seconds
Started Aug 17 05:58:46 PM PDT 24
Finished Aug 17 05:59:03 PM PDT 24
Peak memory 248604 kb
Host smart-ea03e03e-d487-48c9-8b35-127468709574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60247
0605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.602470605
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3240055546
Short name T530
Test name
Test status
Simulation time 527248971 ps
CPU time 34.35 seconds
Started Aug 17 05:58:46 PM PDT 24
Finished Aug 17 05:59:20 PM PDT 24
Peak memory 256908 kb
Host smart-016ed843-2385-4dd7-91d9-e5973c49217b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32400
55546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3240055546
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.308230734
Short name T222
Test name
Test status
Simulation time 50420525592 ps
CPU time 2153.1 seconds
Started Aug 17 05:58:55 PM PDT 24
Finished Aug 17 06:34:48 PM PDT 24
Peak memory 297956 kb
Host smart-ab32b7e7-b468-4bf4-9b33-355f49327714
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308230734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.308230734
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.179891790
Short name T404
Test name
Test status
Simulation time 33907796592 ps
CPU time 2411.73 seconds
Started Aug 17 05:58:56 PM PDT 24
Finished Aug 17 06:39:08 PM PDT 24
Peak memory 288860 kb
Host smart-1a3b1534-2564-4a8d-a8bb-dcb6974636a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179891790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.179891790
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3789231725
Short name T365
Test name
Test status
Simulation time 548588450 ps
CPU time 44.48 seconds
Started Aug 17 05:58:54 PM PDT 24
Finished Aug 17 05:59:39 PM PDT 24
Peak memory 257024 kb
Host smart-bb951987-48e5-4b56-b8cd-37cbaf07d3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37892
31725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3789231725
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1966718642
Short name T304
Test name
Test status
Simulation time 221199444093 ps
CPU time 3072.52 seconds
Started Aug 17 05:58:57 PM PDT 24
Finished Aug 17 06:50:10 PM PDT 24
Peak memory 289512 kb
Host smart-b42026d0-5906-4907-ba74-608fef505c08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966718642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1966718642
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1174794469
Short name T488
Test name
Test status
Simulation time 34775787747 ps
CPU time 2029.69 seconds
Started Aug 17 05:58:58 PM PDT 24
Finished Aug 17 06:32:47 PM PDT 24
Peak memory 273468 kb
Host smart-f1bd7fbf-762a-4784-8c64-0a8a54928db4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174794469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1174794469
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.4101868056
Short name T572
Test name
Test status
Simulation time 15560670079 ps
CPU time 314.29 seconds
Started Aug 17 05:58:57 PM PDT 24
Finished Aug 17 06:04:12 PM PDT 24
Peak memory 247980 kb
Host smart-fe96defb-f878-40f1-a196-6f19706b9094
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101868056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.4101868056
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2333195426
Short name T263
Test name
Test status
Simulation time 1341898335 ps
CPU time 48.7 seconds
Started Aug 17 05:58:56 PM PDT 24
Finished Aug 17 05:59:44 PM PDT 24
Peak memory 248840 kb
Host smart-a942fda4-d30f-4d8c-80b0-9858edd10923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23331
95426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2333195426
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3243684988
Short name T487
Test name
Test status
Simulation time 5401927260 ps
CPU time 79.64 seconds
Started Aug 17 05:58:55 PM PDT 24
Finished Aug 17 06:00:15 PM PDT 24
Peak memory 257068 kb
Host smart-3eae8798-3a6f-43fe-aa3e-3c1e726e5837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32436
84988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3243684988
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3802514801
Short name T462
Test name
Test status
Simulation time 675509734 ps
CPU time 50.11 seconds
Started Aug 17 05:58:55 PM PDT 24
Finished Aug 17 05:59:45 PM PDT 24
Peak memory 257016 kb
Host smart-ebe31822-936c-4a49-b7f4-b202b4fd4526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38025
14801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3802514801
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2073780230
Short name T461
Test name
Test status
Simulation time 796200023 ps
CPU time 38.07 seconds
Started Aug 17 05:58:55 PM PDT 24
Finished Aug 17 05:59:34 PM PDT 24
Peak memory 256976 kb
Host smart-f783efb3-ae79-4849-ad11-98586dc6e08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20737
80230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2073780230
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1812760569
Short name T671
Test name
Test status
Simulation time 2145150046 ps
CPU time 181.56 seconds
Started Aug 17 05:58:55 PM PDT 24
Finished Aug 17 06:01:57 PM PDT 24
Peak memory 256968 kb
Host smart-a0b7e901-aa76-4e01-afd0-96ba029c61a8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812760569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1812760569
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.4053101642
Short name T61
Test name
Test status
Simulation time 13730482769 ps
CPU time 206.37 seconds
Started Aug 17 05:58:56 PM PDT 24
Finished Aug 17 06:02:22 PM PDT 24
Peak memory 267256 kb
Host smart-fa6419e3-360d-439f-bfd6-604d14d8fbe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053101642 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.4053101642
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2267238102
Short name T98
Test name
Test status
Simulation time 11752441273 ps
CPU time 1156.81 seconds
Started Aug 17 05:59:04 PM PDT 24
Finished Aug 17 06:18:21 PM PDT 24
Peak memory 288256 kb
Host smart-e8c84452-587f-4844-ba3e-d20229e8e567
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267238102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2267238102
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.573334109
Short name T563
Test name
Test status
Simulation time 296920936 ps
CPU time 25.31 seconds
Started Aug 17 05:58:54 PM PDT 24
Finished Aug 17 05:59:19 PM PDT 24
Peak memory 257040 kb
Host smart-3c0eb46c-795e-4881-87a4-9620e8854279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57333
4109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.573334109
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1923547711
Short name T614
Test name
Test status
Simulation time 433397829 ps
CPU time 34.3 seconds
Started Aug 17 05:58:53 PM PDT 24
Finished Aug 17 05:59:27 PM PDT 24
Peak memory 248632 kb
Host smart-5a7d5690-507d-472f-838c-15fa9052ac2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19235
47711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1923547711
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1607339023
Short name T19
Test name
Test status
Simulation time 53597697644 ps
CPU time 1616.33 seconds
Started Aug 17 05:59:04 PM PDT 24
Finished Aug 17 06:26:00 PM PDT 24
Peak memory 273480 kb
Host smart-b5a2c98f-7b96-4e93-962b-18766d11f78e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607339023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1607339023
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2987381035
Short name T603
Test name
Test status
Simulation time 252812560709 ps
CPU time 1533.15 seconds
Started Aug 17 05:59:05 PM PDT 24
Finished Aug 17 06:24:39 PM PDT 24
Peak memory 273016 kb
Host smart-90a4d35e-d1c5-403a-965c-373d96581d68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987381035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2987381035
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1615117581
Short name T289
Test name
Test status
Simulation time 9907684974 ps
CPU time 425.8 seconds
Started Aug 17 05:58:59 PM PDT 24
Finished Aug 17 06:06:05 PM PDT 24
Peak memory 247752 kb
Host smart-87688e09-9a63-42f5-8c0c-a0c028c34283
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615117581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1615117581
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2541031165
Short name T355
Test name
Test status
Simulation time 906820416 ps
CPU time 28.1 seconds
Started Aug 17 05:58:55 PM PDT 24
Finished Aug 17 05:59:23 PM PDT 24
Peak memory 248864 kb
Host smart-9a0f5904-0d55-45e8-8dc4-7bbb43545228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25410
31165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2541031165
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2738355292
Short name T658
Test name
Test status
Simulation time 1217207026 ps
CPU time 21.26 seconds
Started Aug 17 05:58:57 PM PDT 24
Finished Aug 17 05:59:18 PM PDT 24
Peak memory 248336 kb
Host smart-fe9b90ee-5893-4f16-8f7f-53d2421a73be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27383
55292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2738355292
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1212781424
Short name T661
Test name
Test status
Simulation time 2472919999 ps
CPU time 18.89 seconds
Started Aug 17 05:59:01 PM PDT 24
Finished Aug 17 05:59:19 PM PDT 24
Peak memory 257008 kb
Host smart-cd4e507b-3abf-4ba4-96a4-998d87d623cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12127
81424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1212781424
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.574871340
Short name T538
Test name
Test status
Simulation time 443128737 ps
CPU time 30.25 seconds
Started Aug 17 05:58:56 PM PDT 24
Finished Aug 17 05:59:26 PM PDT 24
Peak memory 248756 kb
Host smart-4f39882c-bd9e-459c-bebc-68cfe50b2311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57487
1340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.574871340
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2015033478
Short name T573
Test name
Test status
Simulation time 48774490578 ps
CPU time 1955.74 seconds
Started Aug 17 05:59:01 PM PDT 24
Finished Aug 17 06:31:38 PM PDT 24
Peak memory 289708 kb
Host smart-bde0ab49-1f20-49a2-9a62-9b7fd29d6518
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015033478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2015033478
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.951102827
Short name T97
Test name
Test status
Simulation time 8096191577 ps
CPU time 145.73 seconds
Started Aug 17 05:59:04 PM PDT 24
Finished Aug 17 06:01:30 PM PDT 24
Peak memory 265692 kb
Host smart-a1af9aa0-aaee-4ceb-b7f5-feb53c4e0a64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951102827 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.951102827
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.4144703931
Short name T691
Test name
Test status
Simulation time 31620051819 ps
CPU time 1202.35 seconds
Started Aug 17 05:59:02 PM PDT 24
Finished Aug 17 06:19:04 PM PDT 24
Peak memory 286736 kb
Host smart-d0006d39-626d-4fde-b390-97d8cc22197d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144703931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.4144703931
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3340496903
Short name T701
Test name
Test status
Simulation time 1885978264 ps
CPU time 80.86 seconds
Started Aug 17 05:59:04 PM PDT 24
Finished Aug 17 06:00:25 PM PDT 24
Peak memory 256428 kb
Host smart-2dd3a1fd-13c5-4b71-a00a-cc8303e36555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33404
96903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3340496903
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3694858040
Short name T419
Test name
Test status
Simulation time 2730467719 ps
CPU time 52.91 seconds
Started Aug 17 05:59:04 PM PDT 24
Finished Aug 17 05:59:57 PM PDT 24
Peak memory 248712 kb
Host smart-246b620e-e8a7-4d98-8e4c-9f0c8dfa67db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36948
58040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3694858040
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.175829511
Short name T446
Test name
Test status
Simulation time 19631399135 ps
CPU time 1055.34 seconds
Started Aug 17 05:59:01 PM PDT 24
Finished Aug 17 06:16:37 PM PDT 24
Peak memory 273404 kb
Host smart-b2734835-8af7-404c-9338-c4cab55fa7d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175829511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.175829511
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.570861145
Short name T414
Test name
Test status
Simulation time 37429118947 ps
CPU time 2171.04 seconds
Started Aug 17 05:59:03 PM PDT 24
Finished Aug 17 06:35:15 PM PDT 24
Peak memory 282676 kb
Host smart-f8b08fd9-8fce-43b4-9dc3-1941338348d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570861145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.570861145
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3098632822
Short name T292
Test name
Test status
Simulation time 10666172973 ps
CPU time 460.76 seconds
Started Aug 17 05:59:03 PM PDT 24
Finished Aug 17 06:06:44 PM PDT 24
Peak memory 247728 kb
Host smart-ecbd5d8c-14a0-48cd-b3a5-7de4d144e965
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098632822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3098632822
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1544724828
Short name T343
Test name
Test status
Simulation time 192993893 ps
CPU time 25.11 seconds
Started Aug 17 05:59:02 PM PDT 24
Finished Aug 17 05:59:28 PM PDT 24
Peak memory 256216 kb
Host smart-707d50d5-fb62-446c-9359-be288ab30cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15447
24828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1544724828
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.499820557
Short name T416
Test name
Test status
Simulation time 500759479 ps
CPU time 36.37 seconds
Started Aug 17 05:59:04 PM PDT 24
Finished Aug 17 05:59:41 PM PDT 24
Peak memory 248176 kb
Host smart-3d0948a2-5013-4581-87c0-99f4bb5e72b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49982
0557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.499820557
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2877312051
Short name T610
Test name
Test status
Simulation time 4605571984 ps
CPU time 60.44 seconds
Started Aug 17 05:59:02 PM PDT 24
Finished Aug 17 06:00:03 PM PDT 24
Peak memory 256756 kb
Host smart-e5e439ce-bcf9-4da6-8b52-84656abd052a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28773
12051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2877312051
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1334917196
Short name T372
Test name
Test status
Simulation time 1515339811 ps
CPU time 38.05 seconds
Started Aug 17 05:59:04 PM PDT 24
Finished Aug 17 05:59:42 PM PDT 24
Peak memory 256956 kb
Host smart-49e7012a-190d-4e15-a20f-1121e6d0f510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13349
17196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1334917196
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2743817352
Short name T581
Test name
Test status
Simulation time 257143577937 ps
CPU time 1603.72 seconds
Started Aug 17 05:59:01 PM PDT 24
Finished Aug 17 06:25:45 PM PDT 24
Peak memory 272884 kb
Host smart-769b9747-82c8-4473-9582-456f94727b8f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743817352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2743817352
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3276360392
Short name T256
Test name
Test status
Simulation time 120401516923 ps
CPU time 2719.73 seconds
Started Aug 17 05:59:02 PM PDT 24
Finished Aug 17 06:44:22 PM PDT 24
Peak memory 289848 kb
Host smart-ba65b744-0dba-4652-a60d-b1b2dbf215e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276360392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3276360392
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3204720394
Short name T363
Test name
Test status
Simulation time 7404143230 ps
CPU time 237.25 seconds
Started Aug 17 05:59:03 PM PDT 24
Finished Aug 17 06:03:01 PM PDT 24
Peak memory 256544 kb
Host smart-65cc3961-b4e1-4818-9b88-dc44f95e0686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32047
20394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3204720394
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2495753420
Short name T524
Test name
Test status
Simulation time 2297238552 ps
CPU time 72.99 seconds
Started Aug 17 05:59:03 PM PDT 24
Finished Aug 17 06:00:17 PM PDT 24
Peak memory 248928 kb
Host smart-c587aea9-ceb5-445f-94d6-fc4f5a459758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24957
53420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2495753420
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.479107931
Short name T590
Test name
Test status
Simulation time 5228965508 ps
CPU time 673.3 seconds
Started Aug 17 05:59:10 PM PDT 24
Finished Aug 17 06:10:23 PM PDT 24
Peak memory 266212 kb
Host smart-49bb3050-7160-4da4-8bce-c1548604f758
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479107931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.479107931
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.171881475
Short name T279
Test name
Test status
Simulation time 58594718649 ps
CPU time 665.7 seconds
Started Aug 17 05:59:09 PM PDT 24
Finished Aug 17 06:10:15 PM PDT 24
Peak memory 248868 kb
Host smart-9e720458-b241-4281-871e-9886523df966
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171881475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.171881475
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.146875327
Short name T459
Test name
Test status
Simulation time 490460221 ps
CPU time 31.14 seconds
Started Aug 17 05:59:03 PM PDT 24
Finished Aug 17 05:59:34 PM PDT 24
Peak memory 256636 kb
Host smart-7b1276d1-f0a9-4f49-9295-1150ac9271ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14687
5327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.146875327
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1687143444
Short name T49
Test name
Test status
Simulation time 483567115 ps
CPU time 6.76 seconds
Started Aug 17 05:59:02 PM PDT 24
Finished Aug 17 05:59:08 PM PDT 24
Peak memory 239924 kb
Host smart-2ad95656-f6c1-4adb-aeba-b8bc3392d659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16871
43444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1687143444
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.22014127
Short name T83
Test name
Test status
Simulation time 942360920 ps
CPU time 23.1 seconds
Started Aug 17 05:59:04 PM PDT 24
Finished Aug 17 05:59:27 PM PDT 24
Peak memory 256216 kb
Host smart-27c9c64b-83e2-40cf-805b-8da07a61735f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22014
127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.22014127
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2520117142
Short name T675
Test name
Test status
Simulation time 1790716065 ps
CPU time 39.69 seconds
Started Aug 17 05:59:00 PM PDT 24
Finished Aug 17 05:59:40 PM PDT 24
Peak memory 256936 kb
Host smart-752f6e1f-32ce-4268-b896-7ed248d2dd50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25201
17142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2520117142
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2515749187
Short name T558
Test name
Test status
Simulation time 7473384046 ps
CPU time 838.1 seconds
Started Aug 17 05:59:08 PM PDT 24
Finished Aug 17 06:13:07 PM PDT 24
Peak memory 272828 kb
Host smart-77761aea-082f-4a27-89d0-9b854bfd250e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515749187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2515749187
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1641948910
Short name T420
Test name
Test status
Simulation time 170633895631 ps
CPU time 1012.14 seconds
Started Aug 17 05:59:09 PM PDT 24
Finished Aug 17 06:16:02 PM PDT 24
Peak memory 273328 kb
Host smart-b9bff17a-d6f9-412f-8b16-5efee7d9e7f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641948910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1641948910
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2277393293
Short name T182
Test name
Test status
Simulation time 16757512898 ps
CPU time 243.69 seconds
Started Aug 17 05:59:09 PM PDT 24
Finished Aug 17 06:03:13 PM PDT 24
Peak memory 250272 kb
Host smart-5c7ce486-8e1c-4186-b423-38a27b3c96e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22773
93293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2277393293
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.4101053319
Short name T676
Test name
Test status
Simulation time 2344763088 ps
CPU time 39.33 seconds
Started Aug 17 05:59:09 PM PDT 24
Finished Aug 17 05:59:48 PM PDT 24
Peak memory 248920 kb
Host smart-e3f516ea-ea12-4de3-9448-490caa0efaec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41010
53319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.4101053319
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.4084089532
Short name T202
Test name
Test status
Simulation time 32907987919 ps
CPU time 2379.75 seconds
Started Aug 17 05:59:17 PM PDT 24
Finished Aug 17 06:38:57 PM PDT 24
Peak memory 289216 kb
Host smart-c26dfa92-6464-41fb-85d3-c5f9cf4921a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084089532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.4084089532
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.4120254399
Short name T313
Test name
Test status
Simulation time 48420594126 ps
CPU time 1425.99 seconds
Started Aug 17 05:59:17 PM PDT 24
Finished Aug 17 06:23:03 PM PDT 24
Peak memory 273060 kb
Host smart-850293ba-523b-44d4-b591-0eb0cec80c76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120254399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.4120254399
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2343947297
Short name T426
Test name
Test status
Simulation time 4148749772 ps
CPU time 181.6 seconds
Started Aug 17 05:59:16 PM PDT 24
Finished Aug 17 06:02:18 PM PDT 24
Peak memory 248840 kb
Host smart-648b18a6-9455-44d7-a0fe-8de0f485fb7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343947297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2343947297
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.584449047
Short name T211
Test name
Test status
Simulation time 3534523084 ps
CPU time 59.49 seconds
Started Aug 17 05:59:07 PM PDT 24
Finished Aug 17 06:00:07 PM PDT 24
Peak memory 256996 kb
Host smart-d498baca-a75e-416d-9271-b17743b544c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58444
9047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.584449047
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4085382051
Short name T601
Test name
Test status
Simulation time 48476112 ps
CPU time 5.85 seconds
Started Aug 17 05:59:09 PM PDT 24
Finished Aug 17 05:59:15 PM PDT 24
Peak memory 239964 kb
Host smart-c0835749-4213-4b08-b398-6c835bbdbab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40853
82051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4085382051
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3389925806
Short name T223
Test name
Test status
Simulation time 359047272 ps
CPU time 24.72 seconds
Started Aug 17 05:59:08 PM PDT 24
Finished Aug 17 05:59:32 PM PDT 24
Peak memory 256180 kb
Host smart-b31c41a2-60a5-4438-a56e-02d1dd8b29cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33899
25806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3389925806
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3786323830
Short name T589
Test name
Test status
Simulation time 1585812948 ps
CPU time 53.57 seconds
Started Aug 17 05:59:10 PM PDT 24
Finished Aug 17 06:00:04 PM PDT 24
Peak memory 256984 kb
Host smart-bb58d7b1-da68-4478-9769-fe6c157ba4e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37863
23830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3786323830
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2977845201
Short name T391
Test name
Test status
Simulation time 3269356309 ps
CPU time 34.76 seconds
Started Aug 17 05:59:18 PM PDT 24
Finished Aug 17 05:59:53 PM PDT 24
Peak memory 256268 kb
Host smart-0f56a5e7-a80e-4f84-a522-fd50ca12e60e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977845201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2977845201
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.396603465
Short name T246
Test name
Test status
Simulation time 14047151151 ps
CPU time 497.12 seconds
Started Aug 17 05:59:17 PM PDT 24
Finished Aug 17 06:07:34 PM PDT 24
Peak memory 267336 kb
Host smart-08644706-b054-4495-93b9-2913c8441055
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396603465 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.396603465
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3807572741
Short name T452
Test name
Test status
Simulation time 73798028581 ps
CPU time 1504.14 seconds
Started Aug 17 05:59:17 PM PDT 24
Finished Aug 17 06:24:22 PM PDT 24
Peak memory 288996 kb
Host smart-db09ddd9-316d-4ec1-b6c1-32af72484890
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807572741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3807572741
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2060479421
Short name T632
Test name
Test status
Simulation time 29768365300 ps
CPU time 282.86 seconds
Started Aug 17 05:59:17 PM PDT 24
Finished Aug 17 06:03:59 PM PDT 24
Peak memory 251980 kb
Host smart-2001fdd1-e1c0-4b40-8ab9-d88ce73c11f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20604
79421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2060479421
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1748324390
Short name T609
Test name
Test status
Simulation time 1373043444 ps
CPU time 31.96 seconds
Started Aug 17 05:59:17 PM PDT 24
Finished Aug 17 05:59:49 PM PDT 24
Peak memory 256932 kb
Host smart-326d01fd-1599-4fe3-acfc-d88ced9b0c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17483
24390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1748324390
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3901314800
Short name T315
Test name
Test status
Simulation time 24015101546 ps
CPU time 619.66 seconds
Started Aug 17 05:59:16 PM PDT 24
Finished Aug 17 06:09:36 PM PDT 24
Peak memory 271728 kb
Host smart-108ea541-5a7a-45c7-9b49-109eec4429e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901314800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3901314800
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2686320344
Short name T554
Test name
Test status
Simulation time 37552014426 ps
CPU time 2041.96 seconds
Started Aug 17 05:59:19 PM PDT 24
Finished Aug 17 06:33:21 PM PDT 24
Peak memory 273312 kb
Host smart-bf61de20-3cbc-4bc1-9784-3c7b220f74f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686320344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2686320344
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.677283654
Short name T611
Test name
Test status
Simulation time 78388940611 ps
CPU time 844.92 seconds
Started Aug 17 05:59:20 PM PDT 24
Finished Aug 17 06:13:25 PM PDT 24
Peak memory 248808 kb
Host smart-816dddb0-7476-498b-af4d-810dddf6c56b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677283654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.677283654
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2555581231
Short name T555
Test name
Test status
Simulation time 787392666 ps
CPU time 40.65 seconds
Started Aug 17 05:59:19 PM PDT 24
Finished Aug 17 05:59:59 PM PDT 24
Peak memory 248796 kb
Host smart-f4e0a096-a26e-4b4b-b9d3-683b97efc3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25555
81231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2555581231
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.788639931
Short name T434
Test name
Test status
Simulation time 854392574 ps
CPU time 50.52 seconds
Started Aug 17 05:59:20 PM PDT 24
Finished Aug 17 06:00:11 PM PDT 24
Peak memory 256324 kb
Host smart-54956178-2d69-4a51-8db0-60bfd87387ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78863
9931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.788639931
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.363917855
Short name T600
Test name
Test status
Simulation time 162066038 ps
CPU time 15.65 seconds
Started Aug 17 05:59:16 PM PDT 24
Finished Aug 17 05:59:32 PM PDT 24
Peak memory 256128 kb
Host smart-5e4422d6-10c8-41a8-a66a-e21719444a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36391
7855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.363917855
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2442639898
Short name T539
Test name
Test status
Simulation time 1417567366 ps
CPU time 38.05 seconds
Started Aug 17 05:59:16 PM PDT 24
Finished Aug 17 05:59:55 PM PDT 24
Peak memory 248820 kb
Host smart-5fb1f644-5539-45c6-879d-ad6a195f6fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24426
39898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2442639898
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.702411949
Short name T425
Test name
Test status
Simulation time 933041166 ps
CPU time 48.13 seconds
Started Aug 17 05:59:17 PM PDT 24
Finished Aug 17 06:00:05 PM PDT 24
Peak memory 257000 kb
Host smart-cad73fca-3bd0-44da-9a84-cb50554dc217
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702411949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.702411949
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2733782709
Short name T242
Test name
Test status
Simulation time 16974000293 ps
CPU time 580.35 seconds
Started Aug 17 05:59:17 PM PDT 24
Finished Aug 17 06:08:58 PM PDT 24
Peak memory 271396 kb
Host smart-888fe5aa-f0ed-41c4-a7ad-ec9a7b4d1e24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733782709 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2733782709
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1914647160
Short name T690
Test name
Test status
Simulation time 62232619175 ps
CPU time 3370.47 seconds
Started Aug 17 05:59:26 PM PDT 24
Finished Aug 17 06:55:37 PM PDT 24
Peak memory 289680 kb
Host smart-fd4691dc-47ae-4d0c-a1c9-a181ba7984bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914647160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1914647160
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3445226738
Short name T470
Test name
Test status
Simulation time 2674006069 ps
CPU time 193.46 seconds
Started Aug 17 05:59:22 PM PDT 24
Finished Aug 17 06:02:36 PM PDT 24
Peak memory 257036 kb
Host smart-4ec0df68-2bdc-4760-ba17-dc57f69992de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34452
26738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3445226738
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.911115074
Short name T379
Test name
Test status
Simulation time 887627144 ps
CPU time 26 seconds
Started Aug 17 05:59:23 PM PDT 24
Finished Aug 17 05:59:49 PM PDT 24
Peak memory 248380 kb
Host smart-598c72f3-7bf4-478b-ade5-0562913659b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91111
5074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.911115074
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1257652531
Short name T273
Test name
Test status
Simulation time 17677716282 ps
CPU time 802.86 seconds
Started Aug 17 05:59:22 PM PDT 24
Finished Aug 17 06:12:46 PM PDT 24
Peak memory 273344 kb
Host smart-23626d59-ab5f-431c-9a7b-3aa9e12e4ff6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257652531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1257652531
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2379188317
Short name T406
Test name
Test status
Simulation time 74455578068 ps
CPU time 1142.39 seconds
Started Aug 17 05:59:23 PM PDT 24
Finished Aug 17 06:18:25 PM PDT 24
Peak memory 265160 kb
Host smart-cdb1ca7f-7858-4d0f-9198-5d257074e2b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379188317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2379188317
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2945461695
Short name T110
Test name
Test status
Simulation time 21955258158 ps
CPU time 423.46 seconds
Started Aug 17 05:59:25 PM PDT 24
Finished Aug 17 06:06:28 PM PDT 24
Peak memory 248816 kb
Host smart-42561517-6a99-4019-b1ec-25fda25c25de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945461695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2945461695
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.491315704
Short name T682
Test name
Test status
Simulation time 1934380060 ps
CPU time 28.5 seconds
Started Aug 17 05:59:17 PM PDT 24
Finished Aug 17 05:59:45 PM PDT 24
Peak memory 256200 kb
Host smart-a08bee42-6bcb-4943-8554-c7b690261d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49131
5704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.491315704
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1092211318
Short name T467
Test name
Test status
Simulation time 1001736825 ps
CPU time 61.89 seconds
Started Aug 17 05:59:17 PM PDT 24
Finished Aug 17 06:00:19 PM PDT 24
Peak memory 256992 kb
Host smart-684f0e2b-fb39-4ceb-b279-13c884425228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10922
11318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1092211318
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2435741016
Short name T22
Test name
Test status
Simulation time 1990288287 ps
CPU time 33.39 seconds
Started Aug 17 05:59:22 PM PDT 24
Finished Aug 17 05:59:56 PM PDT 24
Peak memory 247832 kb
Host smart-acb1678f-e062-4f35-8698-664184598a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24357
41016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2435741016
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3568112547
Short name T598
Test name
Test status
Simulation time 257454700 ps
CPU time 5.04 seconds
Started Aug 17 05:59:15 PM PDT 24
Finished Aug 17 05:59:20 PM PDT 24
Peak memory 251716 kb
Host smart-51a97aa5-ebc3-459b-82c7-89fda586b70a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35681
12547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3568112547
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1317731542
Short name T41
Test name
Test status
Simulation time 1242756666 ps
CPU time 84.44 seconds
Started Aug 17 05:59:20 PM PDT 24
Finished Aug 17 06:00:44 PM PDT 24
Peak memory 250048 kb
Host smart-85d06dbd-fd15-4d53-bc28-e7e1427ff287
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317731542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1317731542
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.4243227343
Short name T66
Test name
Test status
Simulation time 231710052906 ps
CPU time 3481.37 seconds
Started Aug 17 05:59:23 PM PDT 24
Finished Aug 17 06:57:25 PM PDT 24
Peak memory 289184 kb
Host smart-b614913c-9b01-47c8-9254-5ee16af53f4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243227343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.4243227343
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2763485420
Short name T560
Test name
Test status
Simulation time 1209071284 ps
CPU time 120.3 seconds
Started Aug 17 05:59:22 PM PDT 24
Finished Aug 17 06:01:22 PM PDT 24
Peak memory 256452 kb
Host smart-2fa38fb6-45c8-40f6-b56d-df6eff489f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27634
85420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2763485420
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3927282741
Short name T229
Test name
Test status
Simulation time 4309350082 ps
CPU time 63 seconds
Started Aug 17 05:59:24 PM PDT 24
Finished Aug 17 06:00:27 PM PDT 24
Peak memory 248768 kb
Host smart-5d53cb9b-f2f9-40e3-ace3-bb79cbce0be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39272
82741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3927282741
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.711478913
Short name T465
Test name
Test status
Simulation time 646870561052 ps
CPU time 1732.56 seconds
Started Aug 17 05:59:31 PM PDT 24
Finished Aug 17 06:28:23 PM PDT 24
Peak memory 271828 kb
Host smart-bf809fe6-ed9f-4066-86bf-aee627a5a2d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711478913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.711478913
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1555134145
Short name T298
Test name
Test status
Simulation time 39260696766 ps
CPU time 409.55 seconds
Started Aug 17 05:59:30 PM PDT 24
Finished Aug 17 06:06:20 PM PDT 24
Peak memory 255772 kb
Host smart-503e5fe6-e25d-4828-bcd2-a5d68b2cd926
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555134145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1555134145
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2248097555
Short name T405
Test name
Test status
Simulation time 5056452379 ps
CPU time 34.9 seconds
Started Aug 17 05:59:22 PM PDT 24
Finished Aug 17 05:59:57 PM PDT 24
Peak memory 256028 kb
Host smart-b1cc4dc2-6a68-4520-97a9-6d06db78b670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22480
97555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2248097555
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2170678791
Short name T362
Test name
Test status
Simulation time 648824511 ps
CPU time 46.44 seconds
Started Aug 17 05:59:19 PM PDT 24
Finished Aug 17 06:00:05 PM PDT 24
Peak memory 256524 kb
Host smart-2f0e13a9-5154-4ebb-9078-80f504cfbc53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21706
78791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2170678791
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.684964767
Short name T445
Test name
Test status
Simulation time 5716682664 ps
CPU time 58.45 seconds
Started Aug 17 05:59:22 PM PDT 24
Finished Aug 17 06:00:21 PM PDT 24
Peak memory 248488 kb
Host smart-9de80674-5de2-42ce-a266-67e80772e8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68496
4767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.684964767
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1238267978
Short name T417
Test name
Test status
Simulation time 1130639943 ps
CPU time 33.23 seconds
Started Aug 17 05:59:24 PM PDT 24
Finished Aug 17 05:59:57 PM PDT 24
Peak memory 256808 kb
Host smart-79288d29-4443-49ac-a6f6-4374a65f5229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12382
67978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1238267978
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.576382136
Short name T687
Test name
Test status
Simulation time 18738435261 ps
CPU time 597.46 seconds
Started Aug 17 05:59:30 PM PDT 24
Finished Aug 17 06:09:28 PM PDT 24
Peak memory 281896 kb
Host smart-f2f29107-3ac7-4ed8-abf7-7c205dfffd8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576382136 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.576382136
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.437515541
Short name T193
Test name
Test status
Simulation time 228943818 ps
CPU time 3.8 seconds
Started Aug 17 05:56:29 PM PDT 24
Finished Aug 17 05:56:33 PM PDT 24
Peak memory 249016 kb
Host smart-07fc1cdd-a0bd-4829-9c2d-68c455596b45
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=437515541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.437515541
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3227045019
Short name T55
Test name
Test status
Simulation time 38594225192 ps
CPU time 1270.45 seconds
Started Aug 17 05:56:21 PM PDT 24
Finished Aug 17 06:17:32 PM PDT 24
Peak memory 289196 kb
Host smart-d6267547-3b69-4a35-bcff-1c69171c9c22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227045019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3227045019
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1181179710
Short name T493
Test name
Test status
Simulation time 1010527848 ps
CPU time 41.45 seconds
Started Aug 17 05:56:27 PM PDT 24
Finished Aug 17 05:57:09 PM PDT 24
Peak memory 248756 kb
Host smart-ff2a6309-aaff-4147-aad6-3c89d6e420c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1181179710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1181179710
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3724877467
Short name T505
Test name
Test status
Simulation time 29671938 ps
CPU time 4.57 seconds
Started Aug 17 05:56:21 PM PDT 24
Finished Aug 17 05:56:25 PM PDT 24
Peak memory 250848 kb
Host smart-621b4037-aa29-41c6-b8cc-d4b86d4b8330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37248
77467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3724877467
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2902381385
Short name T418
Test name
Test status
Simulation time 251336504 ps
CPU time 12.27 seconds
Started Aug 17 05:56:20 PM PDT 24
Finished Aug 17 05:56:33 PM PDT 24
Peak memory 248408 kb
Host smart-c65eac20-4061-4fd6-907e-78a79fd9c905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29023
81385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2902381385
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1151237944
Short name T705
Test name
Test status
Simulation time 17298258659 ps
CPU time 1142.74 seconds
Started Aug 17 05:56:26 PM PDT 24
Finished Aug 17 06:15:29 PM PDT 24
Peak memory 271596 kb
Host smart-41f9a020-2da2-450f-8738-2632a1564300
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151237944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1151237944
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.667567442
Short name T433
Test name
Test status
Simulation time 48559150735 ps
CPU time 1428.09 seconds
Started Aug 17 05:56:27 PM PDT 24
Finished Aug 17 06:20:16 PM PDT 24
Peak memory 266232 kb
Host smart-4121f912-bd64-444a-a633-96d56da0a100
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667567442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.667567442
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2889559573
Short name T652
Test name
Test status
Simulation time 17877548280 ps
CPU time 363.56 seconds
Started Aug 17 05:56:31 PM PDT 24
Finished Aug 17 06:02:35 PM PDT 24
Peak memory 247752 kb
Host smart-81bb0f75-f89c-4f95-9ffb-f2d8f38fccfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889559573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2889559573
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1320312534
Short name T42
Test name
Test status
Simulation time 1391970556 ps
CPU time 52.63 seconds
Started Aug 17 05:56:21 PM PDT 24
Finished Aug 17 05:57:14 PM PDT 24
Peak memory 256760 kb
Host smart-3038068b-1306-4f49-b5e1-1c2b5a31cb42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13203
12534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1320312534
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1122202517
Short name T64
Test name
Test status
Simulation time 594561450 ps
CPU time 18.58 seconds
Started Aug 17 05:56:21 PM PDT 24
Finished Aug 17 05:56:39 PM PDT 24
Peak memory 256096 kb
Host smart-d83f6646-8443-4eea-92e1-1f8c4524247d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11222
02517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1122202517
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1977710905
Short name T475
Test name
Test status
Simulation time 807454894 ps
CPU time 52.04 seconds
Started Aug 17 05:56:18 PM PDT 24
Finished Aug 17 05:57:10 PM PDT 24
Peak memory 256452 kb
Host smart-6c454709-bd1a-400d-b23d-09d79c93751d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19777
10905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1977710905
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.927992763
Short name T518
Test name
Test status
Simulation time 317424838 ps
CPU time 25.58 seconds
Started Aug 17 05:56:19 PM PDT 24
Finished Aug 17 05:56:44 PM PDT 24
Peak memory 256312 kb
Host smart-e3ff61fc-808e-471b-9a39-b0e54f225940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92799
2763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.927992763
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.121883620
Short name T268
Test name
Test status
Simulation time 65893321065 ps
CPU time 1599.17 seconds
Started Aug 17 05:56:26 PM PDT 24
Finished Aug 17 06:23:06 PM PDT 24
Peak memory 289856 kb
Host smart-44db3a33-66d4-4de8-b3d4-e506a3145ce5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121883620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.121883620
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.25118653
Short name T453
Test name
Test status
Simulation time 8489170853 ps
CPU time 280.15 seconds
Started Aug 17 05:56:27 PM PDT 24
Finished Aug 17 06:01:08 PM PDT 24
Peak memory 267440 kb
Host smart-6112fa7b-e67f-4cbb-9c92-64fe0ef8bfda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25118653 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.25118653
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2897020569
Short name T43
Test name
Test status
Simulation time 587019483 ps
CPU time 3.89 seconds
Started Aug 17 05:56:29 PM PDT 24
Finished Aug 17 05:56:32 PM PDT 24
Peak memory 248880 kb
Host smart-c73e97e2-3f8d-4fdb-8936-6877f7b7e1b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2897020569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2897020569
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2764911499
Short name T662
Test name
Test status
Simulation time 28022820110 ps
CPU time 1212.55 seconds
Started Aug 17 05:56:31 PM PDT 24
Finished Aug 17 06:16:43 PM PDT 24
Peak memory 286472 kb
Host smart-c10d6f7a-54b4-45d5-bf74-f5ec55233637
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764911499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2764911499
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2906165115
Short name T210
Test name
Test status
Simulation time 843979945 ps
CPU time 37.96 seconds
Started Aug 17 05:56:28 PM PDT 24
Finished Aug 17 05:57:07 PM PDT 24
Peak memory 248832 kb
Host smart-424cf167-23ee-435d-94ef-793cb9f35ce0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2906165115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2906165115
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2042646417
Short name T503
Test name
Test status
Simulation time 1177174297 ps
CPU time 115.68 seconds
Started Aug 17 05:56:31 PM PDT 24
Finished Aug 17 05:58:26 PM PDT 24
Peak memory 256764 kb
Host smart-c68a7450-fa80-4009-9aa1-f37da353745f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20426
46417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2042646417
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2811567417
Short name T251
Test name
Test status
Simulation time 3257825915 ps
CPU time 75.95 seconds
Started Aug 17 05:56:30 PM PDT 24
Finished Aug 17 05:57:46 PM PDT 24
Peak memory 248932 kb
Host smart-c41a438d-4d3c-4aea-961b-aa8f5421c340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28115
67417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2811567417
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.125501772
Short name T321
Test name
Test status
Simulation time 9848119747 ps
CPU time 1304.63 seconds
Started Aug 17 05:56:29 PM PDT 24
Finished Aug 17 06:18:14 PM PDT 24
Peak memory 281576 kb
Host smart-4880ee92-0307-442b-b01e-c2b03ec8a9a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125501772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.125501772
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1568470286
Short name T481
Test name
Test status
Simulation time 21523288689 ps
CPU time 1465.4 seconds
Started Aug 17 05:56:28 PM PDT 24
Finished Aug 17 06:20:54 PM PDT 24
Peak memory 273196 kb
Host smart-ccf0dd6c-780a-4374-a5b5-cd896e0fc417
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568470286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1568470286
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.192659441
Short name T52
Test name
Test status
Simulation time 1706148388 ps
CPU time 34.06 seconds
Started Aug 17 05:56:27 PM PDT 24
Finished Aug 17 05:57:01 PM PDT 24
Peak memory 256936 kb
Host smart-61280da6-c705-4fa8-b6ef-33e7f4972adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19265
9441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.192659441
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.4239807820
Short name T201
Test name
Test status
Simulation time 659140576 ps
CPU time 15.81 seconds
Started Aug 17 05:56:28 PM PDT 24
Finished Aug 17 05:56:44 PM PDT 24
Peak memory 248384 kb
Host smart-3be49569-cad9-4912-ad0a-01edb3d6b909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42398
07820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.4239807820
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.673230111
Short name T595
Test name
Test status
Simulation time 250925344 ps
CPU time 5.85 seconds
Started Aug 17 05:56:28 PM PDT 24
Finished Aug 17 05:56:34 PM PDT 24
Peak memory 239932 kb
Host smart-0accd7fc-7219-4df8-a339-80cfd016af30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67323
0111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.673230111
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3172949343
Short name T630
Test name
Test status
Simulation time 1390020490 ps
CPU time 59.68 seconds
Started Aug 17 05:56:29 PM PDT 24
Finished Aug 17 05:57:28 PM PDT 24
Peak memory 256988 kb
Host smart-68c15ba2-b516-434b-9ff4-f2138f3a12b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31729
49343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3172949343
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3811334190
Short name T571
Test name
Test status
Simulation time 41938524855 ps
CPU time 2415.58 seconds
Started Aug 17 05:56:27 PM PDT 24
Finished Aug 17 06:36:43 PM PDT 24
Peak memory 283412 kb
Host smart-d6a5bac6-3368-41ed-b498-3b176b11a3fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811334190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3811334190
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1833477714
Short name T107
Test name
Test status
Simulation time 9480071326 ps
CPU time 326.18 seconds
Started Aug 17 05:56:27 PM PDT 24
Finished Aug 17 06:01:54 PM PDT 24
Peak memory 267460 kb
Host smart-864c87aa-9d1f-4d99-b25b-770a40d71c0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833477714 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1833477714
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.4074831332
Short name T189
Test name
Test status
Simulation time 40838394 ps
CPU time 3.68 seconds
Started Aug 17 05:56:34 PM PDT 24
Finished Aug 17 05:56:38 PM PDT 24
Peak memory 248988 kb
Host smart-6f1da780-b42e-49ff-a92a-3763efcbd216
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4074831332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.4074831332
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.852313443
Short name T13
Test name
Test status
Simulation time 140385942657 ps
CPU time 2189.34 seconds
Started Aug 17 05:56:29 PM PDT 24
Finished Aug 17 06:32:58 PM PDT 24
Peak memory 285600 kb
Host smart-af95d336-7be2-4dae-b720-d97ac90b5296
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852313443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.852313443
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2006739608
Short name T451
Test name
Test status
Simulation time 1024969527 ps
CPU time 14.07 seconds
Started Aug 17 05:56:37 PM PDT 24
Finished Aug 17 05:56:51 PM PDT 24
Peak memory 248800 kb
Host smart-3da6547f-64d6-4677-ba2a-5193b1665780
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2006739608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2006739608
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2990453543
Short name T680
Test name
Test status
Simulation time 7473879317 ps
CPU time 29.57 seconds
Started Aug 17 05:56:29 PM PDT 24
Finished Aug 17 05:56:58 PM PDT 24
Peak memory 256512 kb
Host smart-37505850-156a-4171-9cd4-cbc8498643b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29904
53543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2990453543
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1244855809
Short name T440
Test name
Test status
Simulation time 1139909491 ps
CPU time 19.73 seconds
Started Aug 17 05:56:28 PM PDT 24
Finished Aug 17 05:56:48 PM PDT 24
Peak memory 248092 kb
Host smart-4a3b80a9-a2fb-4257-bbd1-964c26a09af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12448
55809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1244855809
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2819495956
Short name T302
Test name
Test status
Simulation time 134239797319 ps
CPU time 2296.36 seconds
Started Aug 17 05:56:37 PM PDT 24
Finished Aug 17 06:34:54 PM PDT 24
Peak memory 289400 kb
Host smart-430aa6dc-4ba7-4032-9f6a-65204f693bbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819495956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2819495956
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1355316770
Short name T627
Test name
Test status
Simulation time 168137880725 ps
CPU time 2509.16 seconds
Started Aug 17 05:56:40 PM PDT 24
Finished Aug 17 06:38:30 PM PDT 24
Peak memory 285076 kb
Host smart-f9ed19c2-c44f-4ba5-a5b8-5a402a8975ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355316770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1355316770
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.4049411966
Short name T579
Test name
Test status
Simulation time 110328664168 ps
CPU time 516.73 seconds
Started Aug 17 05:56:35 PM PDT 24
Finished Aug 17 06:05:12 PM PDT 24
Peak memory 248524 kb
Host smart-c72841d5-f50a-4eda-9bdf-9a1744ac8f0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049411966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.4049411966
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2146670080
Short name T401
Test name
Test status
Simulation time 1959191388 ps
CPU time 61.63 seconds
Started Aug 17 05:56:28 PM PDT 24
Finished Aug 17 05:57:29 PM PDT 24
Peak memory 256304 kb
Host smart-f96e17e9-c6b1-4c8b-a926-6a752abe6a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21466
70080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2146670080
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1954671787
Short name T605
Test name
Test status
Simulation time 1356819858 ps
CPU time 28.81 seconds
Started Aug 17 05:56:28 PM PDT 24
Finished Aug 17 05:56:57 PM PDT 24
Peak memory 256144 kb
Host smart-00ec39cf-a4ee-4633-a230-7c93cb3fd08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19546
71787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1954671787
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.583027837
Short name T77
Test name
Test status
Simulation time 782989464 ps
CPU time 32.56 seconds
Started Aug 17 05:56:30 PM PDT 24
Finished Aug 17 05:57:03 PM PDT 24
Peak memory 248844 kb
Host smart-3e40da40-87b8-497c-9956-b1952bbc1391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58302
7837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.583027837
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.202832529
Short name T347
Test name
Test status
Simulation time 483404944 ps
CPU time 19.55 seconds
Started Aug 17 05:56:28 PM PDT 24
Finished Aug 17 05:56:48 PM PDT 24
Peak memory 248824 kb
Host smart-536b7dee-72e1-40de-ace9-16882cac958f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20283
2529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.202832529
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.50830644
Short name T109
Test name
Test status
Simulation time 37736159376 ps
CPU time 1756.53 seconds
Started Aug 17 05:56:38 PM PDT 24
Finished Aug 17 06:25:55 PM PDT 24
Peak memory 289504 kb
Host smart-13fd6ced-231a-4801-981c-5e81e90843ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50830644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handl
er_stress_all.50830644
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.3241900829
Short name T506
Test name
Test status
Simulation time 9564774497 ps
CPU time 175.24 seconds
Started Aug 17 05:56:36 PM PDT 24
Finished Aug 17 05:59:31 PM PDT 24
Peak memory 266360 kb
Host smart-cd02a123-e95e-42e0-a600-e140bfbbb805
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241900829 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.3241900829
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3618159543
Short name T183
Test name
Test status
Simulation time 26151761 ps
CPU time 2.57 seconds
Started Aug 17 05:56:36 PM PDT 24
Finished Aug 17 05:56:38 PM PDT 24
Peak memory 249024 kb
Host smart-fd255ebb-0a24-4241-98ee-b07d7a501457
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3618159543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3618159543
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.966919168
Short name T485
Test name
Test status
Simulation time 35513405845 ps
CPU time 2051 seconds
Started Aug 17 05:56:37 PM PDT 24
Finished Aug 17 06:30:48 PM PDT 24
Peak memory 272828 kb
Host smart-478c3f0d-a404-4a23-a571-0082b76f09fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966919168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.966919168
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.213321708
Short name T622
Test name
Test status
Simulation time 653143046 ps
CPU time 10.08 seconds
Started Aug 17 05:56:37 PM PDT 24
Finished Aug 17 05:56:47 PM PDT 24
Peak memory 248820 kb
Host smart-f4400b6e-be96-4d23-81ed-c9b168d764fc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=213321708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.213321708
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3831631101
Short name T38
Test name
Test status
Simulation time 2916430647 ps
CPU time 103.94 seconds
Started Aug 17 05:56:36 PM PDT 24
Finished Aug 17 05:58:20 PM PDT 24
Peak memory 256616 kb
Host smart-b8904016-3aa9-4880-a22a-a94d81023ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38316
31101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3831631101
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3769931408
Short name T79
Test name
Test status
Simulation time 1937176901 ps
CPU time 56.81 seconds
Started Aug 17 05:56:35 PM PDT 24
Finished Aug 17 05:57:32 PM PDT 24
Peak memory 256972 kb
Host smart-27553b2a-8bf6-46dc-aa76-5449ba2a6b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37699
31408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3769931408
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3653393087
Short name T316
Test name
Test status
Simulation time 14877469499 ps
CPU time 1577.82 seconds
Started Aug 17 05:56:39 PM PDT 24
Finished Aug 17 06:22:57 PM PDT 24
Peak memory 289224 kb
Host smart-90c70ac7-2026-4299-8679-791c34b05378
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653393087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3653393087
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1702879638
Short name T348
Test name
Test status
Simulation time 12408478821 ps
CPU time 1323.77 seconds
Started Aug 17 05:56:38 PM PDT 24
Finished Aug 17 06:18:42 PM PDT 24
Peak memory 287348 kb
Host smart-d728ef3a-0f23-48c0-b80e-eb4f39dc4b21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702879638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1702879638
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2150263872
Short name T694
Test name
Test status
Simulation time 1043116425 ps
CPU time 45.99 seconds
Started Aug 17 05:56:38 PM PDT 24
Finished Aug 17 05:57:24 PM PDT 24
Peak memory 256144 kb
Host smart-4d392e81-619c-4cec-9d17-c74a914f80b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21502
63872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2150263872
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3935614750
Short name T369
Test name
Test status
Simulation time 1012344371 ps
CPU time 31.07 seconds
Started Aug 17 05:56:38 PM PDT 24
Finished Aug 17 05:57:09 PM PDT 24
Peak memory 248828 kb
Host smart-13847b26-64ad-4937-b73d-8e7fd725d042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39356
14750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3935614750
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3486601231
Short name T463
Test name
Test status
Simulation time 176344398 ps
CPU time 12.52 seconds
Started Aug 17 05:56:36 PM PDT 24
Finished Aug 17 05:56:49 PM PDT 24
Peak memory 248784 kb
Host smart-ea382b31-20ef-4dd4-8bac-c5a9828e5b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34866
01231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3486601231
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.881601666
Short name T594
Test name
Test status
Simulation time 1385535008 ps
CPU time 21.83 seconds
Started Aug 17 05:56:38 PM PDT 24
Finished Aug 17 05:57:00 PM PDT 24
Peak memory 248768 kb
Host smart-1839ed9d-a4cc-4d63-9e0a-f6f684bc4c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88160
1666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.881601666
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.141464911
Short name T625
Test name
Test status
Simulation time 74777024189 ps
CPU time 2658.62 seconds
Started Aug 17 05:56:38 PM PDT 24
Finished Aug 17 06:40:57 PM PDT 24
Peak memory 289728 kb
Host smart-58f50868-149e-40ff-9273-1066711ba8a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141464911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.141464911
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.951851155
Short name T195
Test name
Test status
Simulation time 96047394 ps
CPU time 3.36 seconds
Started Aug 17 05:56:34 PM PDT 24
Finished Aug 17 05:56:38 PM PDT 24
Peak memory 248936 kb
Host smart-e0919cfd-62e1-4423-b65a-d50ec196e303
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=951851155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.951851155
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3013195923
Short name T423
Test name
Test status
Simulation time 10928182252 ps
CPU time 1347.28 seconds
Started Aug 17 05:56:39 PM PDT 24
Finished Aug 17 06:19:07 PM PDT 24
Peak memory 281064 kb
Host smart-7c8e9041-1194-4e68-8453-42f40cd7d84f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013195923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3013195923
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2925118799
Short name T371
Test name
Test status
Simulation time 1028493341 ps
CPU time 16.48 seconds
Started Aug 17 05:56:35 PM PDT 24
Finished Aug 17 05:56:51 PM PDT 24
Peak memory 248696 kb
Host smart-cd7c5284-9ec9-4133-a72c-b2582b980bce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2925118799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2925118799
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2938611728
Short name T482
Test name
Test status
Simulation time 1300011806 ps
CPU time 133.17 seconds
Started Aug 17 05:56:40 PM PDT 24
Finished Aug 17 05:58:53 PM PDT 24
Peak memory 256408 kb
Host smart-3c4d1340-32e9-4138-a66c-16ca615598e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29386
11728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2938611728
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.258841531
Short name T408
Test name
Test status
Simulation time 373567749 ps
CPU time 5.55 seconds
Started Aug 17 05:56:36 PM PDT 24
Finished Aug 17 05:56:41 PM PDT 24
Peak memory 253308 kb
Host smart-f6c8a3ad-7690-4297-b3fb-91efbd92dfa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25884
1531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.258841531
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1926691126
Short name T200
Test name
Test status
Simulation time 348650072741 ps
CPU time 2969.55 seconds
Started Aug 17 05:56:39 PM PDT 24
Finished Aug 17 06:46:09 PM PDT 24
Peak memory 287788 kb
Host smart-59433abe-5a43-4825-99ec-fe7e1a94f909
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926691126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1926691126
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2421130374
Short name T492
Test name
Test status
Simulation time 192032121288 ps
CPU time 1789.55 seconds
Started Aug 17 05:56:39 PM PDT 24
Finished Aug 17 06:26:29 PM PDT 24
Peak memory 270404 kb
Host smart-14935ecb-080c-405b-9e44-495e313e1ddd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421130374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2421130374
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.663074981
Short name T529
Test name
Test status
Simulation time 1456061228 ps
CPU time 22.39 seconds
Started Aug 17 05:56:36 PM PDT 24
Finished Aug 17 05:56:59 PM PDT 24
Peak memory 256112 kb
Host smart-0ae60222-84de-4d8c-9183-bcaa7a7c8d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66307
4981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.663074981
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3592994103
Short name T90
Test name
Test status
Simulation time 207090940 ps
CPU time 20.31 seconds
Started Aug 17 05:56:36 PM PDT 24
Finished Aug 17 05:56:57 PM PDT 24
Peak memory 256144 kb
Host smart-68a10855-f94b-42c4-925e-344d977d5d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35929
94103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3592994103
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.118432128
Short name T76
Test name
Test status
Simulation time 731328049 ps
CPU time 20.54 seconds
Started Aug 17 05:56:39 PM PDT 24
Finished Aug 17 05:57:00 PM PDT 24
Peak memory 256876 kb
Host smart-4ce481c9-1a67-4008-8286-e20e9a119241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11843
2128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.118432128
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.737417674
Short name T583
Test name
Test status
Simulation time 481351022 ps
CPU time 20.46 seconds
Started Aug 17 05:56:38 PM PDT 24
Finished Aug 17 05:56:59 PM PDT 24
Peak memory 256896 kb
Host smart-a33133a7-a514-478b-b253-21a201a7c208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73741
7674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.737417674
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.728161229
Short name T34
Test name
Test status
Simulation time 58006019998 ps
CPU time 2694.55 seconds
Started Aug 17 05:56:37 PM PDT 24
Finished Aug 17 06:41:32 PM PDT 24
Peak memory 299620 kb
Host smart-c9501825-1943-43d4-bb8d-0a0de19ff8c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728161229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.728161229
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3732141138
Short name T657
Test name
Test status
Simulation time 10659126650 ps
CPU time 312.19 seconds
Started Aug 17 05:56:33 PM PDT 24
Finished Aug 17 06:01:46 PM PDT 24
Peak memory 273588 kb
Host smart-6f72853c-8638-4999-ad5a-d1007265a451
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732141138 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3732141138
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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