Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T44,T45,T193
1	1	Covered	T1,T2,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T11

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13564	0	0
DisabledNoTrigBkwd_A	2147483647	649162	0	0
DisabledNoTrigFwd_A	2147483647	1310197834	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13564	0	0
T6	538902	0	0	0
T17	1731514	0	0	0
T18	748562	0	0	0
T19	817066	0	0	0
T20	320606	0	0	0
T44	2954	590	0	0
T45	8048	773	0	0
T46	48876	0	0	0
T47	241806	0	0	0
T62	28419	0	0	0
T74	8464	0	0	0
T86	72249	0	0	0
T193	0	1040	0	0
T194	0	1521	0	0
T195	0	290	0	0
T196	0	224	0	0
T197	0	1956	0	0
T198	0	231	0	0
T199	0	594	0	0
T200	0	896	0	0
T201	4033	642	0	0
T202	0	975	0	0
T203	0	502	0	0
T204	0	796	0	0
T205	0	717	0	0
T206	0	511	0	0
T207	0	318	0	0
T208	0	181	0	0
T209	0	536	0	0
T210	0	271	0	0
T211	692307	0	0	0
T212	153248	0	0	0
T213	339120	0	0	0
T214	11541	0	0	0
T215	26022	0	0	0
T216	65277	0	0	0
T217	324233	0	0	0
T218	113528	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	649162	0	0
T1	19402	20	0	0
T2	2750664	2	0	0
T3	1216707	0	0	0
T4	172976	298	0	0
T5	121297	1241	0	0
T6	0	2	0	0
T7	2299896	11200	0	0
T11	213855	3	0	0
T12	625287	1965	0	0
T13	336984	4649	0	0
T14	559844	412	0	0
T15	113480	36	0	0
T17	0	257	0	0
T19	0	12	0	0
T21	77394	14	0	0
T26	50242	29	0	0
T29	31456	94	0	0
T42	16546	0	0	0
T43	150113	24	0	0
T44	0	15	0	0
T45	0	4	0	0
T46	0	29	0	0
T47	0	2	0	0
T48	8096	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1310197834	0	0
T1	38804	22832	0	0
T2	3667552	2317398	0	0
T3	1622276	1140579	0	0
T4	172976	76585	0	0
T7	3066528	770416	0	0
T11	285140	272345	0	0
T12	833716	632708	0	0
T13	449312	117706	0	0
T14	559844	282370	0	0
T15	113480	11890	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T11,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201
1	1	Covered	T1,T11,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T11,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	563095079	642	0	0
DisabledNoTrigBkwd_A	563095079	164767	0	0
DisabledNoTrigFwd_A	563095079	314583523	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	642	0	0
T62	28419	0	0	0
T201	4033	642	0	0
T211	692307	0	0	0
T212	153248	0	0	0
T213	339120	0	0	0
T214	11541	0	0	0
T215	26022	0	0	0
T216	65277	0	0	0
T217	324233	0	0	0
T218	113528	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	164767	0	0
T1	9701	6	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	207	0	0
T7	766632	2834	0	0
T11	71285	3	0	0
T12	208429	2	0	0
T13	112328	1604	0	0
T14	139961	0	0	0
T15	28370	15	0	0
T21	0	14	0	0
T26	0	10	0	0
T29	0	94	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	314583523	0	0
T1	9701	3505	0	0
T2	916888	481778	0	0
T3	405569	115980	0	0
T4	43244	20421	0	0
T7	766632	595	0	0
T11	71285	64978	0	0
T12	208429	207432	0	0
T13	112328	1032	0	0
T14	139961	1874	0	0
T15	28370	1971	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T11,T7
1	1	Covered	T1,T2,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T45,T198,T204
1	1	Covered	T1,T2,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	563095079	2629	0	0
DisabledNoTrigBkwd_A	563095079	143527	0	0
DisabledNoTrigFwd_A	563095079	353057590	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	2629	0	0
T6	269451	0	0	0
T17	865757	0	0	0
T18	374281	0	0	0
T19	817066	0	0	0
T20	320606	0	0	0
T45	4024	773	0	0
T46	24438	0	0	0
T47	120903	0	0	0
T74	4232	0	0	0
T86	72249	0	0	0
T198	0	231	0	0
T204	0	796	0	0
T206	0	511	0	0
T207	0	318	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	143527	0	0
T2	916888	2	0	0
T3	405569	0	0	0
T4	43244	32	0	0
T5	0	19	0	0
T6	0	2	0	0
T7	766632	6694	0	0
T11	71285	0	0	0
T12	208429	1963	0	0
T13	112328	1323	0	0
T14	139961	0	0	0
T15	28370	5	0	0
T21	38697	0	0	0
T26	0	6	0	0
T45	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	353057590	0	0
T1	9701	8067	0	0
T2	916888	2032	0	0
T3	405569	297921	0	0
T4	43244	23871	0	0
T7	766632	2646	0	0
T11	71285	64973	0	0
T12	208429	8779	0	0
T13	112328	3568	0	0
T14	139961	139951	0	0
T15	28370	1987	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T13

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T44,T194,T195
1	1	Covered	T1,T7,T13

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	563095079	6867	0	0
DisabledNoTrigBkwd_A	563095079	170264	0	0
DisabledNoTrigFwd_A	563095079	330324545	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	6867	0	0
T6	269451	0	0	0
T17	865757	0	0	0
T18	374281	0	0	0
T23	27354	0	0	0
T44	2954	590	0	0
T45	4024	0	0	0
T46	24438	0	0	0
T47	120903	0	0	0
T73	10459	0	0	0
T74	4232	0	0	0
T194	0	1521	0	0
T195	0	290	0	0
T196	0	224	0	0
T197	0	1956	0	0
T199	0	594	0	0
T202	0	975	0	0
T208	0	181	0	0
T209	0	536	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	170264	0	0
T1	9701	14	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	18	0	0
T5	0	9	0	0
T7	766632	1672	0	0
T11	71285	0	0	0
T12	208429	0	0	0
T13	112328	1722	0	0
T14	139961	0	0	0
T15	28370	10	0	0
T17	0	256	0	0
T26	0	1	0	0
T44	0	15	0	0
T47	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	330324545	0	0
T1	9701	1632	0	0
T2	916888	916794	0	0
T3	405569	363339	0	0
T4	43244	26530	0	0
T7	766632	603	0	0
T11	71285	71197	0	0
T12	208429	208422	0	0
T13	112328	1040	0	0
T14	139961	139951	0	0
T15	28370	5907	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T193,T200,T203
1	1	Covered	T12,T13,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T14,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	563095079	3426	0	0
DisabledNoTrigBkwd_A	563095079	170604	0	0
DisabledNoTrigFwd_A	563095079	312232176	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	3426	0	0
T28	265954	0	0	0
T79	22818	0	0	0
T102	909749	0	0	0
T193	4614	1040	0	0
T200	0	896	0	0
T203	0	502	0	0
T205	0	717	0	0
T210	0	271	0	0
T219	18849	0	0	0
T220	450547	0	0	0
T221	736129	0	0	0
T222	790525	0	0	0
T223	19305	0	0	0
T224	123963	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	170604	0	0
T4	43244	41	0	0
T5	121297	1213	0	0
T14	139961	412	0	0
T15	28370	6	0	0
T17	0	1	0	0
T19	0	12	0	0
T20	0	899	0	0
T21	38697	0	0	0
T26	50242	12	0	0
T29	31456	0	0	0
T42	16546	0	0	0
T43	150113	24	0	0
T46	0	29	0	0
T48	8096	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	312232176	0	0
T1	9701	9628	0	0
T2	916888	916794	0	0
T3	405569	363339	0	0
T4	43244	5763	0	0
T7	766632	766572	0	0
T11	71285	71197	0	0
T12	208429	208075	0	0
T13	112328	112066	0	0
T14	139961	594	0	0
T15	28370	2025	0	0