Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.39	100.00	97.78	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T22
1	1	1	Covered	T1,T2,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T7
1	0	1	Covered	T2,T12,T13
1	1	0	Covered	T1,T11,T7
1	1	1	Covered	T1,T11,T7

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T7
0	1	Covered	T5,T23,T6
1	0	Covered	T7,T5,T20

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T7
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T5,T20

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T7
1	0	Covered	T5,T24,T25
1	1	Covered	T5,T23,T6

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T11,T7
1	Covered	T2,T13,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T7,T12,T13

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T11,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T1,T26,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T7

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T11
Phase1St	198	Covered	T1,T2,T11
Phase2St	215	Covered	T1,T2,T11
Phase3St	233	Covered	T1,T2,T11
TerminalSt	249	Covered	T1,T2,T11
TimeoutSt	159	Covered	T1,T11,T7

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T11
IdleSt->TimeoutSt	159	Covered	T1,T11,T7
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T6,T27,T28
Phase0St->Phase1St	198	Covered	T1,T2,T11
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T7,T29,T6
Phase1St->Phase2St	215	Covered	T1,T2,T11
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T5,T17,T20
Phase2St->Phase3St	233	Covered	T1,T2,T11
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T7,T26,T5
Phase3St->TerminalSt	249	Covered	T1,T2,T11
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T11
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T11,T7
TimeoutSt->Phase0St	172	Covered	T7,T5,T23

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T5,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T30,T31
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T29,T32
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T17,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T7,T26,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1107	0	0
CheckAccumTrig0_A	2147483647	2287	0	0
CheckAccumTrig1_A	2147483647	118	0	0
CheckClr_A	2147483647	1118	0	0
CheckEn_A	2147483647	1006463096	0	0
CheckPhase0_A	2147483647	2572	0	0
CheckPhase1_A	2147483647	2516	0	0
CheckPhase2_A	2147483647	2472	0	0
CheckPhase3_A	2147483647	2420	0	0
CheckTimeout0_A	2147483647	2054	0	0
CheckTimeoutSt1_A	2147483647	279761	0	0
CheckTimeoutSt2_A	2147483647	1690	0	0
CheckTimeoutStTrig_A	2147483647	225	0	0
ErrorStAllEscAsserted_A	2147483647	5849	0	0
ErrorStIsTerminal_A	2147483647	4769	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1107	0	0
T8	185372	216	0	0
T9	0	120	0	0
T10	0	225	0	0
T16	3884408	0	0	0
T32	75308	0	0	0
T33	0	259	0	0
T34	0	287	0	0
T35	124820	0	0	0
T36	548440	0	0	0
T37	482796	0	0	0
T38	92608	0	0	0
T39	488872	0	0	0
T40	1089400	0	0	0
T41	879636	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2287	0	0
T1	19402	3	0	0
T2	2750664	2	0	0
T3	1216707	0	0	0
T4	172976	9	0	0
T5	121297	9	0	0
T6	0	1	0	0
T7	2299896	5	0	0
T11	213855	1	0	0
T12	625287	4	0	0
T13	336984	5	0	0
T14	559844	1	0	0
T15	113480	7	0	0
T17	0	4	0	0
T21	77394	1	0	0
T26	50242	5	0	0
T29	31456	2	0	0
T42	16546	3	0	0
T43	150113	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	8096	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	118	0	0
T4	86488	0	0	0
T5	0	1	0	0
T7	1533264	2	0	0
T12	416858	0	0	0
T13	224656	0	0	0
T14	279922	0	0	0
T15	56740	0	0	0
T20	641212	4	0	0
T21	77394	0	0	0
T24	0	1	0	0
T26	100484	0	0	0
T28	0	4	0	0
T29	62912	0	0	0
T31	0	3	0	0
T42	33092	0	0	0
T49	149426	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	50076	0	0	0
T65	360830	0	0	0
T66	284050	0	0	0
T67	68766	0	0	0
T68	227682	0	0	0
T69	94640	0	0	0
T70	1622172	0	0	0
T71	50202	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1118	0	0
T1	9701	1	0	0
T2	1833776	1	0	0
T3	811138	0	0	0
T4	172976	4	0	0
T5	121297	13	0	0
T6	0	4	0	0
T7	2299896	4	0	0
T11	213855	1	0	0
T12	625287	2	0	0
T13	336984	2	0	0
T14	559844	0	0	0
T15	113480	3	0	0
T17	0	2	0	0
T20	0	18	0	0
T21	116091	0	0	0
T26	100484	2	0	0
T29	62912	1	0	0
T32	0	3	0	0
T42	16546	2	0	0
T43	150113	0	0	0
T48	8096	0	0	0
T49	0	2	0	0
T65	0	1	0	0
T70	0	3	0	0
T71	0	3	0	0
T72	0	10	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1006463096	0	0
T1	38804	21744	0	0
T2	3667552	2317395	0	0
T3	1622276	1140576	0	0
T4	172976	75259	0	0
T7	3066528	770415	0	0
T11	285140	272341	0	0
T12	833716	430817	0	0
T13	449312	117706	0	0
T14	559844	282370	0	0
T15	113480	11890	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2572	0	0
T1	19402	3	0	0
T2	2750664	2	0	0
T3	1216707	0	0	0
T4	172976	9	0	0
T5	121297	9	0	0
T6	0	3	0	0
T7	2299896	7	0	0
T11	213855	1	0	0
T12	625287	4	0	0
T13	336984	5	0	0
T14	559844	1	0	0
T15	113480	7	0	0
T17	0	4	0	0
T19	0	1	0	0
T21	77394	1	0	0
T23	0	1	0	0
T26	50242	5	0	0
T29	31456	2	0	0
T42	16546	0	0	0
T43	150113	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	8096	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2516	0	0
T1	19402	3	0	0
T2	2750664	2	0	0
T3	1216707	0	0	0
T4	172976	9	0	0
T5	121297	9	0	0
T6	0	3	0	0
T7	2299896	6	0	0
T11	213855	1	0	0
T12	625287	4	0	0
T13	336984	5	0	0
T14	559844	1	0	0
T15	113480	7	0	0
T17	0	4	0	0
T19	0	1	0	0
T21	77394	1	0	0
T23	0	1	0	0
T26	50242	5	0	0
T29	31456	1	0	0
T42	16546	0	0	0
T43	150113	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	8096	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2472	0	0
T1	19402	3	0	0
T2	2750664	2	0	0
T3	1216707	0	0	0
T4	172976	9	0	0
T5	121297	9	0	0
T6	0	3	0	0
T7	2299896	6	0	0
T11	213855	1	0	0
T12	625287	4	0	0
T13	336984	5	0	0
T14	559844	1	0	0
T15	113480	7	0	0
T17	0	3	0	0
T19	0	1	0	0
T21	77394	1	0	0
T23	0	1	0	0
T26	50242	5	0	0
T29	31456	1	0	0
T42	16546	0	0	0
T43	150113	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	8096	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2420	0	0
T1	19402	3	0	0
T2	2750664	2	0	0
T3	1216707	0	0	0
T4	172976	9	0	0
T5	121297	9	0	0
T6	0	3	0	0
T7	2299896	5	0	0
T11	213855	1	0	0
T12	625287	4	0	0
T13	336984	5	0	0
T14	559844	1	0	0
T15	113480	7	0	0
T17	0	3	0	0
T19	0	1	0	0
T21	77394	1	0	0
T23	0	1	0	0
T26	50242	4	0	0
T29	31456	1	0	0
T42	16546	0	0	0
T43	150113	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	8096	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2054	0	0
T1	9701	1	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	172976	1	0	0
T5	121297	19	0	0
T6	0	23	0	0
T7	2299896	3	0	0
T11	142570	1	0	0
T12	625287	0	0	0
T13	336984	0	0	0
T14	559844	0	0	0
T15	113480	0	0	0
T20	0	11	0	0
T21	116091	1	0	0
T23	0	12	0	0
T26	150726	0	0	0
T29	94368	0	0	0
T32	0	7	0	0
T35	0	4	0	0
T36	0	3	0	0
T38	0	3	0	0
T42	33092	0	0	0
T43	150113	0	0	0
T48	8096	0	0	0
T64	0	1	0	0
T69	0	2	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	6	0	0
T73	0	6	0	0
T74	0	1	0	0
T75	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	279761	0	0
T1	9701	32	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	172976	42	0	0
T5	121297	1237	0	0
T6	0	4760	0	0
T7	2299896	113	0	0
T11	142570	87	0	0
T12	625287	0	0	0
T13	336984	0	0	0
T14	559844	0	0	0
T15	113480	0	0	0
T20	0	1110	0	0
T21	116091	34	0	0
T23	0	987	0	0
T26	150726	0	0	0
T29	94368	0	0	0
T32	0	3994	0	0
T35	0	483	0	0
T36	0	1103	0	0
T38	0	300	0	0
T42	33092	0	0	0
T43	150113	0	0	0
T48	8096	0	0	0
T64	0	174	0	0
T69	0	269	0	0
T70	0	390	0	0
T71	0	47	0	0
T72	0	1396	0	0
T73	0	342	0	0
T74	0	151	0	0
T75	0	692	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1690	0	0
T1	9701	1	0	0
T4	86488	1	0	0
T5	121297	17	0	0
T6	269451	15	0	0
T7	1533264	1	0	0
T11	142570	1	0	0
T12	416858	0	0	0
T13	224656	0	0	0
T14	279922	0	0	0
T15	56740	0	0	0
T17	865757	0	0	0
T20	0	5	0	0
T21	38697	1	0	0
T23	27354	11	0	0
T26	50242	0	0	0
T29	31456	0	0	0
T32	0	4	0	0
T35	0	4	0	0
T36	0	1	0	0
T38	0	3	0	0
T43	150113	0	0	0
T44	2954	0	0	0
T45	4024	0	0	0
T46	24438	0	0	0
T64	0	1	0	0
T69	0	2	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	7	0	0
T73	10459	6	0	0
T74	4232	1	0	0
T75	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	225	0	0
T5	121297	1	0	0
T6	1077804	5	0	0
T17	1731514	0	0	0
T18	1122843	0	0	0
T19	2451198	0	0	0
T20	641212	0	0	0
T23	54708	1	0	0
T24	0	1	0	0
T28	0	1	0	0
T32	0	3	0	0
T36	0	1	0	0
T43	150113	0	0	0
T44	2954	0	0	0
T45	8048	0	0	0
T46	48876	0	0	0
T47	362709	0	0	0
T49	149426	0	0	0
T50	0	3	0	0
T52	0	2	0	0
T64	50076	0	0	0
T65	360830	0	0	0
T66	284050	0	0	0
T67	0	1	0	0
T72	0	2	0	0
T73	10459	0	0	0
T74	8464	0	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	5	0	0
T81	0	2	0	0
T82	0	2	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	216747	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5849	0	0
T8	185372	1232	0	0
T9	0	661	0	0
T10	0	1244	0	0
T16	3884408	0	0	0
T32	75308	0	0	0
T33	0	1385	0	0
T34	0	1327	0	0
T35	124820	0	0	0
T36	548440	0	0	0
T37	482796	0	0	0
T38	92608	0	0	0
T39	488872	0	0	0
T40	1089400	0	0	0
T41	879636	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4769	0	0
T8	185372	992	0	0
T9	0	541	0	0
T10	0	1004	0	0
T16	3884408	0	0	0
T32	75308	0	0	0
T33	0	1145	0	0
T34	0	1087	0	0
T35	124820	0	0	0
T36	548440	0	0	0
T37	482796	0	0	0
T38	92608	0	0	0
T39	488872	0	0	0
T40	1089400	0	0	0
T41	879636	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	38804	38512	0	0
T2	3667552	3667176	0	0
T3	1622276	1621976	0	0
T4	172976	172460	0	0
T7	3066528	3066288	0	0
T11	285140	284788	0	0
T12	833716	833688	0	0
T13	449312	449280	0	0
T14	559844	559804	0	0
T15	113480	113152	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	38804	38512	0	0
T2	3667552	3667176	0	0
T3	1622276	1621976	0	0
T4	172976	172460	0	0
T7	3066528	3066288	0	0
T11	285140	284788	0	0
T12	833716	833688	0	0
T13	449312	449280	0	0
T14	559844	559804	0	0
T15	113480	113152	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T7,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T4
1	0	1	Covered	T5,T44,T65
1	1	0	Covered	T11,T4,T15
1	1	1	Covered	T1,T5,T23

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T23
0	1	Covered	T6,T32,T36
1	0	Covered	T20,T32,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T5,T23
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T32,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T23
1	0	Not Covered
1	1	Covered	T6,T32,T36

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T13
1	Covered	T44,T86,T36

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T4
1	Covered	T13,T26,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T26,T5
1	Covered	T1,T7,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T13
1	Covered	T5,T17,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T7,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T7,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T13,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T7,T13
Phase1St	198	Covered	T1,T7,T13
Phase2St	215	Covered	T1,T7,T13
Phase3St	233	Covered	T1,T7,T13
TerminalSt	249	Covered	T1,T7,T13
TimeoutSt	159	Covered	T1,T5,T23

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T7,T13
IdleSt->TimeoutSt	159	Covered	T1,T5,T23
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T30,T87
Phase0St->Phase1St	198	Covered	T1,T7,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T88,T83,T89
Phase1St->Phase2St	215	Covered	T1,T7,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T17,T20,T90
Phase2St->Phase3St	233	Covered	T1,T7,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T91,T92,T93
Phase3St->TerminalSt	249	Covered	T1,T7,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T26
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T5,T23
TimeoutSt->Phase0St	172	Covered	T6,T20,T32

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T23
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T32
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T23
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T87,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T7,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T7,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T88,T83,T89
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T7,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T7,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T17,T20,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T7,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T7,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T91,T92,T93
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T7,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T7,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T7,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	563095079	247	0	0
CheckAccumTrig0_A	563095079	491	0	0
CheckAccumTrig1_A	563095079	23	0	0
CheckClr_A	563095079	244	0	0
CheckEn_A	562813369	250381249	0	0
CheckPhase0_A	563095079	561	0	0
CheckPhase1_A	563095079	551	0	0
CheckPhase2_A	563095079	541	0	0
CheckPhase3_A	563095079	530	0	0
CheckTimeout0_A	563095079	522	0	0
CheckTimeoutSt1_A	563095079	74381	0	0
CheckTimeoutSt2_A	563095079	437	0	0
CheckTimeoutStTrig_A	563095079	57	0	0
ErrorStAllEscAsserted_A	563095079	1433	0	0
ErrorStIsTerminal_A	563095079	1163	0	0
EscStateOut_A	562811736	562741101	0	0
u_state_regs_A	563095079	562908982	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	247	0	0
T8	46343	59	0	0
T9	0	25	0	0
T10	0	55	0	0
T16	971102	0	0	0
T32	18827	0	0	0
T33	0	41	0	0
T34	0	67	0	0
T35	31205	0	0	0
T36	137110	0	0	0
T37	120699	0	0	0
T38	23152	0	0	0
T39	122218	0	0	0
T40	272350	0	0	0
T41	219909	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	491	0	0
T1	9701	2	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	4	0	0
T5	0	3	0	0
T7	766632	1	0	0
T11	71285	0	0	0
T12	208429	0	0	0
T13	112328	1	0	0
T14	139961	0	0	0
T15	28370	1	0	0
T17	0	3	0	0
T26	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	23	0	0
T20	320606	2	0	0
T49	74713	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T64	25038	0	0	0
T65	180415	0	0	0
T66	142025	0	0	0
T67	34383	0	0	0
T68	113841	0	0	0
T69	47320	0	0	0
T70	811086	0	0	0
T71	25101	0	0	0
T91	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	244	0	0
T1	9701	1	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	3	0	0
T5	0	2	0	0
T6	0	1	0	0
T7	766632	0	0	0
T11	71285	0	0	0
T12	208429	0	0	0
T13	112328	0	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T17	0	2	0	0
T20	0	10	0	0
T26	0	1	0	0
T32	0	1	0	0
T49	0	1	0	0
T70	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562813369	250381249	0	0
T1	9701	1632	0	0
T2	916888	916793	0	0
T3	405569	363338	0	0
T4	43244	26529	0	0
T7	766632	603	0	0
T11	71285	71196	0	0
T12	208429	208422	0	0
T13	112328	1040	0	0
T14	139961	139951	0	0
T15	28370	5907	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	561	0	0
T1	9701	2	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	4	0	0
T5	0	3	0	0
T6	0	2	0	0
T7	766632	1	0	0
T11	71285	0	0	0
T12	208429	0	0	0
T13	112328	1	0	0
T14	139961	0	0	0
T15	28370	1	0	0
T17	0	3	0	0
T26	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	551	0	0
T1	9701	2	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	4	0	0
T5	0	3	0	0
T6	0	2	0	0
T7	766632	1	0	0
T11	71285	0	0	0
T12	208429	0	0	0
T13	112328	1	0	0
T14	139961	0	0	0
T15	28370	1	0	0
T17	0	3	0	0
T26	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	541	0	0
T1	9701	2	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	4	0	0
T5	0	3	0	0
T6	0	2	0	0
T7	766632	1	0	0
T11	71285	0	0	0
T12	208429	0	0	0
T13	112328	1	0	0
T14	139961	0	0	0
T15	28370	1	0	0
T17	0	2	0	0
T26	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	530	0	0
T1	9701	2	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	4	0	0
T5	0	3	0	0
T6	0	2	0	0
T7	766632	1	0	0
T11	71285	0	0	0
T12	208429	0	0	0
T13	112328	1	0	0
T14	139961	0	0	0
T15	28370	1	0	0
T17	0	2	0	0
T26	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	522	0	0
T1	9701	1	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	0	0	0
T5	0	3	0	0
T6	0	6	0	0
T7	766632	0	0	0
T11	71285	0	0	0
T12	208429	0	0	0
T13	112328	0	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T20	0	2	0	0
T23	0	2	0	0
T32	0	3	0	0
T35	0	4	0	0
T36	0	2	0	0
T69	0	1	0	0
T70	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	74381	0	0
T1	9701	32	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	0	0	0
T5	0	138	0	0
T6	0	958	0	0
T7	766632	0	0	0
T11	71285	0	0	0
T12	208429	0	0	0
T13	112328	0	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T20	0	3	0	0
T23	0	201	0	0
T32	0	2496	0	0
T35	0	483	0	0
T36	0	433	0	0
T69	0	143	0	0
T70	0	188	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	437	0	0
T1	9701	1	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	0	0	0
T5	0	3	0	0
T6	0	3	0	0
T7	766632	0	0	0
T11	71285	0	0	0
T12	208429	0	0	0
T13	112328	0	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T23	0	2	0	0
T32	0	2	0	0
T35	0	4	0	0
T36	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	57	0	0
T6	269451	2	0	0
T18	374281	0	0	0
T19	817066	0	0	0
T20	320606	0	0	0
T32	0	1	0	0
T36	0	1	0	0
T47	120903	0	0	0
T49	74713	0	0	0
T52	0	2	0	0
T64	25038	0	0	0
T65	180415	0	0	0
T66	142025	0	0	0
T72	0	2	0	0
T76	0	1	0	0
T77	0	1	0	0
T80	0	2	0	0
T83	0	1	0	0
T86	72249	0	0	0
T99	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	1433	0	0
T8	46343	312	0	0
T9	0	147	0	0
T10	0	329	0	0
T16	971102	0	0	0
T32	18827	0	0	0
T33	0	318	0	0
T34	0	327	0	0
T35	31205	0	0	0
T36	137110	0	0	0
T37	120699	0	0	0
T38	23152	0	0	0
T39	122218	0	0	0
T40	272350	0	0	0
T41	219909	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	1163	0	0
T8	46343	252	0	0
T9	0	117	0	0
T10	0	269	0	0
T16	971102	0	0	0
T32	18827	0	0	0
T33	0	258	0	0
T34	0	267	0	0
T35	31205	0	0	0
T36	137110	0	0	0
T37	120699	0	0	0
T38	23152	0	0	0
T39	122218	0	0	0
T40	272350	0	0	0
T41	219909	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562811736	562741101	0	0
T1	9701	9628	0	0
T2	916888	916794	0	0
T3	405569	405494	0	0
T4	43244	43115	0	0
T7	766632	766572	0	0
T11	71285	71197	0	0
T12	208429	208422	0	0
T13	112328	112320	0	0
T14	139961	139951	0	0
T15	28370	28288	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	562908982	0	0
T1	9701	9628	0	0
T2	916888	916794	0	0
T3	405569	405494	0	0
T4	43244	43115	0	0
T7	766632	766572	0	0
T11	71285	71197	0	0
T12	208429	208422	0	0
T13	112328	112320	0	0
T14	139961	139951	0	0
T15	28370	28288	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T7,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T7
1	0	1	Covered	T2,T12,T13
1	1	0	Covered	T1,T11,T4
1	1	1	Covered	T7,T5,T73

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T73
0	1	Covered	T23,T6,T32
1	0	Covered	T7,T28,T52

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T7,T5,T73
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T28,T52

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T73
1	0	Covered	T25
1	1	Covered	T23,T6,T32

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T12,T13
1	Covered	T2,T4,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T7,T12,T13

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T15,T5,T23

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T5,T65,T71

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T13,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T7,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T7,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T12,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T7,T12
Phase1St	198	Covered	T2,T7,T12
Phase2St	215	Covered	T2,T7,T12
Phase3St	233	Covered	T2,T7,T12
TerminalSt	249	Covered	T2,T7,T12
TimeoutSt	159	Covered	T7,T5,T73

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T2,T7,T12
IdleSt->TimeoutSt	159	Covered	T7,T5,T73
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T28,T100
Phase0St->Phase1St	198	Covered	T2,T7,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T7,T32,T101
Phase1St->Phase2St	215	Covered	T2,T7,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T102,T28
Phase2St->Phase3St	233	Covered	T2,T7,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T7,T6,T100
Phase3St->TerminalSt	249	Covered	T2,T7,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T7,T12
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T73,T23
TimeoutSt->Phase0St	172	Covered	T7,T23,T6

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T5,T73
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T23,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T7,T5,T73
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T73,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T100,T103
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T7,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T7,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T32,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T7,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T7,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T102,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T7,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T7,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T7,T6,T100
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T7,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T7,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T7,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T7,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	563095079	285	0	0
CheckAccumTrig0_A	563095079	470	0	0
CheckAccumTrig1_A	563095079	23	0	0
CheckClr_A	563095079	224	0	0
CheckEn_A	562813369	284427099	0	0
CheckPhase0_A	563095079	534	0	0
CheckPhase1_A	563095079	520	0	0
CheckPhase2_A	563095079	507	0	0
CheckPhase3_A	563095079	498	0	0
CheckTimeout0_A	563095079	532	0	0
CheckTimeoutSt1_A	563095079	79383	0	0
CheckTimeoutSt2_A	563095079	450	0	0
CheckTimeoutStTrig_A	563095079	53	0	0
ErrorStAllEscAsserted_A	563095079	1519	0	0
ErrorStIsTerminal_A	563095079	1249	0	0
EscStateOut_A	562811736	562741101	0	0
u_state_regs_A	563095079	562908982	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	285	0	0
T8	46343	66	0	0
T9	0	34	0	0
T10	0	51	0	0
T16	971102	0	0	0
T32	18827	0	0	0
T33	0	76	0	0
T34	0	58	0	0
T35	31205	0	0	0
T36	137110	0	0	0
T37	120699	0	0	0
T38	23152	0	0	0
T39	122218	0	0	0
T40	272350	0	0	0
T41	219909	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	470	0	0
T2	916888	2	0	0
T3	405569	0	0	0
T4	43244	1	0	0
T5	0	4	0	0
T6	0	1	0	0
T7	766632	4	0	0
T11	71285	0	0	0
T12	208429	3	0	0
T13	112328	3	0	0
T14	139961	0	0	0
T15	28370	3	0	0
T21	38697	0	0	0
T26	0	1	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	23	0	0
T4	43244	0	0	0
T7	766632	1	0	0
T12	208429	0	0	0
T13	112328	0	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T21	38697	0	0	0
T26	50242	0	0	0
T28	0	4	0	0
T29	31456	0	0	0
T42	16546	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	224	0	0
T2	916888	1	0	0
T3	405569	0	0	0
T4	43244	0	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	766632	4	0	0
T11	71285	0	0	0
T12	208429	2	0	0
T13	112328	2	0	0
T14	139961	0	0	0
T15	28370	2	0	0
T21	38697	0	0	0
T32	0	2	0	0
T71	0	3	0	0
T72	0	9	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562813369	284427099	0	0
T1	9701	8066	0	0
T2	916888	2032	0	0
T3	405569	297920	0	0
T4	43244	23870	0	0
T7	766632	2646	0	0
T11	71285	64972	0	0
T12	208429	8779	0	0
T13	112328	3568	0	0
T14	139961	139951	0	0
T15	28370	1987	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	534	0	0
T2	916888	2	0	0
T3	405569	0	0	0
T4	43244	1	0	0
T5	0	4	0	0
T7	766632	5	0	0
T11	71285	0	0	0
T12	208429	3	0	0
T13	112328	3	0	0
T14	139961	0	0	0
T15	28370	3	0	0
T21	38697	0	0	0
T23	0	1	0	0
T26	0	1	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	520	0	0
T2	916888	2	0	0
T3	405569	0	0	0
T4	43244	1	0	0
T5	0	4	0	0
T7	766632	4	0	0
T11	71285	0	0	0
T12	208429	3	0	0
T13	112328	3	0	0
T14	139961	0	0	0
T15	28370	3	0	0
T21	38697	0	0	0
T23	0	1	0	0
T26	0	1	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	507	0	0
T2	916888	2	0	0
T3	405569	0	0	0
T4	43244	1	0	0
T5	0	4	0	0
T7	766632	4	0	0
T11	71285	0	0	0
T12	208429	3	0	0
T13	112328	3	0	0
T14	139961	0	0	0
T15	28370	3	0	0
T21	38697	0	0	0
T23	0	1	0	0
T26	0	1	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	498	0	0
T2	916888	2	0	0
T3	405569	0	0	0
T4	43244	1	0	0
T5	0	4	0	0
T7	766632	3	0	0
T11	71285	0	0	0
T12	208429	3	0	0
T13	112328	3	0	0
T14	139961	0	0	0
T15	28370	3	0	0
T21	38697	0	0	0
T23	0	1	0	0
T26	0	1	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	532	0	0
T4	43244	0	0	0
T5	0	5	0	0
T6	0	6	0	0
T7	766632	1	0	0
T12	208429	0	0	0
T13	112328	0	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T21	38697	0	0	0
T23	0	5	0	0
T26	50242	0	0	0
T29	31456	0	0	0
T32	0	4	0	0
T38	0	1	0	0
T42	16546	0	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	3	0	0
T73	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	79383	0	0
T4	43244	0	0	0
T5	0	193	0	0
T6	0	1335	0	0
T7	766632	1	0	0
T12	208429	0	0	0
T13	112328	0	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T21	38697	0	0	0
T23	0	402	0	0
T26	50242	0	0	0
T29	31456	0	0	0
T32	0	1498	0	0
T38	0	163	0	0
T42	16546	0	0	0
T70	0	202	0	0
T71	0	47	0	0
T72	0	33	0	0
T73	0	146	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	450	0	0
T5	121297	5	0	0
T6	269451	3	0	0
T17	865757	0	0	0
T23	27354	4	0	0
T32	0	2	0	0
T38	0	1	0	0
T43	150113	0	0	0
T44	2954	0	0	0
T45	4024	0	0	0
T46	24438	0	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	3	0	0
T73	10459	2	0	0
T74	4232	0	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	53	0	0
T6	269451	3	0	0
T17	865757	0	0	0
T18	374281	0	0	0
T19	817066	0	0	0
T23	27354	1	0	0
T24	0	1	0	0
T32	0	2	0	0
T45	4024	0	0	0
T46	24438	0	0	0
T47	120903	0	0	0
T50	0	1	0	0
T74	4232	0	0	0
T80	0	2	0	0
T81	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	72249	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	1519	0	0
T8	46343	296	0	0
T9	0	165	0	0
T10	0	343	0	0
T16	971102	0	0	0
T32	18827	0	0	0
T33	0	368	0	0
T34	0	347	0	0
T35	31205	0	0	0
T36	137110	0	0	0
T37	120699	0	0	0
T38	23152	0	0	0
T39	122218	0	0	0
T40	272350	0	0	0
T41	219909	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	1249	0	0
T8	46343	236	0	0
T9	0	135	0	0
T10	0	283	0	0
T16	971102	0	0	0
T32	18827	0	0	0
T33	0	308	0	0
T34	0	287	0	0
T35	31205	0	0	0
T36	137110	0	0	0
T37	120699	0	0	0
T38	23152	0	0	0
T39	122218	0	0	0
T40	272350	0	0	0
T41	219909	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562811736	562741101	0	0
T1	9701	9628	0	0
T2	916888	916794	0	0
T3	405569	405494	0	0
T4	43244	43115	0	0
T7	766632	766572	0	0
T11	71285	71197	0	0
T12	208429	208422	0	0
T13	112328	112320	0	0
T14	139961	139951	0	0
T15	28370	28288	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	562908982	0	0
T1	9701	9628	0	0
T2	916888	916794	0	0
T3	405569	405494	0	0
T4	43244	43115	0	0
T7	766632	766572	0	0
T11	71285	71197	0	0
T12	208429	208422	0	0
T13	112328	112320	0	0
T14	139961	139951	0	0
T15	28370	28288	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T14,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T14,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T12,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T14,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T26,T5
1	0	1	Covered	T12,T15,T43
1	1	0	Covered	T11,T7,T4
1	1	1	Covered	T4,T5,T73

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T73
0	1	Covered	T6,T20,T36
1	0	Covered	T20,T77,T28

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T5,T73
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T77,T28

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T73
1	0	Covered	T24
1	1	Covered	T6,T20,T36

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T14,T15
1	Covered	T20,T32,T36

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T14,T15
1	Covered	T17,T46,T68

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T26,T5
1	Covered	T4,T14,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T14,T15
1	Covered	T4,T26,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T14,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T14,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T14,T15
Phase1St	198	Covered	T4,T14,T15
Phase2St	215	Covered	T4,T14,T15
Phase3St	233	Covered	T4,T14,T15
TerminalSt	249	Covered	T4,T14,T15
TimeoutSt	159	Covered	T4,T5,T73

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T4,T14,T15
IdleSt->TimeoutSt	159	Covered	T4,T5,T73
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T104,T24,T105
Phase0St->Phase1St	198	Covered	T4,T14,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T68,T75,T106
Phase1St->Phase2St	215	Covered	T4,T14,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T102,T89,T107
Phase2St->Phase3St	233	Covered	T4,T14,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T90,T108,T109
Phase3St->TerminalSt	249	Covered	T4,T14,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T5,T73
TimeoutSt->Phase0St	172	Covered	T6,T20,T36

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T14,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T73
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T36
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T73
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T73
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T105,T62,T110
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T14,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T14,T26
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T68,T75,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T14,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T14,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T102,T89,T107
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T14,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T14,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T90,T108,T109
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T14,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T14,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T14,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	563095079	321	0	0
CheckAccumTrig0_A	563095079	484	0	0
CheckAccumTrig1_A	563095079	31	0	0
CheckClr_A	563095079	228	0	0
CheckEn_A	562813369	246433337	0	0
CheckPhase0_A	563095079	548	0	0
CheckPhase1_A	563095079	536	0	0
CheckPhase2_A	563095079	530	0	0
CheckPhase3_A	563095079	520	0	0
CheckTimeout0_A	563095079	444	0	0
CheckTimeoutSt1_A	563095079	56156	0	0
CheckTimeoutSt2_A	563095079	364	0	0
CheckTimeoutStTrig_A	563095079	45	0	0
ErrorStAllEscAsserted_A	563095079	1429	0	0
ErrorStIsTerminal_A	563095079	1159	0	0
EscStateOut_A	562811736	562741101	0	0
u_state_regs_A	563095079	562908982	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	321	0	0
T8	46343	48	0	0
T9	0	35	0	0
T10	0	77	0	0
T16	971102	0	0	0
T32	18827	0	0	0
T33	0	82	0	0
T34	0	79	0	0
T35	31205	0	0	0
T36	137110	0	0	0
T37	120699	0	0	0
T38	23152	0	0	0
T39	122218	0	0	0
T40	272350	0	0	0
T41	219909	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	484	0	0
T4	43244	3	0	0
T5	121297	2	0	0
T14	139961	1	0	0
T15	28370	1	0	0
T17	0	1	0	0
T19	0	1	0	0
T20	0	3	0	0
T21	38697	0	0	0
T26	50242	1	0	0
T29	31456	0	0	0
T42	16546	0	0	0
T43	150113	1	0	0
T46	0	1	0	0
T48	8096	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	31	0	0
T20	320606	1	0	0
T28	0	1	0	0
T49	74713	0	0	0
T58	0	1	0	0
T59	0	3	0	0
T64	25038	0	0	0
T65	180415	0	0	0
T66	142025	0	0	0
T67	34383	0	0	0
T68	113841	0	0	0
T69	47320	0	0	0
T70	811086	0	0	0
T71	25101	0	0	0
T77	0	1	0	0
T91	0	2	0	0
T105	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	228	0	0
T4	43244	1	0	0
T5	121297	1	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T20	0	2	0	0
T21	38697	0	0	0
T26	50242	0	0	0
T29	31456	0	0	0
T42	16546	0	0	0
T43	150113	0	0	0
T48	8096	0	0	0
T65	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T75	0	5	0	0
T106	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562813369	246433337	0	0
T1	9701	9627	0	0
T2	916888	916793	0	0
T3	405569	363338	0	0
T4	43244	4440	0	0
T7	766632	766571	0	0
T11	71285	71196	0	0
T12	208429	208075	0	0
T13	112328	112066	0	0
T14	139961	594	0	0
T15	28370	2025	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	548	0	0
T4	43244	3	0	0
T5	121297	2	0	0
T6	0	1	0	0
T14	139961	1	0	0
T15	28370	1	0	0
T17	0	1	0	0
T19	0	1	0	0
T21	38697	0	0	0
T26	50242	1	0	0
T29	31456	0	0	0
T42	16546	0	0	0
T43	150113	1	0	0
T46	0	1	0	0
T48	8096	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	536	0	0
T4	43244	3	0	0
T5	121297	2	0	0
T6	0	1	0	0
T14	139961	1	0	0
T15	28370	1	0	0
T17	0	1	0	0
T19	0	1	0	0
T21	38697	0	0	0
T26	50242	1	0	0
T29	31456	0	0	0
T42	16546	0	0	0
T43	150113	1	0	0
T46	0	1	0	0
T48	8096	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	530	0	0
T4	43244	3	0	0
T5	121297	2	0	0
T6	0	1	0	0
T14	139961	1	0	0
T15	28370	1	0	0
T17	0	1	0	0
T19	0	1	0	0
T21	38697	0	0	0
T26	50242	1	0	0
T29	31456	0	0	0
T42	16546	0	0	0
T43	150113	1	0	0
T46	0	1	0	0
T48	8096	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	520	0	0
T4	43244	3	0	0
T5	121297	2	0	0
T6	0	1	0	0
T14	139961	1	0	0
T15	28370	1	0	0
T17	0	1	0	0
T19	0	1	0	0
T21	38697	0	0	0
T26	50242	1	0	0
T29	31456	0	0	0
T42	16546	0	0	0
T43	150113	1	0	0
T46	0	1	0	0
T48	8096	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	444	0	0
T4	43244	1	0	0
T5	121297	6	0	0
T6	0	3	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T20	0	3	0	0
T21	38697	0	0	0
T26	50242	0	0	0
T29	31456	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T42	16546	0	0	0
T43	150113	0	0	0
T48	8096	0	0	0
T69	0	1	0	0
T72	0	3	0	0
T73	0	3	0	0
T75	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	56156	0	0
T4	43244	42	0	0
T5	121297	166	0	0
T6	0	691	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T20	0	422	0	0
T21	38697	0	0	0
T26	50242	0	0	0
T29	31456	0	0	0
T36	0	670	0	0
T38	0	137	0	0
T42	16546	0	0	0
T43	150113	0	0	0
T48	8096	0	0	0
T69	0	126	0	0
T72	0	1363	0	0
T73	0	146	0	0
T75	0	692	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	364	0	0
T4	43244	1	0	0
T5	121297	6	0	0
T6	0	2	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T20	0	1	0	0
T21	38697	0	0	0
T26	50242	0	0	0
T29	31456	0	0	0
T38	0	2	0	0
T42	16546	0	0	0
T43	150113	0	0	0
T48	8096	0	0	0
T50	0	3	0	0
T69	0	1	0	0
T72	0	3	0	0
T73	0	3	0	0
T75	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	45	0	0
T6	269451	1	0	0
T18	374281	0	0	0
T19	817066	0	0	0
T20	320606	1	0	0
T36	0	1	0	0
T47	120903	0	0	0
T49	74713	0	0	0
T50	0	1	0	0
T64	25038	0	0	0
T65	180415	0	0	0
T66	142025	0	0	0
T75	0	1	0	0
T78	0	1	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	1	0	0
T86	72249	0	0	0
T99	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	1429	0	0
T8	46343	330	0	0
T9	0	171	0	0
T10	0	264	0	0
T16	971102	0	0	0
T32	18827	0	0	0
T33	0	353	0	0
T34	0	311	0	0
T35	31205	0	0	0
T36	137110	0	0	0
T37	120699	0	0	0
T38	23152	0	0	0
T39	122218	0	0	0
T40	272350	0	0	0
T41	219909	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	1159	0	0
T8	46343	270	0	0
T9	0	141	0	0
T10	0	204	0	0
T16	971102	0	0	0
T32	18827	0	0	0
T33	0	293	0	0
T34	0	251	0	0
T35	31205	0	0	0
T36	137110	0	0	0
T37	120699	0	0	0
T38	23152	0	0	0
T39	122218	0	0	0
T40	272350	0	0	0
T41	219909	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562811736	562741101	0	0
T1	9701	9628	0	0
T2	916888	916794	0	0
T3	405569	405494	0	0
T4	43244	43115	0	0
T7	766632	766572	0	0
T11	71285	71197	0	0
T12	208429	208422	0	0
T13	112328	112320	0	0
T14	139961	139951	0	0
T15	28370	28288	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	562908982	0	0
T1	9701	9628	0	0
T2	916888	916794	0	0
T3	405569	405494	0	0
T4	43244	43115	0	0
T7	766632	766572	0	0
T11	71285	71197	0	0
T12	208429	208422	0	0
T13	112328	112320	0	0
T14	139961	139951	0	0
T15	28370	28288	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T11,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T11,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T22
1	1	1	Covered	T1,T11,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T7
1	0	1	Covered	T12,T13,T14
1	1	0	Covered	T1,T11,T4
1	1	1	Covered	T11,T7,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T7,T21
0	1	Covered	T5,T67,T50
1	0	Covered	T7,T5,T20

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T11,T7,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T5,T20

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T7,T21
1	0	Covered	T5
1	1	Covered	T5,T67,T50

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T11,T7
1	Covered	T13,T4,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T11,T7
1	Covered	T42,T5,T47

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T13,T4
1	Covered	T11,T7,T12

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T7,T12
1	Covered	T1,T26,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T7,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T7,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T4,T29

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T7,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T11,T7
Phase1St	198	Covered	T1,T11,T7
Phase2St	215	Covered	T1,T11,T7
Phase3St	233	Covered	T1,T11,T7
TerminalSt	249	Covered	T1,T11,T7
TimeoutSt	159	Covered	T11,T7,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T11,T12
IdleSt->TimeoutSt	159	Covered	T11,T7,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T31,T104
Phase0St->Phase1St	198	Covered	T1,T11,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T6,T104
Phase1St->Phase2St	215	Covered	T1,T11,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T5,T114,T115
Phase2St->Phase3St	233	Covered	T1,T11,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T26,T5,T104
Phase3St->TerminalSt	249	Covered	T1,T11,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T11,T4,T15
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T11,T7,T21
TimeoutSt->Phase0St	172	Covered	T7,T5,T20

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T7,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T5,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T11,T7,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T11,T7,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T31,T116,T53
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T11,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T11,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T59,T117
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T11,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T11,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T114,T115
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T11,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T11,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T5,T104
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T11,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T11,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T11,T15,T42
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T11,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	563095079	254	0	0
CheckAccumTrig0_A	563095079	842	0	0
CheckAccumTrig1_A	563095079	41	0	0
CheckClr_A	563095079	422	0	0
CheckEn_A	562813369	225221411	0	0
CheckPhase0_A	563095079	929	0	0
CheckPhase1_A	563095079	909	0	0
CheckPhase2_A	563095079	894	0	0
CheckPhase3_A	563095079	872	0	0
CheckTimeout0_A	563095079	556	0	0
CheckTimeoutSt1_A	563095079	69841	0	0
CheckTimeoutSt2_A	563095079	439	0	0
CheckTimeoutStTrig_A	563095079	70	0	0
ErrorStAllEscAsserted_A	563095079	1468	0	0
ErrorStIsTerminal_A	563095079	1198	0	0
EscStateOut_A	562811736	562741101	0	0
u_state_regs_A	563095079	562908982	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	254	0	0
T8	46343	43	0	0
T9	0	26	0	0
T10	0	42	0	0
T16	971102	0	0	0
T32	18827	0	0	0
T33	0	60	0	0
T34	0	83	0	0
T35	31205	0	0	0
T36	137110	0	0	0
T37	120699	0	0	0
T38	23152	0	0	0
T39	122218	0	0	0
T40	272350	0	0	0
T41	219909	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	842	0	0
T1	9701	1	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	1	0	0
T7	766632	0	0	0
T11	71285	1	0	0
T12	208429	1	0	0
T13	112328	1	0	0
T14	139961	0	0	0
T15	28370	2	0	0
T21	0	1	0	0
T26	0	2	0	0
T29	0	2	0	0
T42	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	41	0	0
T4	43244	0	0	0
T5	0	1	0	0
T7	766632	1	0	0
T12	208429	0	0	0
T13	112328	0	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T20	0	2	0	0
T21	38697	0	0	0
T24	0	1	0	0
T26	50242	0	0	0
T29	31456	0	0	0
T31	0	3	0	0
T42	16546	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T53	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	422	0	0
T4	43244	0	0	0
T5	0	7	0	0
T6	0	2	0	0
T7	766632	0	0	0
T11	71285	1	0	0
T12	208429	0	0	0
T13	112328	0	0	0
T14	139961	0	0	0
T15	28370	1	0	0
T20	0	6	0	0
T21	38697	0	0	0
T26	50242	1	0	0
T29	31456	1	0	0
T42	0	2	0	0
T49	0	1	0	0
T70	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562813369	225221411	0	0
T1	9701	2419	0	0
T2	916888	481777	0	0
T3	405569	115980	0	0
T4	43244	20420	0	0
T7	766632	595	0	0
T11	71285	64977	0	0
T12	208429	5541	0	0
T13	112328	1032	0	0
T14	139961	1874	0	0
T15	28370	1971	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	929	0	0
T1	9701	1	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	1	0	0
T7	766632	1	0	0
T11	71285	1	0	0
T12	208429	1	0	0
T13	112328	1	0	0
T14	139961	0	0	0
T15	28370	2	0	0
T21	0	1	0	0
T26	0	2	0	0
T29	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	909	0	0
T1	9701	1	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	1	0	0
T7	766632	1	0	0
T11	71285	1	0	0
T12	208429	1	0	0
T13	112328	1	0	0
T14	139961	0	0	0
T15	28370	2	0	0
T21	0	1	0	0
T26	0	2	0	0
T29	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	894	0	0
T1	9701	1	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	1	0	0
T7	766632	1	0	0
T11	71285	1	0	0
T12	208429	1	0	0
T13	112328	1	0	0
T14	139961	0	0	0
T15	28370	2	0	0
T21	0	1	0	0
T26	0	2	0	0
T29	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	872	0	0
T1	9701	1	0	0
T2	916888	0	0	0
T3	405569	0	0	0
T4	43244	1	0	0
T7	766632	1	0	0
T11	71285	1	0	0
T12	208429	1	0	0
T13	112328	1	0	0
T14	139961	0	0	0
T15	28370	2	0	0
T21	0	1	0	0
T26	0	1	0	0
T29	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	556	0	0
T4	43244	0	0	0
T5	0	5	0	0
T6	0	8	0	0
T7	766632	2	0	0
T11	71285	1	0	0
T12	208429	0	0	0
T13	112328	0	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T20	0	6	0	0
T21	38697	1	0	0
T23	0	5	0	0
T26	50242	0	0	0
T29	31456	0	0	0
T64	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	69841	0	0
T4	43244	0	0	0
T5	0	740	0	0
T6	0	1776	0	0
T7	766632	112	0	0
T11	71285	87	0	0
T12	208429	0	0	0
T13	112328	0	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T20	0	685	0	0
T21	38697	34	0	0
T23	0	384	0	0
T26	50242	0	0	0
T29	31456	0	0	0
T64	0	174	0	0
T73	0	50	0	0
T74	0	151	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	439	0	0
T4	43244	0	0	0
T5	0	3	0	0
T6	0	7	0	0
T7	766632	1	0	0
T11	71285	1	0	0
T12	208429	0	0	0
T13	112328	0	0	0
T14	139961	0	0	0
T15	28370	0	0	0
T20	0	4	0	0
T21	38697	1	0	0
T23	0	5	0	0
T26	50242	0	0	0
T29	31456	0	0	0
T64	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	70	0	0
T5	121297	1	0	0
T6	269451	0	0	0
T17	865757	0	0	0
T23	27354	0	0	0
T28	0	1	0	0
T43	150113	0	0	0
T44	2954	0	0	0
T45	4024	0	0	0
T46	24438	0	0	0
T50	0	2	0	0
T67	0	1	0	0
T73	10459	0	0	0
T74	4232	0	0	0
T76	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	1468	0	0
T8	46343	294	0	0
T9	0	178	0	0
T10	0	308	0	0
T16	971102	0	0	0
T32	18827	0	0	0
T33	0	346	0	0
T34	0	342	0	0
T35	31205	0	0	0
T36	137110	0	0	0
T37	120699	0	0	0
T38	23152	0	0	0
T39	122218	0	0	0
T40	272350	0	0	0
T41	219909	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	1198	0	0
T8	46343	234	0	0
T9	0	148	0	0
T10	0	248	0	0
T16	971102	0	0	0
T32	18827	0	0	0
T33	0	286	0	0
T34	0	282	0	0
T35	31205	0	0	0
T36	137110	0	0	0
T37	120699	0	0	0
T38	23152	0	0	0
T39	122218	0	0	0
T40	272350	0	0	0
T41	219909	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562811736	562741101	0	0
T1	9701	9628	0	0
T2	916888	916794	0	0
T3	405569	405494	0	0
T4	43244	43115	0	0
T7	766632	766572	0	0
T11	71285	71197	0	0
T12	208429	208422	0	0
T13	112328	112320	0	0
T14	139961	139951	0	0
T15	28370	28288	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563095079	562908982	0	0
T1	9701	9628	0	0
T2	916888	916794	0	0
T3	405569	405494	0	0
T4	43244	43115	0	0
T7	766632	766572	0	0
T11	71285	71197	0	0
T12	208429	208422	0	0
T13	112328	112320	0	0
T14	139961	139951	0	0
T15	28370	28288	0	0