Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T52,T196
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2096562348	13421	0	0
DisabledNoTrigBkwd_A	2096562348	697019	0	0
DisabledNoTrigFwd_A	2096562348	1085099904	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	13421	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	0	0	0
T7	410582	0	0	0
T11	23981	0	0	0
T12	1018	296	0	0
T13	67152	0	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	26725	0	0	0
T40	103170	0	0	0
T52	0	516	0	0
T85	29967	0	0	0
T86	91592	0	0	0
T113	127267	0	0	0
T114	11905	0	0	0
T115	214372	0	0	0
T196	2876	533	0	0
T197	0	960	0	0
T198	0	591	0	0
T199	0	184	0	0
T200	0	241	0	0
T201	0	893	0	0
T202	3684	333	0	0
T203	0	1416	0	0
T204	0	416	0	0
T205	0	583	0	0
T206	0	1323	0	0
T207	0	937	0	0
T208	0	1147	0	0
T209	0	373	0	0
T210	0	885	0	0
T211	0	637	0	0
T212	0	935	0	0
T213	0	222	0	0
T214	395012	0	0	0
T215	11747	0	0	0
T216	325476	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	697019	0	0
T1	478307	376	0	0
T2	119676	71	0	0
T3	250022	59	0	0
T4	361005	888	0	0
T5	34118	0	0	0
T6	146753	35	0	0
T7	1231746	4089	0	0
T11	47962	81	0	0
T12	2036	9	0	0
T13	201456	1	0	0
T14	608757	264	0	0
T15	120876	8	0	0
T16	53450	58	0	0
T21	293446	4725	0	0
T22	219928	7079	0	0
T23	182483	2498	0	0
T24	450482	4157	0	0
T25	0	1648	0	0
T26	0	2351	0	0
T34	321694	170	0	0
T37	12404	0	0	0
T52	2898	14	0	0
T53	0	45	0	0
T54	10517	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	1085099904	0	0
T1	1913228	1442928	0	0
T2	239352	184799	0	0
T3	500044	383404	0	0
T4	481340	400198	0	0
T7	1642328	857753	0	0
T11	95924	34060	0	0
T12	4072	2416	0	0
T13	268608	244624	0	0
T14	811676	411245	0	0
T15	161168	79365	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T196,T198,T199
1	1	Covered	T2,T3,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	524140587	3192	0	0
DisabledNoTrigBkwd_A	524140587	180607	0	0
DisabledNoTrigFwd_A	524140587	286338413	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	3192	0	0
T40	103170	0	0	0
T85	29967	0	0	0
T86	91592	0	0	0
T113	127267	0	0	0
T114	11905	0	0	0
T115	214372	0	0	0
T196	2876	533	0	0
T198	0	591	0	0
T199	0	184	0	0
T204	0	416	0	0
T205	0	583	0	0
T210	0	885	0	0
T214	395012	0	0	0
T215	11747	0	0	0
T216	325476	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	180607	0	0
T2	59838	71	0	0
T3	125011	59	0	0
T4	120335	8	0	0
T5	17059	0	0	0
T6	0	27	0	0
T7	410582	2676	0	0
T11	23981	81	0	0
T12	1018	0	0	0
T13	67152	0	0	0
T14	202919	123	0	0
T15	40292	7	0	0
T16	0	13	0	0
T22	0	1699	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	286338413	0	0
T1	478307	477751	0	0
T2	59838	5462	0	0
T3	125011	8563	0	0
T4	120335	116180	0	0
T7	410582	34593	0	0
T11	23981	3655	0	0
T12	1018	598	0	0
T13	67152	60825	0	0
T14	202919	582	0	0
T15	40292	3072	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T11
1	0	Covered	T1,T3,T13
1	1	Covered	T1,T12,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T52,T197
1	1	Covered	T1,T12,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T12,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	524140587	5845	0	0
DisabledNoTrigBkwd_A	524140587	185398	0	0
DisabledNoTrigFwd_A	524140587	252639619	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	5845	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	0	0	0
T7	410582	0	0	0
T11	23981	0	0	0
T12	1018	296	0	0
T13	67152	0	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	26725	0	0	0
T52	0	516	0	0
T197	0	960	0	0
T200	0	241	0	0
T206	0	1323	0	0
T207	0	937	0	0
T211	0	637	0	0
T212	0	935	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	185398	0	0
T1	478307	376	0	0
T2	59838	0	0	0
T3	125011	0	0	0
T4	120335	880	0	0
T6	0	2	0	0
T7	410582	0	0	0
T11	23981	0	0	0
T12	1018	9	0	0
T13	67152	0	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	0	9	0	0
T21	0	1725	0	0
T23	0	2121	0	0
T24	0	2106	0	0
T34	0	53	0	0
T52	0	14	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	252639619	0	0
T1	478307	8575	0	0
T2	59838	59779	0	0
T3	125011	124947	0	0
T4	120335	43634	0	0
T7	410582	410573	0	0
T11	23981	3870	0	0
T12	1018	602	0	0
T13	67152	67099	0	0
T14	202919	202864	0	0
T15	40292	3089	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T11,T13
1	0	Covered	T1,T3,T13
1	1	Covered	T13,T14,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T202,T203,T213
1	1	Covered	T13,T14,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T4,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T14,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	524140587	1971	0	0
DisabledNoTrigBkwd_A	524140587	190670	0	0
DisabledNoTrigFwd_A	524140587	266221124	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	1971	0	0
T108	307200	0	0	0
T125	41330	0	0	0
T202	3684	333	0	0
T203	0	1416	0	0
T213	0	222	0	0
T217	7795	0	0	0
T218	22209	0	0	0
T219	227449	0	0	0
T220	88066	0	0	0
T221	71719	0	0	0
T222	847267	0	0	0
T223	3395	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	190670	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	6	0	0
T7	410582	1413	0	0
T13	67152	1	0	0
T14	202919	141	0	0
T15	40292	1	0	0
T16	26725	0	0	0
T21	146723	1310	0	0
T22	109964	2853	0	0
T23	0	136	0	0
T26	0	2	0	0
T34	0	117	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	266221124	0	0
T1	478307	478301	0	0
T2	59838	59779	0	0
T3	125011	124947	0	0
T4	120335	120077	0	0
T7	410582	2014	0	0
T11	23981	2645	0	0
T12	1018	606	0	0
T13	67152	60820	0	0
T14	202919	4935	0	0
T15	40292	32995	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T5
1	0	Covered	T1,T3,T13
1	1	Covered	T13,T6,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T208,T209
1	1	Covered	T13,T6,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T13,T6,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T21,T22

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	524140587	2413	0	0
DisabledNoTrigBkwd_A	524140587	140344	0	0
DisabledNoTrigFwd_A	524140587	279900748	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	2413	0	0
T62	298947	0	0	0
T201	3780	893	0	0
T208	0	1147	0	0
T209	0	373	0	0
T224	7755	0	0	0
T225	667155	0	0	0
T226	116447	0	0	0
T227	341814	0	0	0
T228	18446	0	0	0
T229	93943	0	0	0
T230	322179	0	0	0
T231	13878	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	140344	0	0
T16	26725	36	0	0
T21	146723	1690	0	0
T22	109964	2527	0	0
T23	182483	241	0	0
T24	450482	2051	0	0
T25	0	1648	0	0
T26	0	2349	0	0
T27	25056	0	0	0
T30	0	107	0	0
T34	321694	0	0	0
T37	12404	0	0	0
T52	2898	0	0	0
T53	0	45	0	0
T54	10517	0	0	0
T97	0	2291	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	279900748	0	0
T1	478307	478301	0	0
T2	59838	59779	0	0
T3	125011	124947	0	0
T4	120335	120307	0	0
T7	410582	410573	0	0
T11	23981	23890	0	0
T12	1018	610	0	0
T13	67152	55880	0	0
T14	202919	202864	0	0
T15	40292	40209	0	0