Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T11
1	0	1	Covered	T1,T2,T12
1	1	0	Covered	T3,T11,T13
1	1	1	Covered	T13,T6,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T6,T16
0	1	Covered	T24,T27,T28
1	0	Covered	T16,T29,T30

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T6,T16
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T16,T29,T30

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T6,T16
1	0	Covered	T31
1	1	Covered	T24,T27,T28

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T13,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T3,T11,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T11,T14

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T2,T14,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T12,T14,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T12

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T13,T6,T16

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T13,T6,T16
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T2,T6,T22
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T6,T22,T29
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T23,T32,T33
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T34,T35,T36
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T11,T13
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T6,T37,T23
TimeoutSt->Phase0St	172	Covered	T16,T24,T27

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T6,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T24,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T6,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T37,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T22,T26
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T22,T38,T39
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T23,T33,T40
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T35,T36
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T11,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2096562348	756	0	0
CheckAccumTrig0_A	2096562348	2342	0	0
CheckAccumTrig1_A	2096562348	123	0	0
CheckClr_A	2096562348	1074	0	0
CheckEn_A	2095757600	829518483	0	0
CheckPhase0_A	2096562348	2594	0	0
CheckPhase1_A	2096562348	2542	0	0
CheckPhase2_A	2096562348	2487	0	0
CheckPhase3_A	2096562348	2444	0	0
CheckTimeout0_A	2096562348	4040	0	0
CheckTimeoutSt1_A	2096562348	446592	0	0
CheckTimeoutSt2_A	2096562348	3671	0	0
CheckTimeoutStTrig_A	2096562348	227	0	0
ErrorStAllEscAsserted_A	2096562348	4458	0	0
ErrorStIsTerminal_A	2096562348	3618	0	0
EscStateOut_A	2095749916	2095480772	0	0
u_state_regs_A	2096562348	2095934776	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	756	0	0
T8	202944	127	0	0
T9	0	101	0	0
T10	0	218	0	0
T41	0	107	0	0
T42	0	203	0	0
T43	286152	0	0	0
T44	1137012	0	0	0
T45	93164	0	0	0
T46	305364	0	0	0
T47	179736	0	0	0
T48	81308	0	0	0
T49	28192	0	0	0
T50	422776	0	0	0
T51	117416	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	2342	0	0
T1	478307	1	0	0
T2	119676	2	0	0
T3	250022	2	0	0
T4	361005	2	0	0
T5	34118	0	0	0
T6	146753	8	0	0
T7	1231746	4	0	0
T11	47962	2	0	0
T12	2036	1	0	0
T13	201456	1	0	0
T14	608757	2	0	0
T15	120876	2	0	0
T16	53450	2	0	0
T21	293446	5	0	0
T22	219928	6	0	0
T23	182483	14	0	0
T24	450482	6	0	0
T25	0	1	0	0
T26	0	2	0	0
T34	321694	2	0	0
T37	12404	0	0	0
T52	2898	1	0	0
T53	0	1	0	0
T54	10517	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	123	0	0
T16	26725	1	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T23	182483	0	0	0
T24	450482	0	0	0
T27	25056	0	0	0
T29	0	1	0	0
T30	263492	1	0	0
T32	484498	2	0	0
T33	941548	1	0	0
T34	321694	0	0	0
T37	12404	0	0	0
T52	2898	0	0	0
T54	10517	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	3	0	0
T68	0	1	0	0
T69	0	5	0	0
T70	0	1	0	0
T71	40634	0	0	0
T72	71425	0	0	0
T73	20666	0	0	0
T74	487455	0	0	0
T75	387022	0	0	0
T76	123524	0	0	0
T77	80573	0	0	0
T78	67660	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	1074	0	0
T2	59838	1	0	0
T3	125011	1	0	0
T4	240670	0	0	0
T5	34118	0	0	0
T6	146753	4	0	0
T7	821164	2	0	0
T11	23981	1	0	0
T12	1018	0	0	0
T13	134304	1	0	0
T14	405838	0	0	0
T15	80584	0	0	0
T21	293446	1	0	0
T22	219928	3	0	0
T23	182483	9	0	0
T24	450482	2	0	0
T25	107740	0	0	0
T26	0	5	0	0
T27	25056	0	0	0
T28	0	5	0	0
T29	0	4	0	0
T30	0	3	0	0
T33	0	1	0	0
T34	321694	2	0	0
T37	12404	0	0	0
T38	0	1	0	0
T52	2898	0	0	0
T54	10517	0	0	0
T55	0	3	0	0
T73	0	3	0	0
T74	0	1	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2095757600	829518483	0	0
T1	1913228	1442928	0	0
T2	239352	181381	0	0
T3	500044	383401	0	0
T4	481340	400194	0	0
T7	1642328	857753	0	0
T11	95924	34059	0	0
T12	4072	2416	0	0
T13	268608	228794	0	0
T14	811676	411243	0	0
T15	161168	61768	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	2594	0	0
T1	478307	1	0	0
T2	119676	1	0	0
T3	250022	2	0	0
T4	481340	2	0	0
T5	51177	0	0	0
T6	293506	7	0	0
T7	1642328	4	0	0
T11	47962	2	0	0
T12	2036	1	0	0
T13	268608	2	0	0
T14	811676	2	0	0
T15	161168	2	0	0
T16	53450	3	0	0
T21	293446	5	0	0
T22	219928	5	0	0
T23	0	11	0	0
T24	0	9	0	0
T25	0	1	0	0
T26	0	2	0	0
T28	0	1	0	0
T34	0	2	0	0
T52	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	2542	0	0
T1	478307	1	0	0
T2	119676	1	0	0
T3	250022	2	0	0
T4	361005	2	0	0
T5	34118	0	0	0
T6	146753	6	0	0
T7	1231746	4	0	0
T11	47962	2	0	0
T12	2036	1	0	0
T13	201456	1	0	0
T14	608757	2	0	0
T15	120876	2	0	0
T16	53450	3	0	0
T21	293446	5	0	0
T22	219928	4	0	0
T23	182483	11	0	0
T24	450482	9	0	0
T25	0	2	0	0
T26	0	2	0	0
T28	0	1	0	0
T34	321694	2	0	0
T37	12404	0	0	0
T52	2898	1	0	0
T54	10517	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	2487	0	0
T1	478307	1	0	0
T2	119676	1	0	0
T3	250022	2	0	0
T4	361005	2	0	0
T5	34118	0	0	0
T6	146753	6	0	0
T7	1231746	4	0	0
T11	47962	2	0	0
T12	2036	1	0	0
T13	201456	1	0	0
T14	608757	2	0	0
T15	120876	2	0	0
T16	53450	3	0	0
T21	293446	5	0	0
T22	219928	4	0	0
T23	182483	10	0	0
T24	450482	9	0	0
T25	0	2	0	0
T26	0	2	0	0
T28	0	1	0	0
T34	321694	2	0	0
T37	12404	0	0	0
T52	2898	1	0	0
T54	10517	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	2444	0	0
T1	478307	1	0	0
T2	119676	1	0	0
T3	250022	2	0	0
T4	361005	2	0	0
T5	34118	0	0	0
T6	146753	6	0	0
T7	1231746	4	0	0
T11	47962	2	0	0
T12	2036	1	0	0
T13	201456	1	0	0
T14	608757	2	0	0
T15	120876	2	0	0
T16	53450	3	0	0
T21	293446	5	0	0
T22	219928	4	0	0
T23	182483	10	0	0
T24	450482	9	0	0
T25	0	2	0	0
T26	0	2	0	0
T28	0	1	0	0
T34	321694	2	0	0
T37	12404	0	0	0
T52	2898	1	0	0
T54	10517	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	4040	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	587012	18	0	0
T7	410582	0	0	0
T13	67152	2	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	106900	1	0	0
T21	586892	0	0	0
T22	439856	0	0	0
T23	547449	3	0	0
T24	1351446	66	0	0
T27	0	10	0	0
T28	0	11	0	0
T29	0	15	0	0
T30	0	9	0	0
T32	0	2	0	0
T33	0	3	0	0
T34	965082	1	0	0
T37	37212	4	0	0
T52	8694	0	0	0
T54	31551	0	0	0
T55	0	4	0	0
T74	0	9	0	0
T78	0	2	0	0
T80	0	2	0	0
T81	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	446592	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	587012	1369	0	0
T7	410582	0	0	0
T13	67152	623	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	106900	4	0	0
T21	586892	0	0	0
T22	439856	0	0	0
T23	547449	158	0	0
T24	1351446	14110	0	0
T27	0	1166	0	0
T28	0	1188	0	0
T29	0	1271	0	0
T30	0	2075	0	0
T32	0	32	0	0
T33	0	88	0	0
T34	965082	131	0	0
T37	37212	228	0	0
T52	8694	0	0	0
T54	31551	0	0	0
T55	0	544	0	0
T74	0	1945	0	0
T78	0	314	0	0
T80	0	114	0	0
T81	0	984	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	3671	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	587012	17	0	0
T7	410582	0	0	0
T13	67152	0	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	106900	0	0	0
T21	586892	0	0	0
T22	439856	0	0	0
T23	547449	3	0	0
T24	1351446	36	0	0
T27	0	5	0	0
T28	0	3	0	0
T29	0	14	0	0
T30	0	1	0	0
T32	0	11	0	0
T33	0	2	0	0
T34	965082	1	0	0
T36	0	4	0	0
T37	37212	2	0	0
T38	0	1	0	0
T52	8694	0	0	0
T54	31551	0	0	0
T55	0	2	0	0
T74	0	7	0	0
T78	0	2	0	0
T80	0	1	0	0
T81	0	5	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	227	0	0
T4	120335	0	0	0
T13	67152	0	0	0
T14	202919	0	0	0
T17	273326	0	0	0
T18	255782	0	0	0
T24	450482	2	0	0
T25	215480	0	0	0
T26	215500	0	0	0
T27	50112	1	0	0
T28	50688	5	0	0
T29	338436	0	0	0
T30	263492	3	0	0
T34	321694	0	0	0
T36	0	1	0	0
T49	0	3	0	0
T53	342264	0	0	0
T55	0	3	0	0
T62	0	1	0	0
T63	0	2	0	0
T80	117645	1	0	0
T82	51285	0	0	0
T83	0	1	0	0
T85	0	1	0	0
T86	0	3	0	0
T87	0	3	0	0
T88	0	2	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	3	0	0
T93	0	3	0	0
T94	0	1	0	0
T95	202784	0	0	0
T96	173564	0	0	0
T97	529881	0	0	0
T98	104363	0	0	0
T99	248900	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	4458	0	0
T8	202944	637	0	0
T9	0	642	0	0
T10	0	1243	0	0
T41	0	644	0	0
T42	0	1292	0	0
T43	286152	0	0	0
T44	1137012	0	0	0
T45	93164	0	0	0
T46	305364	0	0	0
T47	179736	0	0	0
T48	81308	0	0	0
T49	28192	0	0	0
T50	422776	0	0	0
T51	117416	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	3618	0	0
T8	202944	517	0	0
T9	0	522	0	0
T10	0	1003	0	0
T41	0	524	0	0
T42	0	1052	0	0
T43	286152	0	0	0
T44	1137012	0	0	0
T45	93164	0	0	0
T46	305364	0	0	0
T47	179736	0	0	0
T48	81308	0	0	0
T49	28192	0	0	0
T50	422776	0	0	0
T51	117416	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2095749916	2095480772	0	0
T1	1913228	1913204	0	0
T2	239352	239116	0	0
T3	500044	499788	0	0
T4	481340	481228	0	0
T7	1642328	1642292	0	0
T11	95924	95560	0	0
T12	4072	3744	0	0
T13	268608	268396	0	0
T14	811676	811456	0	0
T15	161168	160836	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096562348	2095934776	0	0
T1	1913228	1913204	0	0
T2	239352	239116	0	0
T3	500044	499788	0	0
T4	481340	481228	0	0
T7	1642328	1642292	0	0
T11	95924	95560	0	0
T12	4072	3744	0	0
T13	268608	268396	0	0
T14	811676	811456	0	0
T15	161168	160836	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T11
1	0	1	Covered	T2,T14,T15
1	1	0	Covered	T11,T13,T6
1	1	1	Covered	T6,T16,T37

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T16,T37
0	1	Covered	T27,T30,T55
1	0	Covered	T16,T29,T32

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T16,T37
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T29,T32

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T16,T37
1	0	Not Covered
1	1	Covered	T27,T30,T55

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T7,T6,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T14
1	Covered	T3,T11,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T11,T14,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T11,T14
1	Covered	T2,T15,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T15,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T11,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T11
Phase1St	198	Covered	T2,T3,T11
Phase2St	215	Covered	T2,T3,T11
Phase3St	233	Covered	T2,T3,T11
TerminalSt	249	Covered	T2,T3,T11
TimeoutSt	159	Covered	T6,T16,T37

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T2,T3,T11
IdleSt->TimeoutSt	159	Covered	T6,T16,T37
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T2,T6,T22
Phase0St->Phase1St	198	Covered	T2,T3,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T22,T39,T36
Phase1St->Phase2St	215	Covered	T2,T3,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T40,T56
Phase2St->Phase3St	233	Covered	T2,T3,T11
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T34,T35,T59
Phase3St->TerminalSt	249	Covered	T2,T3,T11
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T11,T7
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T37,T23
TimeoutSt->Phase0St	172	Covered	T16,T27,T29

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T16,T37
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T27,T29
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T16,T37
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T37,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T22,T26
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T22,T39,T36
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T40,T56,T100
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T35,T59
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T11,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	524140587	199	0	0
CheckAccumTrig0_A	524140587	886	0	0
CheckAccumTrig1_A	524140587	48	0	0
CheckClr_A	524140587	452	0	0
CheckEn_A	523939400	220810685	0	0
CheckPhase0_A	524140587	962	0	0
CheckPhase1_A	524140587	940	0	0
CheckPhase2_A	524140587	915	0	0
CheckPhase3_A	524140587	897	0	0
CheckTimeout0_A	524140587	621	0	0
CheckTimeoutSt1_A	524140587	71116	0	0
CheckTimeoutSt2_A	524140587	501	0	0
CheckTimeoutStTrig_A	524140587	68	0	0
ErrorStAllEscAsserted_A	524140587	1157	0	0
ErrorStIsTerminal_A	524140587	947	0	0
EscStateOut_A	523937479	523870193	0	0
u_state_regs_A	524140587	523983694	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	199	0	0
T8	50736	33	0	0
T9	0	25	0	0
T10	0	54	0	0
T41	0	24	0	0
T42	0	63	0	0
T43	71538	0	0	0
T44	284253	0	0	0
T45	23291	0	0	0
T46	76341	0	0	0
T47	44934	0	0	0
T48	20327	0	0	0
T49	7048	0	0	0
T50	105694	0	0	0
T51	29354	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	886	0	0
T2	59838	2	0	0
T3	125011	2	0	0
T4	120335	1	0	0
T5	17059	0	0	0
T6	0	5	0	0
T7	410582	3	0	0
T11	23981	2	0	0
T12	1018	0	0	0
T13	67152	0	0	0
T14	202919	1	0	0
T15	40292	1	0	0
T22	0	4	0	0
T23	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	48	0	0
T16	26725	1	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T23	182483	0	0	0
T24	450482	0	0	0
T27	25056	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T34	321694	0	0	0
T37	12404	0	0	0
T52	2898	0	0	0
T54	10517	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T63	0	2	0	0
T65	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	5	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	452	0	0
T2	59838	1	0	0
T3	125011	1	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	0	3	0	0
T7	410582	2	0	0
T11	23981	1	0	0
T12	1018	0	0	0
T13	67152	0	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T22	0	3	0	0
T23	0	1	0	0
T26	0	3	0	0
T29	0	4	0	0
T34	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523939400	220810685	0	0
T1	478307	477751	0	0
T2	59838	2047	0	0
T3	125011	8563	0	0
T4	120335	116179	0	0
T7	410582	34593	0	0
T11	23981	3655	0	0
T12	1018	598	0	0
T13	67152	60824	0	0
T14	202919	582	0	0
T15	40292	3072	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	962	0	0
T2	59838	1	0	0
T3	125011	2	0	0
T4	120335	1	0	0
T5	17059	0	0	0
T6	0	4	0	0
T7	410582	3	0	0
T11	23981	2	0	0
T12	1018	0	0	0
T13	67152	0	0	0
T14	202919	1	0	0
T15	40292	1	0	0
T16	0	1	0	0
T22	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	940	0	0
T2	59838	1	0	0
T3	125011	2	0	0
T4	120335	1	0	0
T5	17059	0	0	0
T6	0	4	0	0
T7	410582	3	0	0
T11	23981	2	0	0
T12	1018	0	0	0
T13	67152	0	0	0
T14	202919	1	0	0
T15	40292	1	0	0
T16	0	1	0	0
T22	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	915	0	0
T2	59838	1	0	0
T3	125011	2	0	0
T4	120335	1	0	0
T5	17059	0	0	0
T6	0	4	0	0
T7	410582	3	0	0
T11	23981	2	0	0
T12	1018	0	0	0
T13	67152	0	0	0
T14	202919	1	0	0
T15	40292	1	0	0
T16	0	1	0	0
T22	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	897	0	0
T2	59838	1	0	0
T3	125011	2	0	0
T4	120335	1	0	0
T5	17059	0	0	0
T6	0	4	0	0
T7	410582	3	0	0
T11	23981	2	0	0
T12	1018	0	0	0
T13	67152	0	0	0
T14	202919	1	0	0
T15	40292	1	0	0
T16	0	1	0	0
T22	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	621	0	0
T6	146753	10	0	0
T16	26725	1	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T23	182483	3	0	0
T24	450482	21	0	0
T27	0	1	0	0
T28	0	3	0	0
T29	0	15	0	0
T30	0	2	0	0
T34	321694	1	0	0
T37	12404	1	0	0
T52	2898	0	0	0
T54	10517	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	71116	0	0
T6	146753	696	0	0
T16	26725	4	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T23	182483	158	0	0
T24	450482	4201	0	0
T27	0	77	0	0
T28	0	510	0	0
T29	0	1271	0	0
T30	0	376	0	0
T34	321694	131	0	0
T37	12404	55	0	0
T52	2898	0	0	0
T54	10517	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	501	0	0
T6	146753	10	0	0
T16	26725	0	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T23	182483	3	0	0
T24	450482	21	0	0
T28	0	3	0	0
T29	0	14	0	0
T32	0	10	0	0
T33	0	1	0	0
T34	321694	1	0	0
T37	12404	1	0	0
T52	2898	0	0	0
T54	10517	0	0	0
T82	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	68	0	0
T17	136663	0	0	0
T25	107740	0	0	0
T26	107750	0	0	0
T27	25056	1	0	0
T28	25344	0	0	0
T29	169218	0	0	0
T30	0	2	0	0
T36	0	1	0	0
T49	0	1	0	0
T53	114088	0	0	0
T55	0	2	0	0
T80	39215	0	0	0
T83	0	1	0	0
T85	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T95	101392	0	0	0
T96	86782	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	1157	0	0
T8	50736	170	0	0
T9	0	167	0	0
T10	0	318	0	0
T41	0	166	0	0
T42	0	336	0	0
T43	71538	0	0	0
T44	284253	0	0	0
T45	23291	0	0	0
T46	76341	0	0	0
T47	44934	0	0	0
T48	20327	0	0	0
T49	7048	0	0	0
T50	105694	0	0	0
T51	29354	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	947	0	0
T8	50736	140	0	0
T9	0	137	0	0
T10	0	258	0	0
T41	0	136	0	0
T42	0	276	0	0
T43	71538	0	0	0
T44	284253	0	0	0
T45	23291	0	0	0
T46	76341	0	0	0
T47	44934	0	0	0
T48	20327	0	0	0
T49	7048	0	0	0
T50	105694	0	0	0
T51	29354	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523937479	523870193	0	0
T1	478307	478301	0	0
T2	59838	59779	0	0
T3	125011	124947	0	0
T4	120335	120307	0	0
T7	410582	410573	0	0
T11	23981	23890	0	0
T12	1018	936	0	0
T13	67152	67099	0	0
T14	202919	202864	0	0
T15	40292	40209	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	523983694	0	0
T1	478307	478301	0	0
T2	59838	59779	0	0
T3	125011	124947	0	0
T4	120335	120307	0	0
T7	410582	410573	0	0
T11	23981	23890	0	0
T12	1018	936	0	0
T13	67152	67099	0	0
T14	202919	202864	0	0
T15	40292	40209	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T13,T14,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T14,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T11,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T13,T14,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T13,T15
1	0	1	Covered	T14,T6,T21
1	1	0	Covered	T13,T15,T6
1	1	1	Covered	T6,T37,T24

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T37,T24
0	1	Covered	T80,T55,T86
1	0	Covered	T30,T55,T58

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T37,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T30,T55,T58

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T24
1	0	Not Covered
1	1	Covered	T80,T55,T86

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T14,T15,T7
1	Covered	T13,T6,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T13,T14,T7
1	Covered	T15,T95,T32

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T7,T6,T22

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T15,T7
1	Covered	T14,T99,T32

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T14,T7,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T13,T14,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T14,T6,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T13,T14,T15
Phase1St	198	Covered	T13,T14,T15
Phase2St	215	Covered	T13,T14,T15
Phase3St	233	Covered	T13,T14,T15
TerminalSt	249	Covered	T13,T14,T15
TimeoutSt	159	Covered	T6,T37,T24

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T13,T14,T15
IdleSt->TimeoutSt	159	Covered	T6,T37,T24
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T74,T88,T61
Phase0St->Phase1St	198	Covered	T13,T14,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T38,T61
Phase1St->Phase2St	215	Covered	T13,T14,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T101,T102,T64
Phase2St->Phase3St	233	Covered	T13,T14,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T103,T104,T105
Phase3St->TerminalSt	249	Covered	T13,T14,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T13,T6,T23
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T37,T24
TimeoutSt->Phase0St	172	Covered	T80,T30,T55

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T37,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T80,T30,T55
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T37,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T37,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T88,T106,T105
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T13,T14,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T13,T14,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T38,T106,T107
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T13,T14,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T13,T14,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T101,T102,T64
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T13,T14,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T13,T14,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T103,T104,T105
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T13,T14,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T13,T14,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T6,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T13,T14,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	524140587	169	0	0
CheckAccumTrig0_A	524140587	489	0	0
CheckAccumTrig1_A	524140587	18	0	0
CheckClr_A	524140587	207	0	0
CheckEn_A	523939400	190642306	0	0
CheckPhase0_A	524140587	545	0	0
CheckPhase1_A	524140587	534	0	0
CheckPhase2_A	524140587	525	0	0
CheckPhase3_A	524140587	518	0	0
CheckTimeout0_A	524140587	1094	0	0
CheckTimeoutSt1_A	524140587	121236	0	0
CheckTimeoutSt2_A	524140587	1011	0	0
CheckTimeoutStTrig_A	524140587	58	0	0
ErrorStAllEscAsserted_A	524140587	1065	0	0
ErrorStIsTerminal_A	524140587	855	0	0
EscStateOut_A	523937479	523870193	0	0
u_state_regs_A	524140587	523983694	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	169	0	0
T8	50736	30	0	0
T9	0	32	0	0
T10	0	42	0	0
T41	0	25	0	0
T42	0	40	0	0
T43	71538	0	0	0
T44	284253	0	0	0
T45	23291	0	0	0
T46	76341	0	0	0
T47	44934	0	0	0
T48	20327	0	0	0
T49	7048	0	0	0
T50	105694	0	0	0
T51	29354	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	489	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	2	0	0
T7	410582	1	0	0
T13	67152	1	0	0
T14	202919	1	0	0
T15	40292	1	0	0
T16	26725	0	0	0
T21	146723	1	0	0
T22	109964	1	0	0
T23	0	1	0	0
T26	0	1	0	0
T34	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	18	0	0
T18	255782	0	0	0
T19	498843	0	0	0
T30	263492	1	0	0
T32	242249	0	0	0
T55	0	1	0	0
T58	0	1	0	0
T61	0	1	0	0
T71	20317	0	0	0
T82	51285	0	0	0
T90	0	1	0	0
T93	0	1	0	0
T97	529881	0	0	0
T98	104363	0	0	0
T99	248900	0	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	108986	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	207	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	1	0	0
T7	410582	0	0	0
T13	67152	1	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	26725	0	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T26	0	1	0	0
T38	0	1	0	0
T55	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T86	0	4	0	0
T113	0	1	0	0
T114	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523939400	190642306	0	0
T1	478307	478301	0	0
T2	59838	59778	0	0
T3	125011	124946	0	0
T4	120335	120077	0	0
T7	410582	2014	0	0
T11	23981	2645	0	0
T12	1018	606	0	0
T13	67152	44993	0	0
T14	202919	4935	0	0
T15	40292	15399	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	545	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	2	0	0
T7	410582	1	0	0
T13	67152	1	0	0
T14	202919	1	0	0
T15	40292	1	0	0
T16	26725	0	0	0
T21	146723	1	0	0
T22	109964	1	0	0
T23	0	1	0	0
T26	0	1	0	0
T34	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	534	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	2	0	0
T7	410582	1	0	0
T13	67152	1	0	0
T14	202919	1	0	0
T15	40292	1	0	0
T16	26725	0	0	0
T21	146723	1	0	0
T22	109964	1	0	0
T23	0	1	0	0
T26	0	1	0	0
T34	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	525	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	2	0	0
T7	410582	1	0	0
T13	67152	1	0	0
T14	202919	1	0	0
T15	40292	1	0	0
T16	26725	0	0	0
T21	146723	1	0	0
T22	109964	1	0	0
T23	0	1	0	0
T26	0	1	0	0
T34	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	518	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	2	0	0
T7	410582	1	0	0
T13	67152	1	0	0
T14	202919	1	0	0
T15	40292	1	0	0
T16	26725	0	0	0
T21	146723	1	0	0
T22	109964	1	0	0
T23	0	1	0	0
T26	0	1	0	0
T34	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	1094	0	0
T6	146753	2	0	0
T16	26725	0	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T23	182483	0	0	0
T24	450482	15	0	0
T27	0	5	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	321694	0	0	0
T37	12404	1	0	0
T52	2898	0	0	0
T54	10517	0	0	0
T55	0	3	0	0
T74	0	3	0	0
T80	0	2	0	0
T81	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	121236	0	0
T6	146753	200	0	0
T16	26725	0	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T23	182483	0	0	0
T24	450482	3212	0	0
T27	0	500	0	0
T30	0	11	0	0
T32	0	19	0	0
T34	321694	0	0	0
T37	12404	64	0	0
T52	2898	0	0	0
T54	10517	0	0	0
T55	0	318	0	0
T74	0	845	0	0
T80	0	114	0	0
T81	0	346	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	1011	0	0
T6	146753	2	0	0
T16	26725	0	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T23	182483	0	0	0
T24	450482	15	0	0
T27	0	5	0	0
T32	0	1	0	0
T34	321694	0	0	0
T37	12404	1	0	0
T38	0	1	0	0
T52	2898	0	0	0
T54	10517	0	0	0
T55	0	1	0	0
T74	0	3	0	0
T80	0	1	0	0
T81	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	58	0	0
T18	255782	0	0	0
T29	169218	0	0	0
T30	263492	0	0	0
T53	114088	0	0	0
T55	0	1	0	0
T63	0	1	0	0
T80	39215	1	0	0
T82	51285	0	0	0
T86	0	3	0	0
T87	0	1	0	0
T88	0	1	0	0
T90	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	1	0	0
T96	86782	0	0	0
T97	529881	0	0	0
T98	104363	0	0	0
T99	248900	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	1065	0	0
T8	50736	147	0	0
T9	0	156	0	0
T10	0	292	0	0
T41	0	157	0	0
T42	0	313	0	0
T43	71538	0	0	0
T44	284253	0	0	0
T45	23291	0	0	0
T46	76341	0	0	0
T47	44934	0	0	0
T48	20327	0	0	0
T49	7048	0	0	0
T50	105694	0	0	0
T51	29354	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	855	0	0
T8	50736	117	0	0
T9	0	126	0	0
T10	0	232	0	0
T41	0	127	0	0
T42	0	253	0	0
T43	71538	0	0	0
T44	284253	0	0	0
T45	23291	0	0	0
T46	76341	0	0	0
T47	44934	0	0	0
T48	20327	0	0	0
T49	7048	0	0	0
T50	105694	0	0	0
T51	29354	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523937479	523870193	0	0
T1	478307	478301	0	0
T2	59838	59779	0	0
T3	125011	124947	0	0
T4	120335	120307	0	0
T7	410582	410573	0	0
T11	23981	23890	0	0
T12	1018	936	0	0
T13	67152	67099	0	0
T14	202919	202864	0	0
T15	40292	40209	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	523983694	0	0
T1	478307	478301	0	0
T2	59838	59779	0	0
T3	125011	124947	0	0
T4	120335	120307	0	0
T7	410582	410573	0	0
T11	23981	23890	0	0
T12	1018	936	0	0
T13	67152	67099	0	0
T14	202919	202864	0	0
T15	40292	40209	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T13,T6,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T13,T6,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T6,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T13,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T21,T22

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T6,T16
1	0	1	Covered	T6,T22,T23
1	1	0	Covered	T3,T13,T6
1	1	1	Covered	T13,T6,T37

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T6,T37
0	1	Covered	T13,T24,T28
1	0	Covered	T30,T74,T59

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T13,T6,T37
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T30,T74,T59

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T6,T37
1	0	Not Covered
1	1	Covered	T13,T24,T28

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T13,T16,T21
1	Covered	T21,T23,T24

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T16,T21,T22
1	Covered	T13,T24,T25

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T16,T24,T26

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T16,T21,T23
1	Covered	T21,T22,T24

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T16,T21,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T13,T21,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T13,T21,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T21,T22,T23

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T13,T16,T21
Phase1St	198	Covered	T13,T16,T21
Phase2St	215	Covered	T16,T21,T22
Phase3St	233	Covered	T16,T21,T22
TerminalSt	249	Covered	T16,T21,T22
TimeoutSt	159	Covered	T13,T6,T37

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T16,T21,T22
IdleSt->TimeoutSt	159	Covered	T13,T6,T37
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T74,T115,T40
Phase0St->Phase1St	198	Covered	T13,T16,T21
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T13,T116,T117
Phase1St->Phase2St	215	Covered	T16,T21,T22
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T40,T118,T87
Phase2St->Phase3St	233	Covered	T16,T21,T22
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T55,T59,T119
Phase3St->TerminalSt	249	Covered	T16,T21,T22
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T21,T23,T24
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T6,T37
TimeoutSt->Phase0St	172	Covered	T13,T24,T28

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T21,T22
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T6,T37
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T24,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T6,T37
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T6,T37
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T115,T40,T119
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T13,T16,T21
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T13,T16,T21
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T13,T116,T117
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T16,T21,T22
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T13,T16,T21
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T40,T118,T87
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T16,T21,T22
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T16,T21,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T55,T59,T119
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T16,T21,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T16,T21,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T21,T30,T112
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T16,T21,T22
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	524140587	193	0	0
CheckAccumTrig0_A	524140587	478	0	0
CheckAccumTrig1_A	524140587	25	0	0
CheckClr_A	524140587	215	0	0
CheckEn_A	523939400	230492208	0	0
CheckPhase0_A	524140587	532	0	0
CheckPhase1_A	524140587	523	0	0
CheckPhase2_A	524140587	511	0	0
CheckPhase3_A	524140587	503	0	0
CheckTimeout0_A	524140587	1345	0	0
CheckTimeoutSt1_A	524140587	140369	0	0
CheckTimeoutSt2_A	524140587	1270	0	0
CheckTimeoutStTrig_A	524140587	47	0	0
ErrorStAllEscAsserted_A	524140587	1118	0	0
ErrorStIsTerminal_A	524140587	908	0	0
EscStateOut_A	523937479	523870193	0	0
u_state_regs_A	524140587	523983694	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	193	0	0
T8	50736	26	0	0
T9	0	16	0	0
T10	0	67	0	0
T41	0	29	0	0
T42	0	55	0	0
T43	71538	0	0	0
T44	284253	0	0	0
T45	23291	0	0	0
T46	76341	0	0	0
T47	44934	0	0	0
T48	20327	0	0	0
T49	7048	0	0	0
T50	105694	0	0	0
T51	29354	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	478	0	0
T16	26725	1	0	0
T21	146723	2	0	0
T22	109964	1	0	0
T23	182483	1	0	0
T24	450482	3	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	25056	0	0	0
T30	0	3	0	0
T34	321694	0	0	0
T37	12404	0	0	0
T52	2898	0	0	0
T53	0	1	0	0
T54	10517	0	0	0
T97	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	25	0	0
T18	255782	0	0	0
T19	498843	0	0	0
T30	263492	1	0	0
T32	242249	0	0	0
T59	0	1	0	0
T61	0	2	0	0
T63	0	1	0	0
T67	0	1	0	0
T71	20317	0	0	0
T74	0	1	0	0
T82	51285	0	0	0
T97	529881	0	0	0
T98	104363	0	0	0
T99	248900	0	0	0
T112	108986	0	0	0
T120	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	215	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	0	0	0
T7	410582	0	0	0
T13	67152	1	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	26725	0	0	0
T21	146723	1	0	0
T22	109964	0	0	0
T30	0	4	0	0
T33	0	1	0	0
T40	0	4	0	0
T55	0	17	0	0
T74	0	3	0	0
T112	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523939400	230492208	0	0
T1	478307	478301	0	0
T2	59838	59778	0	0
T3	125011	124946	0	0
T4	120335	120306	0	0
T7	410582	410573	0	0
T11	23981	23889	0	0
T12	1018	610	0	0
T13	67152	55879	0	0
T14	202919	202863	0	0
T15	40292	40208	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	532	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	0	0	0
T7	410582	0	0	0
T13	67152	1	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	26725	1	0	0
T21	146723	2	0	0
T22	109964	1	0	0
T23	0	1	0	0
T24	0	4	0	0
T25	0	1	0	0
T26	0	1	0	0
T28	0	1	0	0
T53	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	523	0	0
T16	26725	1	0	0
T21	146723	2	0	0
T22	109964	1	0	0
T23	182483	1	0	0
T24	450482	4	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	25056	0	0	0
T28	0	1	0	0
T30	0	6	0	0
T34	321694	0	0	0
T37	12404	0	0	0
T52	2898	0	0	0
T53	0	1	0	0
T54	10517	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	511	0	0
T16	26725	1	0	0
T21	146723	2	0	0
T22	109964	1	0	0
T23	182483	1	0	0
T24	450482	4	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	25056	0	0	0
T28	0	1	0	0
T30	0	6	0	0
T34	321694	0	0	0
T37	12404	0	0	0
T52	2898	0	0	0
T53	0	1	0	0
T54	10517	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	503	0	0
T16	26725	1	0	0
T21	146723	2	0	0
T22	109964	1	0	0
T23	182483	1	0	0
T24	450482	4	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	25056	0	0	0
T28	0	1	0	0
T30	0	6	0	0
T34	321694	0	0	0
T37	12404	0	0	0
T52	2898	0	0	0
T53	0	1	0	0
T54	10517	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	1345	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	1	0	0
T7	410582	0	0	0
T13	67152	2	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	26725	0	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T24	0	28	0	0
T27	0	4	0	0
T28	0	3	0	0
T30	0	4	0	0
T33	0	1	0	0
T37	0	2	0	0
T74	0	1	0	0
T81	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	140369	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	74	0	0
T7	410582	0	0	0
T13	67152	623	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	26725	0	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T24	0	6522	0	0
T27	0	589	0	0
T28	0	310	0	0
T30	0	904	0	0
T33	0	45	0	0
T37	0	109	0	0
T74	0	4	0	0
T81	0	195	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	1270	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	1	0	0
T7	410582	0	0	0
T13	67152	1	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	26725	0	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T24	0	27	0	0
T27	0	4	0	0
T28	0	2	0	0
T30	0	1	0	0
T33	0	1	0	0
T37	0	2	0	0
T55	0	5	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	47	0	0
T4	120335	0	0	0
T5	17059	0	0	0
T6	146753	0	0	0
T7	410582	0	0	0
T13	67152	1	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	26725	0	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T24	0	1	0	0
T28	0	1	0	0
T30	0	2	0	0
T36	0	4	0	0
T86	0	1	0	0
T87	0	3	0	0
T90	0	1	0	0
T120	0	1	0	0
T124	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	1118	0	0
T8	50736	171	0	0
T9	0	159	0	0
T10	0	317	0	0
T41	0	159	0	0
T42	0	312	0	0
T43	71538	0	0	0
T44	284253	0	0	0
T45	23291	0	0	0
T46	76341	0	0	0
T47	44934	0	0	0
T48	20327	0	0	0
T49	7048	0	0	0
T50	105694	0	0	0
T51	29354	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	908	0	0
T8	50736	141	0	0
T9	0	129	0	0
T10	0	257	0	0
T41	0	129	0	0
T42	0	252	0	0
T43	71538	0	0	0
T44	284253	0	0	0
T45	23291	0	0	0
T46	76341	0	0	0
T47	44934	0	0	0
T48	20327	0	0	0
T49	7048	0	0	0
T50	105694	0	0	0
T51	29354	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523937479	523870193	0	0
T1	478307	478301	0	0
T2	59838	59779	0	0
T3	125011	124947	0	0
T4	120335	120307	0	0
T7	410582	410573	0	0
T11	23981	23890	0	0
T12	1018	936	0	0
T13	67152	67099	0	0
T14	202919	202864	0	0
T15	40292	40209	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	523983694	0	0
T1	478307	478301	0	0
T2	59838	59779	0	0
T3	125011	124947	0	0
T4	120335	120307	0	0
T7	410582	410573	0	0
T11	23981	23890	0	0
T12	1018	936	0	0
T13	67152	67099	0	0
T14	202919	202864	0	0
T15	40292	40209	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T12,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T12,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T12,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T12,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T6,T16
1	0	1	Covered	T1,T12,T4
1	1	0	Covered	T13,T6,T37
1	1	1	Covered	T6,T24,T28

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T24,T28
0	1	Covered	T24,T28,T30
1	0	Covered	T32,T33,T56

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T24,T28
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T32,T33,T56

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T24,T28
1	0	Covered	T31
1	1	Covered	T24,T28,T30

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T23
1	Covered	T12,T6,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T12,T6
1	Covered	T4,T23,T24

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T4,T16
1	Covered	T1,T23,T28

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T12,T4
1	Covered	T24,T30,T32

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T12,T4,T52

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T12,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T12,T6,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T12,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T12,T4
Phase1St	198	Covered	T1,T12,T4
Phase2St	215	Covered	T1,T12,T4
Phase3St	233	Covered	T1,T12,T4
TerminalSt	249	Covered	T1,T12,T4
TimeoutSt	159	Covered	T6,T24,T28

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T12,T4
IdleSt->TimeoutSt	159	Covered	T6,T24,T28
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T26,T29,T32
Phase0St->Phase1St	198	Covered	T1,T12,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T6,T61,T125
Phase1St->Phase2St	215	Covered	T1,T12,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T23,T33,T106
Phase2St->Phase3St	233	Covered	T1,T12,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T36,T106,T66
Phase3St->TerminalSt	249	Covered	T1,T12,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T21,T23
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T30,T74
TimeoutSt->Phase0St	172	Covered	T24,T28,T30

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T24,T28
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T24,T28,T30
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T24,T28
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T30,T74
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T49,T88
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T12,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T61,T125,T126
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T12,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T23,T33,T126
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T12,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T16,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T36,T106,T66
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T12,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T21,T23,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T12,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	524140587	195	0	0
CheckAccumTrig0_A	524140587	489	0	0
CheckAccumTrig1_A	524140587	32	0	0
CheckClr_A	524140587	200	0	0
CheckEn_A	523939400	187573284	0	0
CheckPhase0_A	524140587	555	0	0
CheckPhase1_A	524140587	545	0	0
CheckPhase2_A	524140587	536	0	0
CheckPhase3_A	524140587	526	0	0
CheckTimeout0_A	524140587	980	0	0
CheckTimeoutSt1_A	524140587	113871	0	0
CheckTimeoutSt2_A	524140587	889	0	0
CheckTimeoutStTrig_A	524140587	54	0	0
ErrorStAllEscAsserted_A	524140587	1118	0	0
ErrorStIsTerminal_A	524140587	908	0	0
EscStateOut_A	523937479	523870193	0	0
u_state_regs_A	524140587	523983694	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	195	0	0
T8	50736	38	0	0
T9	0	28	0	0
T10	0	55	0	0
T41	0	29	0	0
T42	0	45	0	0
T43	71538	0	0	0
T44	284253	0	0	0
T45	23291	0	0	0
T46	76341	0	0	0
T47	44934	0	0	0
T48	20327	0	0	0
T49	7048	0	0	0
T50	105694	0	0	0
T51	29354	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	489	0	0
T1	478307	1	0	0
T2	59838	0	0	0
T3	125011	0	0	0
T4	120335	1	0	0
T6	0	1	0	0
T7	410582	0	0	0
T11	23981	0	0	0
T12	1018	1	0	0
T13	67152	0	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	0	1	0	0
T21	0	2	0	0
T23	0	9	0	0
T24	0	3	0	0
T34	0	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	32	0	0
T32	242249	1	0	0
T33	941548	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T66	0	2	0	0
T67	0	2	0	0
T70	0	1	0	0
T71	20317	0	0	0
T72	71425	0	0	0
T73	20666	0	0	0
T74	487455	0	0	0
T75	387022	0	0	0
T76	123524	0	0	0
T77	80573	0	0	0
T78	67660	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	200	0	0
T21	146723	1	0	0
T22	109964	0	0	0
T23	182483	8	0	0
T24	450482	2	0	0
T25	107740	0	0	0
T26	0	1	0	0
T27	25056	0	0	0
T28	0	5	0	0
T30	0	3	0	0
T33	0	1	0	0
T34	321694	0	0	0
T37	12404	0	0	0
T52	2898	0	0	0
T54	10517	0	0	0
T55	0	1	0	0
T73	0	1	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523939400	187573284	0	0
T1	478307	8575	0	0
T2	59838	59778	0	0
T3	125011	124946	0	0
T4	120335	43632	0	0
T7	410582	410573	0	0
T11	23981	3870	0	0
T12	1018	602	0	0
T13	67152	67098	0	0
T14	202919	202863	0	0
T15	40292	3089	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	555	0	0
T1	478307	1	0	0
T2	59838	0	0	0
T3	125011	0	0	0
T4	120335	1	0	0
T6	0	1	0	0
T7	410582	0	0	0
T11	23981	0	0	0
T12	1018	1	0	0
T13	67152	0	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	0	1	0	0
T21	0	2	0	0
T23	0	9	0	0
T24	0	5	0	0
T34	0	1	0	0
T52	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	545	0	0
T1	478307	1	0	0
T2	59838	0	0	0
T3	125011	0	0	0
T4	120335	1	0	0
T7	410582	0	0	0
T11	23981	0	0	0
T12	1018	1	0	0
T13	67152	0	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	0	1	0	0
T21	0	2	0	0
T23	0	9	0	0
T24	0	5	0	0
T25	0	1	0	0
T34	0	1	0	0
T52	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	536	0	0
T1	478307	1	0	0
T2	59838	0	0	0
T3	125011	0	0	0
T4	120335	1	0	0
T7	410582	0	0	0
T11	23981	0	0	0
T12	1018	1	0	0
T13	67152	0	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	0	1	0	0
T21	0	2	0	0
T23	0	8	0	0
T24	0	5	0	0
T25	0	1	0	0
T34	0	1	0	0
T52	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	526	0	0
T1	478307	1	0	0
T2	59838	0	0	0
T3	125011	0	0	0
T4	120335	1	0	0
T7	410582	0	0	0
T11	23981	0	0	0
T12	1018	1	0	0
T13	67152	0	0	0
T14	202919	0	0	0
T15	40292	0	0	0
T16	0	1	0	0
T21	0	2	0	0
T23	0	8	0	0
T24	0	5	0	0
T25	0	1	0	0
T34	0	1	0	0
T52	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	980	0	0
T6	146753	5	0	0
T16	26725	0	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T23	182483	0	0	0
T24	450482	2	0	0
T28	0	5	0	0
T30	0	2	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	321694	0	0	0
T37	12404	0	0	0
T52	2898	0	0	0
T54	10517	0	0	0
T55	0	1	0	0
T74	0	5	0	0
T78	0	2	0	0
T81	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	113871	0	0
T6	146753	399	0	0
T16	26725	0	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T23	182483	0	0	0
T24	450482	175	0	0
T28	0	368	0	0
T30	0	784	0	0
T32	0	13	0	0
T33	0	43	0	0
T34	321694	0	0	0
T37	12404	0	0	0
T52	2898	0	0	0
T54	10517	0	0	0
T55	0	226	0	0
T74	0	1096	0	0
T78	0	314	0	0
T81	0	443	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	889	0	0
T6	146753	5	0	0
T16	26725	0	0	0
T21	146723	0	0	0
T22	109964	0	0	0
T23	182483	0	0	0
T24	450482	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	321694	0	0	0
T36	0	4	0	0
T37	12404	0	0	0
T52	2898	0	0	0
T54	10517	0	0	0
T55	0	1	0	0
T74	0	4	0	0
T78	0	2	0	0
T81	0	3	0	0
T83	0	1	0	0
T84	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	54	0	0
T17	136663	0	0	0
T24	450482	2	0	0
T25	107740	0	0	0
T26	107750	0	0	0
T27	25056	0	0	0
T28	25344	5	0	0
T30	0	1	0	0
T34	321694	0	0	0
T49	0	2	0	0
T53	114088	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T80	39215	0	0	0
T87	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	2	0	0
T95	101392	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	1118	0	0
T8	50736	149	0	0
T9	0	160	0	0
T10	0	316	0	0
T41	0	162	0	0
T42	0	331	0	0
T43	71538	0	0	0
T44	284253	0	0	0
T45	23291	0	0	0
T46	76341	0	0	0
T47	44934	0	0	0
T48	20327	0	0	0
T49	7048	0	0	0
T50	105694	0	0	0
T51	29354	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	908	0	0
T8	50736	119	0	0
T9	0	130	0	0
T10	0	256	0	0
T41	0	132	0	0
T42	0	271	0	0
T43	71538	0	0	0
T44	284253	0	0	0
T45	23291	0	0	0
T46	76341	0	0	0
T47	44934	0	0	0
T48	20327	0	0	0
T49	7048	0	0	0
T50	105694	0	0	0
T51	29354	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523937479	523870193	0	0
T1	478307	478301	0	0
T2	59838	59779	0	0
T3	125011	124947	0	0
T4	120335	120307	0	0
T7	410582	410573	0	0
T11	23981	23890	0	0
T12	1018	936	0	0
T13	67152	67099	0	0
T14	202919	202864	0	0
T15	40292	40209	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524140587	523983694	0	0
T1	478307	478301	0	0
T2	59838	59779	0	0
T3	125011	124947	0	0
T4	120335	120307	0	0
T7	410582	410573	0	0
T11	23981	23890	0	0
T12	1018	936	0	0
T13	67152	67099	0	0
T14	202919	202864	0	0
T15	40292	40209	0	0