Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	51535	1			T61	1		T86	4		T23	2
class_i[0x1]	35450	1			T17	6		T55	53		T61	172
class_i[0x2]	32190	1			T15	386		T55	8		T61	23
class_i[0x3]	37428	1			T15	139		T55	716		T61	159

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	40712	1			T15	41		T55	17		T61	105
alert[0x1]	38577	1			T15	27		T17	6		T55	17
alert[0x2]	39546	1			T15	48		T55	731		T61	10
alert[0x3]	37768	1			T15	409		T55	12		T61	216

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

156289

1

T15

525

T17

6

T55

777

esc_ping_fail

314

1

T22

1

T23

5

T24

4

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	40623	1			T15	41		T55	17		T61	105
esc_integrity_fail	alert[0x1]	38501	1			T15	27		T17	6		T55	17
esc_integrity_fail	alert[0x2]	39463	1			T15	48		T55	731		T61	10
esc_integrity_fail	alert[0x3]	37702	1			T15	409		T55	12		T61	216
esc_ping_fail	alert[0x0]	89	1			T22	1		T23	2		T24	1
esc_ping_fail	alert[0x1]	76	1			T23	1		T24	2		T84	2
esc_ping_fail	alert[0x2]	83	1			T24	1		T84	2		T318	3
esc_ping_fail	alert[0x3]	66	1			T23	2		T84	1		T318	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	51443	1			T61	1		T86	4		T56	903
esc_integrity_fail	class_i[0x1]	35398	1			T17	6		T55	53		T61	172
esc_integrity_fail	class_i[0x2]	32082	1			T15	386		T55	8		T61	23
esc_integrity_fail	class_i[0x3]	37366	1			T15	139		T55	716		T61	159
esc_ping_fail	class_i[0x0]	92	1			T23	2		T84	6		T244	1
esc_ping_fail	class_i[0x1]	52	1			T23	1		T318	8		T319	11
esc_ping_fail	class_i[0x2]	108	1			T23	2		T24	4		T318	1
esc_ping_fail	class_i[0x3]	62	1			T22	1		T274	10		T320	3