Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	556159680	0	0	623
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	556159680	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	556159680	555976364	0	0
tb.dut.CheckAccuCntDw	0	0	623	623	0	0
tb.dut.CheckEscCntDw	0	0	623	623	0	0
tb.dut.CheckNAlerts	0	0	623	623	0	0
tb.dut.CheckNClasses	0	0	623	623	0	0
tb.dut.CheckNEscSev	0	0	623	623	0	0
tb.dut.CrashdumpKnownO_A	0	0	556159680	555976364	0	0
tb.dut.EdnKnownO_A	0	0	556159680	555976364	0	0
tb.dut.EscPKnownO_A	0	0	556159680	555976364	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	556159680	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	556159680	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	556159680	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	556159680	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	556159680	90	0	0
tb.dut.IrqAKnownO_A	0	0	556159680	555976364	0	0
tb.dut.IrqBKnownO_A	0	0	556159680	555976364	0	0
tb.dut.IrqCKnownO_A	0	0	556159680	555976364	0	0
tb.dut.IrqDKnownO_A	0	0	556159680	555976364	0	0
tb.dut.TlAReadyKnownO_A	0	0	556159680	555976364	0	0
tb.dut.TlDValidKnownO_A	0	0	556159680	555976364	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	579021932	225406	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	579021932	12172	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	579021932	11156	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	579021932	11197	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	579021932	11075	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	579021932	12057	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	579021932	11741	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	579021932	11196	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	579021932	11615	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	579021932	12253	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	579021932	11002	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	579021932	11225	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	579021932	11281	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	579021932	12562	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	579021932	11211	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	579021932	11041	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	579021932	11583	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	579021932	11136	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	579021932	11752	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	579021932	11283	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	579021932	11706	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	579021932	11802	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	579021932	11212	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	579021932	11053	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	579021932	11059	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	579021932	11750	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	579021932	11351	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	579021932	11590	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	579021932	11786	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	579021932	12433	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	579021932	11591	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	579021932	12030	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	579021932	12479	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	579021932	11300	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	579021932	11170	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	579021932	10922	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	579021932	11648	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	579021932	10875	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	579021932	11077	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	579021932	11741	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	579021932	12922	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	579021932	11151	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	579021932	11374	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	579021932	11962	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	579021932	12707	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	579021932	11024	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	579021932	12385	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	579021932	11264	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	579021932	10961	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	579021932	12454	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	579021932	11076	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	579021932	12865	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	579021932	12315	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	579021932	11813	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	579021932	10913	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	579021932	11026	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	579021932	11167	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	579021932	11142	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	579021932	11225	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	579021932	11130	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	579021932	12325	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	579021932	11092	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	579021932	10949	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	579021932	11118	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	579021932	10884	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	579021932	11111	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	579021932	12134	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	579021932	12371	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	579021932	12521	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	579021932	12010	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	579021932	22326	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	579021932	11063	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	579021932	11290	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	579021932	12373	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	579021932	11887	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	579021932	11453	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	579021932	11715	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	579021932	11938	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	579021932	11541	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	556159680	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	556159680	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	556159680	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	556159680	2214	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	556159680	186767	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	556159680	311744289	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	556159680	291	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	556159680	799	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	556159680	39	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	556159680	413	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	555884031	233775390	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	556159680	884	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	556159680	855	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	556159680	833	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	556159680	811	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	556159680	474	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	556159680	64305	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	556159680	366	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	556159680	65	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	556159680	1463	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	556159680	1193	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	555881378	555813301	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	556159680	555976364	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	556159680	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	556159680	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	556159680	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	556159680	1314	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	556159680	206712	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	556159680	285985471	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	556159680	252	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	556159680	469	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	556159680	22	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	556159680	211	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	555884031	232791736	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	556159680	527	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	556159680	509	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	556159680	500	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	556159680	498	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	556159680	481	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	556159680	67253	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	556159680	407	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	556159680	48	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	556159680	1426	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	556159680	1156	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	555881378	555813301	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	556159680	555976364	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	556159680	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	556159680	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	556159680	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	556159680	5807	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	556159680	154049	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	556159680	326619377	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	556159680	305	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	556159680	464	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	556159680	31	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	556159680	242	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	555884031	268682201	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	556159680	548	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	556159680	538	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	556159680	525	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	556159680	511	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	556159680	553	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	556159680	77573	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	556159680	457	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	556159680	64	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	556159680	1468	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	556159680	1198	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	555881378	555813301	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	556159680	555976364	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	556159680	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	556159680	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	556159680	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	556159680	4887	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	556159680	119221	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	556159680	332217373	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	556159680	229	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	556159680	436	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	556159680	20	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	556159680	182	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	555884031	269562556	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	556159680	498	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	556159680	482	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	556159680	473	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	556159680	464	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	556159680	487	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	556159680	65719	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	556159680	409	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	556159680	55	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	556159680	1480	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	556159680	1210	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	555881378	555813301	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	556159680	555976364	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	579021932	81831565	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	579021932	578294481	0	0
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tb.dut.tlul_assert_device.dKnown_A	0	0	579021932	142568005	0	0
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tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	828	828	0	0
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tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	828	828	0	0

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