Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	156	1			T15	1		T39	1		T61	1
index[0x1]	166	1			T62	2		T90	1		T80	1
index[0x2]	148	1			T54	2		T39	2		T49	1
index[0x3]	143	1			T45	1		T16	1		T47	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	197	1			T15	1		T16	1		T39	3
lens_less_than_1000[1]	120	1			T55	1		T61	1		T65	1
lens_less_than_1000[2]	86	1			T54	2		T90	1		T269	1
lens_less_than_1000[3]	61	1			T47	1		T40	3		T238	1
lens_less_than_1000[4]	53	1			T90	1		T91	1		T68	1
lens_less_than_1000[5]	46	1			T45	1		T62	2		T90	1
lens_less_than_1000[6]	21	1			T95	1		T44	1		T99	1
lens_less_than_1000[7]	11	1			T80	1		T98	1		T115	1
lens_less_than_1000[8]	5	1			T86	1		T37	1		T270	1
lens_less_than_1000[9]	3	1			T83	1		T271	1		T272	1
len_2	10	1			T63	1		T44	2		T273	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x1]]	[lens_less_than_1000[9]]	0	1	1
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	48	1			T15	1		T39	1		T61	1
index[0x0]	lens_less_than_1000[1]	29	1			T68	1		T85	2		T274	1
index[0x0]	lens_less_than_1000[2]	24	1			T90	1		T269	1		T44	1
index[0x0]	lens_less_than_1000[3]	19	1			T275	1		T276	1		T277	1
index[0x0]	lens_less_than_1000[4]	15	1			T115	1		T73	1		T127	1
index[0x0]	lens_less_than_1000[5]	10	1			T99	1		T100	1		T278	1
index[0x0]	lens_less_than_1000[6]	3	1			T114	1		T279	1		T124	1
index[0x0]	lens_less_than_1000[7]	2	1			T98	1		T115	1		-	-
index[0x0]	lens_less_than_1000[8]	1	1			T37	1		-	-		-	-
index[0x0]	lens_less_than_1000[9]	2	1			T83	1		T271	1		-	-
index[0x0]	len_2	3	1			T44	2		T280	1		-	-
index[0x1]	lens_less_than_1000[0]	49	1			T91	1		T44	1		T281	2
index[0x1]	lens_less_than_1000[1]	47	1			T94	4		T99	3		T140	1
index[0x1]	lens_less_than_1000[2]	20	1			T282	1		T98	1		T283	1
index[0x1]	lens_less_than_1000[3]	8	1			T40	1		T284	1		T107	1
index[0x1]	lens_less_than_1000[4]	14	1			T91	1		T37	3		T140	1
index[0x1]	lens_less_than_1000[5]	14	1			T62	2		T90	1		T56	1
index[0x1]	lens_less_than_1000[6]	7	1			T95	1		T252	1		T73	1
index[0x1]	lens_less_than_1000[7]	5	1			T80	1		T285	1		T124	1
index[0x1]	lens_less_than_1000[8]	1	1			T286	1		-	-		-	-
index[0x1]	len_2	1	1			T287	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	48	1			T39	2		T49	1		T61	1
index[0x2]	lens_less_than_1000[1]	22	1			T67	1		T99	1		T131	1
index[0x2]	lens_less_than_1000[2]	27	1			T54	2		T40	1		T35	1
index[0x2]	lens_less_than_1000[3]	17	1			T288	1		T275	1		T289	1
index[0x2]	lens_less_than_1000[4]	12	1			T85	1		T290	1		T263	2
index[0x2]	lens_less_than_1000[5]	7	1			T291	1		T292	1		T293	1
index[0x2]	lens_less_than_1000[6]	5	1			T99	1		T100	1		T294	1
index[0x2]	lens_less_than_1000[7]	2	1			T295	1		T264	1		-	-
index[0x2]	lens_less_than_1000[8]	2	1			T86	1		T286	1		-	-
index[0x2]	lens_less_than_1000[9]	1	1			T272	1		-	-		-	-
index[0x2]	len_2	5	1			T63	1		T273	1		T296	1
index[0x3]	lens_less_than_1000[0]	52	1			T16	1		T61	1		T65	1
index[0x3]	lens_less_than_1000[1]	22	1			T55	1		T61	1		T65	1
index[0x3]	lens_less_than_1000[2]	15	1			T244	1		T40	1		T297	1
index[0x3]	lens_less_than_1000[3]	17	1			T47	1		T40	2		T238	1
index[0x3]	lens_less_than_1000[4]	12	1			T90	1		T68	1		T115	1
index[0x3]	lens_less_than_1000[5]	15	1			T45	1		T298	1		T294	1
index[0x3]	lens_less_than_1000[6]	6	1			T44	1		T41	1		T252	1
index[0x3]	lens_less_than_1000[7]	2	1			T299	1		T295	1		-	-
index[0x3]	lens_less_than_1000[8]	1	1			T270	1		-	-		-	-
index[0x3]	len_2	1	1			T300	1		-	-		-	-