Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	65	1			T32	1		T49	1		T61	1
class_index[0x1]	48	1			T83	1		T67	1		T95	1
class_index[0x2]	65	1			T17	1		T90	1		T142	1
class_index[0x3]	55	1			T19	3		T61	1		T83	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	95	1			T32	1		T49	1		T61	1
intr_timeout_cnt[1]	49	1			T19	3		T79	1		T93	1
intr_timeout_cnt[2]	17	1			T90	1		T91	1		T69	2
intr_timeout_cnt[3]	17	1			T67	1		T44	2		T40	1
intr_timeout_cnt[4]	7	1			T139	1		T248	1		T249	1
intr_timeout_cnt[5]	13	1			T250	1		T251	1		T120	4
intr_timeout_cnt[6]	14	1			T140	2		T115	1		T252	1
intr_timeout_cnt[7]	9	1			T17	1		T44	1		T37	1
intr_timeout_cnt[8]	8	1			T61	1		T107	1		T253	1
intr_timeout_cnt[9]	4	1			T115	2		T254	1		T255	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	27	1			T32	1		T49	1		T89	1
class_index[0x0]	intr_timeout_cnt[1]	16	1			T79	1		T89	1		T94	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T91	1		T69	2		T117	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T115	1		T256	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	3	1			T248	1		T249	1		T257	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T250	1		T257	1		T111	1
class_index[0x0]	intr_timeout_cnt[6]	4	1			T140	2		T258	1		T130	1
class_index[0x0]	intr_timeout_cnt[7]	1	1			T259	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T61	1		T260	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	14	1			T83	1		T97	1		T99	1
class_index[0x1]	intr_timeout_cnt[1]	12	1			T95	1		T100	1		T71	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T224	1		T261	1		T52	2
class_index[0x1]	intr_timeout_cnt[3]	8	1			T67	1		T44	2		T40	1
class_index[0x1]	intr_timeout_cnt[5]	4	1			T251	1		T120	3		-	-
class_index[0x1]	intr_timeout_cnt[6]	3	1			T120	1		T257	1		T262	1
class_index[0x1]	intr_timeout_cnt[7]	3	1			T37	1		T262	1		T256	1
class_index[0x2]	intr_timeout_cnt[0]	28	1			T142	1		T44	2		T117	1
class_index[0x2]	intr_timeout_cnt[1]	10	1			T91	2		T95	1		T117	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T90	1		T140	1		T263	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T35	1		T222	1		T52	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T139	1		T251	1		T256	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T120	1		T264	1		T256	1
class_index[0x2]	intr_timeout_cnt[6]	6	1			T115	1		T127	1		T258	1
class_index[0x2]	intr_timeout_cnt[7]	3	1			T17	1		T44	1		T138	1
class_index[0x2]	intr_timeout_cnt[8]	4	1			T107	1		T120	1		T265	1
class_index[0x2]	intr_timeout_cnt[9]	2	1			T254	1		T255	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	26	1			T61	1		T83	1		T37	1
class_index[0x3]	intr_timeout_cnt[1]	11	1			T19	3		T93	1		T97	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T118	2		T110	1		T240	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T69	1		T120	1		T266	1
class_index[0x3]	intr_timeout_cnt[4]	1	1			T111	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	2	1			T265	2		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T252	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T267	2		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T253	1		T256	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T115	2		-	-		-	-