Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287117	1			T1	5		T2	11		T9	7
all_values[1]	287117	1			T1	5		T2	11		T9	7
all_values[2]	287117	1			T1	5		T2	11		T9	7
all_values[3]	287117	1			T1	5		T2	11		T9	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

570301

1

T1

11

T2

26

T9

7

auto[1]

578167

1

T1

9

T2

18

T9

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

689354

1

T1

12

T2

39

T9

26

auto[1]

459114

1

T1

8

T2

5

T9

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	83385	1			T1	2		T2	6		T20	5
all_values[0]	auto[0]	auto[1]	58468	1			T1	1		T2	5		T20	5
all_values[0]	auto[1]	auto[0]	85943	1			T1	1		T9	5		T20	3
all_values[0]	auto[1]	auto[1]	59321	1			T1	1		T9	2		T20	2
all_values[1]	auto[0]	auto[0]	85976	1			T1	3		T2	4		T20	1
all_values[1]	auto[0]	auto[1]	56518	1			T1	2		T20	1		T14	2
all_values[1]	auto[1]	auto[0]	87735	1			T2	7		T9	7		T20	7
all_values[1]	auto[1]	auto[1]	56888	1			T20	6		T14	3		T15	9
all_values[2]	auto[0]	auto[0]	86035	1			T1	2		T2	2		T9	3
all_values[2]	auto[0]	auto[1]	56880	1			T1	1		T20	3		T15	12
all_values[2]	auto[1]	auto[0]	87191	1			T1	1		T2	9		T9	4
all_values[2]	auto[1]	auto[1]	57011	1			T1	1		T20	4		T14	5
all_values[3]	auto[0]	auto[0]	85918	1			T2	9		T9	4		T20	5
all_values[3]	auto[0]	auto[1]	57121	1			T20	4		T14	3		T15	12
all_values[3]	auto[1]	auto[0]	87171	1			T1	3		T2	2		T9	3
all_values[3]	auto[1]	auto[1]	56907	1			T1	2		T20	3		T14	2