Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	287117	1			T1	5		T2	11		T9	7
all_pins[1]	287117	1			T1	5		T2	11		T9	7
all_pins[2]	287117	1			T1	5		T2	11		T9	7
all_pins[3]	287117	1			T1	5		T2	11		T9	7

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	918340	1			T1	16		T2	44		T9	26
values[0x1]	230128	1			T1	4		T9	2		T20	15
transitions[0x0=>0x1]	152964	1			T1	2		T9	1		T20	9
transitions[0x1=>0x0]	153210	1			T1	3		T9	2		T20	9

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	227796	1			T1	4		T2	11		T9	5
all_pins[0]	values[0x1]	59321	1			T1	1		T9	2		T20	2
all_pins[0]	transitions[0x0=>0x1]	58772	1			T9	1		T20	2		T21	5
all_pins[0]	transitions[0x1=>0x0]	56605	1			T1	2		T20	3		T14	2
all_pins[1]	values[0x0]	230229	1			T1	5		T2	11		T9	7
all_pins[1]	values[0x1]	56888	1			T20	6		T14	3		T15	9
all_pins[1]	transitions[0x0=>0x1]	31308	1			T20	5		T14	2		T15	4
all_pins[1]	transitions[0x1=>0x0]	33741	1			T1	1		T9	2		T20	1
all_pins[2]	values[0x0]	230106	1			T1	4		T2	11		T9	7
all_pins[2]	values[0x1]	57011	1			T1	1		T20	4		T14	5
all_pins[2]	transitions[0x0=>0x1]	31362	1			T1	1		T20	1		T14	2
all_pins[2]	transitions[0x1=>0x0]	31239	1			T20	3		T15	5		T48	3
all_pins[3]	values[0x0]	230209	1			T1	3		T2	11		T9	7
all_pins[3]	values[0x1]	56908	1			T1	2		T20	3		T14	2
all_pins[3]	transitions[0x0=>0x1]	31522	1			T1	1		T20	1		T15	3
all_pins[3]	transitions[0x1=>0x0]	31625	1			T20	2		T14	3		T15	3