Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	260	1			T178	7		T180	4		T235	7
all_values[1]	260	1			T178	7		T180	4		T235	7
all_values[2]	260	1			T178	7		T180	4		T235	7
all_values[3]	260	1			T178	7		T180	4		T235	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

599

1

T178

21

T180

8

T235

22

auto[1]

441

1

T178

7

T180

8

T235

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

431

1

T178

10

T180

8

T235

8

auto[1]

609

1

T178

18

T180

8

T235

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

626

1

T178

15

T180

10

T235

15

auto[1]

414

1

T178

13

T180

6

T235

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

66

1

T178

3

T235

2

T370

2

all_values[0]

auto[0]

auto[0]

auto[1]

26

1

T370

2

T371

2

T372

1

all_values[0]

auto[0]

auto[1]

auto[0]

46

1

T178

1

T180

1

T370

1

all_values[0]

auto[0]

auto[1]

auto[1]

21

1

T178

1

T235

2

T373

2

all_values[0]

auto[1]

auto[0]

auto[1]

63

1

T178

2

T180

1

T235

2

all_values[0]

auto[1]

auto[1]

auto[1]

38

1

T180

2

T235

1

T370

1

all_values[1]

auto[0]

auto[0]

auto[0]

61

1

T178

3

T235

1

T370

3

all_values[1]

auto[0]

auto[0]

auto[1]

27

1

T178

2

T180

1

T235

2

all_values[1]

auto[0]

auto[1]

auto[0]

48

1

T180

1

T370

2

T374

1

all_values[1]

auto[0]

auto[1]

auto[1]

27

1

T375

2

T376

1

T372

2

all_values[1]

auto[1]

auto[0]

auto[1]

58

1

T178

2

T180

1

T235

4

all_values[1]

auto[1]

auto[1]

auto[1]

39

1

T180

1

T373

1

T374

1

all_values[2]

auto[0]

auto[0]

auto[0]

66

1

T180

3

T235

2

T370

2

all_values[2]

auto[0]

auto[0]

auto[1]

23

1

T178

1

T235

1

T370

1

all_values[2]

auto[0]

auto[1]

auto[0]

37

1

T178

1

T180

1

T370

1

all_values[2]

auto[0]

auto[1]

auto[1]

27

1

T370

1

T373

2

T374

1

all_values[2]

auto[1]

auto[0]

auto[1]

70

1

T178

3

T235

4

T370

2

all_values[2]

auto[1]

auto[1]

auto[1]

37

1

T178

2

T375

1

T373

2

all_values[3]

auto[0]

auto[0]

auto[0]

68

1

T178

2

T180

1

T235

3

all_values[3]

auto[0]

auto[0]

auto[1]

19

1

T178

1

T180

1

T371

1

all_values[3]

auto[0]

auto[1]

auto[0]

39

1

T180

1

T370

1

T373

1

all_values[3]

auto[0]

auto[1]

auto[1]

25

1

T235

2

T370

1

T375

1

all_values[3]

auto[1]

auto[0]

auto[1]

52

1

T178

2

T235

1

T376

1

all_values[3]

auto[1]

auto[1]

auto[1]

57

1

T178

2

T180

1

T235

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal