Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	79629	1			T236	127		T310	539		T109	505
accum_cnt_1000	164916	1			T15	5		T53	1		T55	5
accum_cnt_100	18982	1			T15	11		T16	1		T53	19
accum_cnt_50	45238	1			T20	9		T21	4		T15	35
accum_cnt_10	159369	1			T1	3		T9	6		T20	17
accum_cnt_0	347320	1			T1	13		T2	36		T9	18

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	212747	1			T1	4		T2	9		T9	6
class_index[0x1]	212747	1			T1	4		T2	9		T9	6
class_index[0x2]	212747	1			T1	4		T2	9		T9	6
class_index[0x3]	212747	1			T1	4		T2	9		T9	6

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	18288	1			T236	83		T311	504		T312	489
class_index[0x0]	accum_cnt_1000	36347	1			T64	8		T135	8		T56	10
class_index[0x0]	accum_cnt_100	4525	1			T33	2		T64	17		T135	11
class_index[0x0]	accum_cnt_50	15848	1			T21	4		T15	17		T45	8
class_index[0x0]	accum_cnt_10	49012	1			T9	6		T20	5		T21	15
class_index[0x0]	accum_cnt_0	77909	1			T1	4		T2	9		T20	2
class_index[0x1]	accum_cnt_2000	22541	1			T310	198		T109	111		T311	539
class_index[0x1]	accum_cnt_1000	49288	1			T53	1		T61	14		T90	10
class_index[0x1]	accum_cnt_100	5306	1			T53	19		T64	10		T200	16
class_index[0x1]	accum_cnt_50	7608	1			T20	4		T15	10		T16	26
class_index[0x1]	accum_cnt_10	35212	1			T1	3		T20	3		T14	3
class_index[0x1]	accum_cnt_0	81423	1			T1	1		T2	9		T9	6
class_index[0x2]	accum_cnt_2000	21636	1			T236	44		T310	341		T313	125
class_index[0x2]	accum_cnt_1000	44561	1			T219	11		T314	47		T315	41
class_index[0x2]	accum_cnt_100	4429	1			T16	1		T65	2		T219	25
class_index[0x2]	accum_cnt_50	10897	1			T16	21		T55	6		T39	2
class_index[0x2]	accum_cnt_10	34642	1			T20	7		T14	4		T48	14
class_index[0x2]	accum_cnt_0	89415	1			T1	4		T2	9		T9	6
class_index[0x3]	accum_cnt_2000	17164	1			T109	394		T311	228		T316	329
class_index[0x3]	accum_cnt_1000	34720	1			T15	5		T55	5		T61	1
class_index[0x3]	accum_cnt_100	4722	1			T15	11		T219	19		T44	3
class_index[0x3]	accum_cnt_50	10885	1			T20	5		T15	8		T16	21
class_index[0x3]	accum_cnt_10	40503	1			T20	2		T14	2		T15	2
class_index[0x3]	accum_cnt_0	98573	1			T1	4		T2	9		T9	6