Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3370	1			T24	1		T317	1		T98	12
alert[0x1]	5817	1			T23	1		T44	2		T37	4
alert[0x2]	4304	1			T67	2		T318	1		T69	171
alert[0x3]	4097	1			T319	2		T69	38		T104	29
alert[0x4]	2200	1			T22	1		T84	1		T37	1
alert[0x5]	5234	1			T23	1		T244	2		T320	1
alert[0x6]	5762	1			T317	1		T320	1		T310	1
alert[0x7]	2987	1			T22	1		T84	2		T85	7
alert[0x8]	3131	1			T90	1		T85	1		T320	1
alert[0x9]	5617	1			T24	1		T68	1		T44	5
alert[0xa]	4231	1			T81	3		T22	1		T91	35
alert[0xb]	4312	1			T15	1		T67	1		T84	2
alert[0xc]	7662	1			T318	1		T138	4		T104	1369
alert[0xd]	9157	1			T24	1		T85	1		T274	1
alert[0xe]	6550	1			T91	1		T40	17		T319	1
alert[0xf]	2905	1			T44	20		T98	4		T236	7
alert[0x10]	7539	1			T24	1		T84	1		T85	1
alert[0x11]	4108	1			T22	1		T321	1		T322	1
alert[0x12]	16369	1			T44	30		T317	1		T319	1
alert[0x13]	7873	1			T84	1		T85	31		T319	2
alert[0x14]	7937	1			T79	3		T44	6		T40	1
alert[0x15]	7203	1			T90	1		T84	1		T104	39
alert[0x16]	1503	1			T67	4		T23	1		T56	6
alert[0x17]	4809	1			T129	1		T323	1		T140	1
alert[0x18]	4158	1			T67	3		T40	6		T37	6
alert[0x19]	2960	1			T44	6		T317	1		T98	28
alert[0x1a]	3096	1			T23	1		T91	4		T69	37
alert[0x1b]	3621	1			T69	37		T129	1		T324	5
alert[0x1c]	1294	1			T23	1		T44	1		T37	17
alert[0x1d]	3681	1			T91	2		T244	1		T318	1
alert[0x1e]	2873	1			T67	3		T282	7		T69	32
alert[0x1f]	3292	1			T44	8		T37	1		T319	1
alert[0x20]	2353	1			T23	1		T44	1		T85	4
alert[0x21]	9649	1			T317	1		T320	1		T98	1
alert[0x22]	10388	1			T318	1		T282	29		T99	2
alert[0x23]	2423	1			T86	1		T318	1		T105	1
alert[0x24]	4185	1			T67	12		T85	4		T319	1
alert[0x25]	2895	1			T23	1		T85	16		T317	1
alert[0x26]	5216	1			T15	15		T319	2		T69	204
alert[0x27]	4851	1			T24	1		T84	1		T69	3
alert[0x28]	1389	1			T86	2		T84	1		T69	3
alert[0x29]	1356	1			T24	1		T84	1		T44	43
alert[0x2a]	3262	1			T84	1		T318	2		T237	1
alert[0x2b]	1679	1			T237	9		T317	1		T274	1
alert[0x2c]	2944	1			T85	5		T325	1		T69	1
alert[0x2d]	5458	1			T237	1		T317	2		T274	1
alert[0x2e]	10237	1			T67	18		T91	31		T274	1
alert[0x2f]	3241	1			T37	6		T274	1		T129	1
alert[0x30]	4321	1			T17	2		T244	1		T318	1
alert[0x31]	3348	1			T56	1		T44	7		T37	4
alert[0x32]	6022	1			T40	3		T104	52		T129	2
alert[0x33]	8497	1			T44	5		T317	1		T319	1
alert[0x34]	9804	1			T37	11		T318	1		T325	1
alert[0x35]	9721	1			T325	1		T319	2		T98	6
alert[0x36]	7301	1			T67	4		T317	1		T69	1
alert[0x37]	12099	1			T85	2		T319	1		T98	2
alert[0x38]	6145	1			T44	52		T37	12		T69	2
alert[0x39]	4854	1			T86	1		T84	1		T44	2
alert[0x3a]	4087	1			T56	12		T85	1		T319	1
alert[0x3b]	3541	1			T317	1		T98	6		T99	1
alert[0x3c]	3484	1			T23	1		T44	48		T282	44
alert[0x3d]	9608	1			T68	2		T317	1		T98	1
alert[0x3e]	3827	1			T67	1		T237	38		T320	1
alert[0x3f]	8605	1			T44	11		T318	1		T325	1
alert[0x40]	3773	1			T318	1		T237	1		T317	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	152747	1			T86	2		T67	42		T22	1
class_i[0x1]	83028	1			T17	2		T79	3		T86	2
class_i[0x2]	83224	1			T15	16		T90	2		T22	2
class_i[0x3]	21216	1			T67	6		T81	3		T22	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

339528

1

T15

16

T17

2

T79

3

alert_ping_fail

687

1

T22

4

T23

8

T24

6

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3364	1			T98	12		T35	2		T278	93
alert_integrity_fail	alert[0x1]	5809	1			T44	2		T37	4		T104	1496
alert_integrity_fail	alert[0x2]	4295	1			T67	2		T69	171		T99	8
alert_integrity_fail	alert[0x3]	4084	1			T69	38		T104	29		T326	8
alert_integrity_fail	alert[0x4]	2190	1			T37	1		T236	8		T104	282
alert_integrity_fail	alert[0x5]	5217	1			T98	5		T104	4		T324	1
alert_integrity_fail	alert[0x6]	5744	1			T310	1		T104	21		T100	3
alert_integrity_fail	alert[0x7]	2974	1			T85	7		T237	4		T98	3
alert_integrity_fail	alert[0x8]	3115	1			T90	1		T85	1		T98	52
alert_integrity_fail	alert[0x9]	5611	1			T68	1		T44	5		T37	2
alert_integrity_fail	alert[0xa]	4217	1			T81	3		T91	35		T37	1
alert_integrity_fail	alert[0xb]	4306	1			T15	1		T67	1		T237	1
alert_integrity_fail	alert[0xc]	7655	1			T138	4		T104	1369		T313	17
alert_integrity_fail	alert[0xd]	9144	1			T85	1		T35	6		T129	9
alert_integrity_fail	alert[0xe]	6539	1			T91	1		T40	17		T104	14
alert_integrity_fail	alert[0xf]	2901	1			T44	20		T98	4		T236	7
alert_integrity_fail	alert[0x10]	7530	1			T85	1		T69	14		T99	22
alert_integrity_fail	alert[0x11]	4099	1			T100	51		T70	2		T115	209
alert_integrity_fail	alert[0x12]	16357	1			T44	30		T73	116		T327	3082
alert_integrity_fail	alert[0x13]	7858	1			T85	31		T69	2		T129	1
alert_integrity_fail	alert[0x14]	7917	1			T79	3		T44	6		T40	1
alert_integrity_fail	alert[0x15]	7195	1			T90	1		T104	39		T313	901
alert_integrity_fail	alert[0x16]	1489	1			T67	4		T56	6		T85	1
alert_integrity_fail	alert[0x17]	4800	1			T129	1		T140	1		T278	16
alert_integrity_fail	alert[0x18]	4150	1			T67	3		T40	6		T37	6
alert_integrity_fail	alert[0x19]	2950	1			T44	6		T98	28		T104	48
alert_integrity_fail	alert[0x1a]	3088	1			T91	4		T69	37		T98	1
alert_integrity_fail	alert[0x1b]	3616	1			T69	37		T129	1		T324	5
alert_integrity_fail	alert[0x1c]	1274	1			T44	1		T37	17		T69	2
alert_integrity_fail	alert[0x1d]	3666	1			T91	2		T282	4		T99	10
alert_integrity_fail	alert[0x1e]	2865	1			T67	3		T282	7		T69	32
alert_integrity_fail	alert[0x1f]	3279	1			T44	8		T37	1		T100	7
alert_integrity_fail	alert[0x20]	2343	1			T44	1		T85	4		T237	2
alert_integrity_fail	alert[0x21]	9639	1			T98	1		T313	2534		T70	148
alert_integrity_fail	alert[0x22]	10371	1			T282	29		T99	2		T100	9
alert_integrity_fail	alert[0x23]	2411	1			T86	1		T100	21		T140	42
alert_integrity_fail	alert[0x24]	4172	1			T67	12		T85	4		T98	126
alert_integrity_fail	alert[0x25]	2887	1			T85	16		T99	4		T104	205
alert_integrity_fail	alert[0x26]	5210	1			T15	15		T69	204		T99	1
alert_integrity_fail	alert[0x27]	4840	1			T69	3		T129	3		T278	1
alert_integrity_fail	alert[0x28]	1378	1			T86	2		T69	3		T98	15
alert_integrity_fail	alert[0x29]	1346	1			T44	43		T98	1		T104	4
alert_integrity_fail	alert[0x2a]	3252	1			T237	1		T69	1		T99	11
alert_integrity_fail	alert[0x2b]	1673	1			T237	9		T98	10		T104	3
alert_integrity_fail	alert[0x2c]	2932	1			T85	5		T69	1		T104	7
alert_integrity_fail	alert[0x2d]	5449	1			T237	1		T313	19		T100	1
alert_integrity_fail	alert[0x2e]	10224	1			T67	18		T91	31		T324	80
alert_integrity_fail	alert[0x2f]	3234	1			T37	6		T129	1		T100	2
alert_integrity_fail	alert[0x30]	4303	1			T17	2		T99	4		T129	1
alert_integrity_fail	alert[0x31]	3342	1			T56	1		T44	7		T37	4
alert_integrity_fail	alert[0x32]	6013	1			T40	3		T104	52		T129	2
alert_integrity_fail	alert[0x33]	8485	1			T44	5		T99	1		T129	4
alert_integrity_fail	alert[0x34]	9797	1			T37	11		T98	3		T138	1
alert_integrity_fail	alert[0x35]	9709	1			T98	6		T35	9		T104	76
alert_integrity_fail	alert[0x36]	7291	1			T67	4		T69	1		T99	1
alert_integrity_fail	alert[0x37]	12093	1			T85	2		T98	2		T310	5
alert_integrity_fail	alert[0x38]	6138	1			T44	52		T37	12		T69	2
alert_integrity_fail	alert[0x39]	4845	1			T86	1		T44	2		T310	3
alert_integrity_fail	alert[0x3a]	4077	1			T56	12		T85	1		T69	1
alert_integrity_fail	alert[0x3b]	3529	1			T98	6		T99	1		T129	10
alert_integrity_fail	alert[0x3c]	3469	1			T44	48		T282	44		T35	1
alert_integrity_fail	alert[0x3d]	9597	1			T68	2		T98	1		T104	14
alert_integrity_fail	alert[0x3e]	3818	1			T67	1		T237	38		T98	10
alert_integrity_fail	alert[0x3f]	8595	1			T44	11		T69	102		T324	1
alert_integrity_fail	alert[0x40]	3768	1			T237	1		T98	6		T104	53
alert_ping_fail	alert[0x0]	6	1			T24	1		T317	1		T328	1
alert_ping_fail	alert[0x1]	8	1			T23	1		T319	1		T329	1
alert_ping_fail	alert[0x2]	9	1			T318	1		T274	1		T105	1
alert_ping_fail	alert[0x3]	13	1			T319	2		T329	1		T323	2
alert_ping_fail	alert[0x4]	10	1			T22	1		T84	1		T318	2
alert_ping_fail	alert[0x5]	17	1			T23	1		T244	2		T320	1
alert_ping_fail	alert[0x6]	18	1			T317	1		T320	1		T322	1
alert_ping_fail	alert[0x7]	13	1			T22	1		T84	2		T274	1
alert_ping_fail	alert[0x8]	16	1			T320	1		T329	1		T105	1
alert_ping_fail	alert[0x9]	6	1			T24	1		T329	1		T105	1
alert_ping_fail	alert[0xa]	14	1			T22	1		T325	1		T329	1
alert_ping_fail	alert[0xb]	6	1			T84	2		T322	1		T330	1
alert_ping_fail	alert[0xc]	7	1			T318	1		T105	1		T328	1
alert_ping_fail	alert[0xd]	13	1			T24	1		T274	1		T329	1
alert_ping_fail	alert[0xe]	11	1			T319	1		T323	1		T331	1
alert_ping_fail	alert[0xf]	4	1			T332	1		T333	1		T334	1
alert_ping_fail	alert[0x10]	9	1			T24	1		T84	1		T325	1
alert_ping_fail	alert[0x11]	9	1			T22	1		T321	1		T322	1
alert_ping_fail	alert[0x12]	12	1			T317	1		T319	1		T274	1
alert_ping_fail	alert[0x13]	15	1			T84	1		T319	2		T335	1
alert_ping_fail	alert[0x14]	20	1			T319	1		T274	2		T304	1
alert_ping_fail	alert[0x15]	8	1			T84	1		T336	1		T337	1
alert_ping_fail	alert[0x16]	14	1			T23	1		T325	1		T317	1
alert_ping_fail	alert[0x17]	9	1			T323	1		T332	1		T338	2
alert_ping_fail	alert[0x18]	8	1			T318	1		T274	1		T320	1
alert_ping_fail	alert[0x19]	10	1			T317	1		T105	2		T337	1
alert_ping_fail	alert[0x1a]	8	1			T23	1		T105	1		T339	1
alert_ping_fail	alert[0x1b]	5	1			T323	1		T337	1		T340	1
alert_ping_fail	alert[0x1c]	20	1			T23	1		T317	1		T319	1
alert_ping_fail	alert[0x1d]	15	1			T244	1		T318	1		T320	1
alert_ping_fail	alert[0x1e]	8	1			T320	1		T335	1		T336	1
alert_ping_fail	alert[0x1f]	13	1			T319	1		T105	1		T339	1
alert_ping_fail	alert[0x20]	10	1			T23	1		T274	2		T320	1
alert_ping_fail	alert[0x21]	10	1			T317	1		T320	1		T336	1
alert_ping_fail	alert[0x22]	17	1			T318	1		T335	1		T304	2
alert_ping_fail	alert[0x23]	12	1			T318	1		T105	1		T335	1
alert_ping_fail	alert[0x24]	13	1			T319	1		T320	1		T105	1
alert_ping_fail	alert[0x25]	8	1			T23	1		T317	1		T319	1
alert_ping_fail	alert[0x26]	6	1			T319	2		T320	1		T341	1
alert_ping_fail	alert[0x27]	11	1			T24	1		T84	1		T322	1
alert_ping_fail	alert[0x28]	11	1			T84	1		T302	1		T306	1
alert_ping_fail	alert[0x29]	10	1			T24	1		T84	1		T317	1
alert_ping_fail	alert[0x2a]	10	1			T84	1		T318	2		T317	1
alert_ping_fail	alert[0x2b]	6	1			T317	1		T274	1		T342	1
alert_ping_fail	alert[0x2c]	12	1			T325	1		T320	1		T323	2
alert_ping_fail	alert[0x2d]	9	1			T317	2		T274	1		T322	1
alert_ping_fail	alert[0x2e]	13	1			T274	1		T321	1		T329	1
alert_ping_fail	alert[0x2f]	7	1			T274	1		T342	2		T343	1
alert_ping_fail	alert[0x30]	18	1			T244	1		T318	1		T274	1
alert_ping_fail	alert[0x31]	6	1			T317	1		T319	1		T274	1
alert_ping_fail	alert[0x32]	9	1			T329	1		T105	1		T331	1
alert_ping_fail	alert[0x33]	12	1			T317	1		T319	1		T320	1
alert_ping_fail	alert[0x34]	7	1			T318	1		T325	1		T274	1
alert_ping_fail	alert[0x35]	12	1			T325	1		T319	2		T335	1
alert_ping_fail	alert[0x36]	10	1			T317	1		T320	1		T335	1
alert_ping_fail	alert[0x37]	6	1			T319	1		T322	2		T323	1
alert_ping_fail	alert[0x38]	7	1			T274	1		T323	1		T336	1
alert_ping_fail	alert[0x39]	9	1			T84	1		T318	1		T322	1
alert_ping_fail	alert[0x3a]	10	1			T319	1		T329	1		T335	1
alert_ping_fail	alert[0x3b]	12	1			T317	1		T105	1		T331	2
alert_ping_fail	alert[0x3c]	15	1			T23	1		T320	1		T321	1
alert_ping_fail	alert[0x3d]	11	1			T317	1		T105	1		T335	1
alert_ping_fail	alert[0x3e]	9	1			T320	1		T321	1		T336	2
alert_ping_fail	alert[0x3f]	10	1			T318	1		T325	1		T320	1
alert_ping_fail	alert[0x40]	5	1			T318	1		T317	1		T105	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	152477	1			T86	2		T67	42		T56	12
alert_integrity_fail	class_i[0x1]	82948	1			T17	2		T79	3		T86	2
alert_integrity_fail	class_i[0x2]	83082	1			T15	16		T90	2		T91	2
alert_integrity_fail	class_i[0x3]	21021	1			T67	6		T81	3		T56	6
alert_ping_fail	class_i[0x0]	270	1			T22	1		T23	1		T24	1
alert_ping_fail	class_i[0x1]	80	1			T24	1		T84	1		T244	2
alert_ping_fail	class_i[0x2]	142	1			T22	2		T23	7		T24	4
alert_ping_fail	class_i[0x3]	195	1			T22	1		T84	12		T318	1