| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.24 | 99.99 | 98.66 | 97.06 | 100.00 | 100.00 | 99.38 | 99.56 |
| T781 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.1839068844 | Aug 21 04:44:47 PM UTC 24 | Aug 21 04:44:56 PM UTC 24 | 911271539 ps | ||
| T782 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1645221942 | Aug 21 04:43:57 PM UTC 24 | Aug 21 04:45:08 PM UTC 24 | 665945575 ps | ||
| T783 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3884554945 | Aug 21 04:44:39 PM UTC 24 | Aug 21 04:45:08 PM UTC 24 | 1360519172 ps | ||
| T161 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.16482859 | Aug 21 04:40:56 PM UTC 24 | Aug 21 04:45:11 PM UTC 24 | 1915076443 ps | ||
| T784 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3377919782 | Aug 21 04:44:59 PM UTC 24 | Aug 21 04:45:12 PM UTC 24 | 194578470 ps | ||
| T785 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.2467599209 | Aug 21 04:44:29 PM UTC 24 | Aug 21 04:45:13 PM UTC 24 | 859524294 ps | ||
| T786 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.269248887 | Aug 21 04:45:13 PM UTC 24 | Aug 21 04:45:17 PM UTC 24 | 18893038 ps | ||
| T787 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1204359216 | Aug 21 04:44:57 PM UTC 24 | Aug 21 04:45:17 PM UTC 24 | 362935129 ps | ||
| T788 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3840757743 | Aug 21 04:45:13 PM UTC 24 | Aug 21 04:45:19 PM UTC 24 | 163171669 ps | ||
| T789 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.2141805049 | Aug 21 04:45:12 PM UTC 24 | Aug 21 04:45:22 PM UTC 24 | 201695465 ps | ||
| T790 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.1073031364 | Aug 21 04:45:18 PM UTC 24 | Aug 21 04:45:24 PM UTC 24 | 82813450 ps | ||
| T791 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.690998400 | Aug 21 04:45:20 PM UTC 24 | Aug 21 04:45:30 PM UTC 24 | 304965934 ps | ||
| T152 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.267799801 | Aug 21 04:38:26 PM UTC 24 | Aug 21 04:45:36 PM UTC 24 | 24772356602 ps | ||
| T792 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.3422121195 | Aug 21 04:45:38 PM UTC 24 | Aug 21 04:45:41 PM UTC 24 | 7107730 ps | ||
| T793 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1962557730 | Aug 21 04:45:35 PM UTC 24 | Aug 21 04:45:41 PM UTC 24 | 36746226 ps | ||
| T162 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2230964116 | Aug 21 04:40:30 PM UTC 24 | Aug 21 04:45:43 PM UTC 24 | 4185733197 ps | ||
| T150 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3203294839 | Aug 21 04:40:27 PM UTC 24 | Aug 21 04:45:47 PM UTC 24 | 4335949634 ps | ||
| T794 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.3460978956 | Aug 21 04:45:42 PM UTC 24 | Aug 21 04:45:48 PM UTC 24 | 19890213 ps | ||
| T795 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.4055675984 | Aug 21 04:45:18 PM UTC 24 | Aug 21 04:45:51 PM UTC 24 | 747669316 ps | ||
| T796 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.3030498664 | Aug 21 04:45:49 PM UTC 24 | Aug 21 04:45:52 PM UTC 24 | 6562336 ps | ||
| T797 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.222647552 | Aug 21 04:45:49 PM UTC 24 | Aug 21 04:45:52 PM UTC 24 | 27746897 ps | ||
| T798 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.2053958446 | Aug 21 04:45:51 PM UTC 24 | Aug 21 04:45:54 PM UTC 24 | 7083658 ps | ||
| T799 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3019219267 | Aug 21 04:45:43 PM UTC 24 | Aug 21 04:45:55 PM UTC 24 | 74925206 ps | ||
| T800 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.603182542 | Aug 21 04:45:54 PM UTC 24 | Aug 21 04:45:57 PM UTC 24 | 22334212 ps | ||
| T801 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.2604732092 | Aug 21 04:45:54 PM UTC 24 | Aug 21 04:45:57 PM UTC 24 | 9673790 ps | ||
| T802 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.372896094 | Aug 21 04:45:55 PM UTC 24 | Aug 21 04:45:58 PM UTC 24 | 13903278 ps | ||
| T803 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.3055981736 | Aug 21 04:45:56 PM UTC 24 | Aug 21 04:45:59 PM UTC 24 | 11348109 ps | ||
| T804 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.2380698003 | Aug 21 04:45:57 PM UTC 24 | Aug 21 04:46:00 PM UTC 24 | 7865478 ps | ||
| T165 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.278458587 | Aug 21 04:42:38 PM UTC 24 | Aug 21 04:46:00 PM UTC 24 | 6040475348 ps | ||
| T805 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.144991773 | Aug 21 04:45:58 PM UTC 24 | Aug 21 04:46:01 PM UTC 24 | 18007068 ps | ||
| T806 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.2424479580 | Aug 21 04:45:58 PM UTC 24 | Aug 21 04:46:02 PM UTC 24 | 7742727 ps | ||
| T807 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.3623161838 | Aug 21 04:46:00 PM UTC 24 | Aug 21 04:46:02 PM UTC 24 | 9625280 ps | ||
| T808 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.207847561 | Aug 21 04:46:01 PM UTC 24 | Aug 21 04:46:04 PM UTC 24 | 7760200 ps | ||
| T809 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.341286327 | Aug 21 04:46:01 PM UTC 24 | Aug 21 04:46:04 PM UTC 24 | 27630446 ps | ||
| T810 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.3478174364 | Aug 21 04:46:02 PM UTC 24 | Aug 21 04:46:05 PM UTC 24 | 14992891 ps | ||
| T811 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.2055437513 | Aug 21 04:46:02 PM UTC 24 | Aug 21 04:46:05 PM UTC 24 | 9178875 ps | ||
| T812 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.238638556 | Aug 21 04:45:30 PM UTC 24 | Aug 21 04:46:06 PM UTC 24 | 4415707175 ps | ||
| T813 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.832309180 | Aug 21 04:46:03 PM UTC 24 | Aug 21 04:46:07 PM UTC 24 | 11862785 ps | ||
| T814 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.1401610985 | Aug 21 04:46:04 PM UTC 24 | Aug 21 04:46:08 PM UTC 24 | 20644918 ps | ||
| T815 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.667885666 | Aug 21 04:46:06 PM UTC 24 | Aug 21 04:46:09 PM UTC 24 | 10524977 ps | ||
| T816 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.769517716 | Aug 21 04:46:07 PM UTC 24 | Aug 21 04:46:10 PM UTC 24 | 18726519 ps | ||
| T817 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.3110074470 | Aug 21 04:46:07 PM UTC 24 | Aug 21 04:46:10 PM UTC 24 | 8615612 ps | ||
| T818 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.263432318 | Aug 21 04:46:07 PM UTC 24 | Aug 21 04:46:10 PM UTC 24 | 10987904 ps | ||
| T819 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.2190980817 | Aug 21 04:46:08 PM UTC 24 | Aug 21 04:46:11 PM UTC 24 | 13679618 ps | ||
| T820 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.3941760127 | Aug 21 04:46:08 PM UTC 24 | Aug 21 04:46:11 PM UTC 24 | 12728482 ps | ||
| T821 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1660598503 | Aug 21 04:45:42 PM UTC 24 | Aug 21 04:46:13 PM UTC 24 | 257118884 ps | ||
| T822 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.2749049334 | Aug 21 04:46:10 PM UTC 24 | Aug 21 04:46:14 PM UTC 24 | 76907103 ps | ||
| T823 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.966400467 | Aug 21 04:46:10 PM UTC 24 | Aug 21 04:46:14 PM UTC 24 | 8887935 ps | ||
| T824 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.2467446071 | Aug 21 04:46:12 PM UTC 24 | Aug 21 04:46:15 PM UTC 24 | 21572264 ps | ||
| T825 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.2691670995 | Aug 21 04:46:12 PM UTC 24 | Aug 21 04:46:15 PM UTC 24 | 9301424 ps | ||
| T826 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.1323644923 | Aug 21 04:46:12 PM UTC 24 | Aug 21 04:46:15 PM UTC 24 | 10637884 ps | ||
| T827 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.4009844580 | Aug 21 04:46:13 PM UTC 24 | Aug 21 04:46:17 PM UTC 24 | 15604736 ps | ||
| T828 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.2558485264 | Aug 21 04:46:14 PM UTC 24 | Aug 21 04:46:17 PM UTC 24 | 9804092 ps | ||
| T158 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1135564533 | Aug 21 04:43:18 PM UTC 24 | Aug 21 04:46:19 PM UTC 24 | 6815901846 ps | ||
| T159 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2067597325 | Aug 21 04:41:27 PM UTC 24 | Aug 21 04:46:46 PM UTC 24 | 48914028784 ps | ||
| T167 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1620399848 | Aug 21 04:42:56 PM UTC 24 | Aug 21 04:46:46 PM UTC 24 | 29805503552 ps | ||
| T151 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2031384649 | Aug 21 04:43:49 PM UTC 24 | Aug 21 04:46:59 PM UTC 24 | 1684259622 ps | ||
| T154 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1708965693 | Aug 21 04:34:10 PM UTC 24 | Aug 21 04:47:11 PM UTC 24 | 9377890404 ps | ||
| T157 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.546864637 | Aug 21 04:36:03 PM UTC 24 | Aug 21 04:47:24 PM UTC 24 | 12092442207 ps | ||
| T169 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.903768002 | Aug 21 04:44:26 PM UTC 24 | Aug 21 04:48:14 PM UTC 24 | 6107117928 ps | ||
| T155 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1720224844 | Aug 21 04:45:09 PM UTC 24 | Aug 21 04:48:48 PM UTC 24 | 26050700534 ps | ||
| T163 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3166618960 | Aug 21 04:42:24 PM UTC 24 | Aug 21 04:49:56 PM UTC 24 | 22751562635 ps | ||
| T168 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1527360265 | Aug 21 04:42:10 PM UTC 24 | Aug 21 04:49:59 PM UTC 24 | 11250665942 ps | ||
| T383 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.54330067 | Aug 21 04:45:09 PM UTC 24 | Aug 21 04:50:00 PM UTC 24 | 4815763861 ps | ||
| T170 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.549219838 | Aug 21 04:45:24 PM UTC 24 | Aug 21 04:50:10 PM UTC 24 | 3819658795 ps | ||
| T171 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2909445249 | Aug 21 04:44:03 PM UTC 24 | Aug 21 04:51:01 PM UTC 24 | 9247906815 ps | ||
| T384 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2520805558 | Aug 21 04:40:56 PM UTC 24 | Aug 21 04:52:03 PM UTC 24 | 18399422115 ps | ||
| T385 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2206701841 | Aug 21 04:41:49 PM UTC 24 | Aug 21 04:53:06 PM UTC 24 | 69454346043 ps | ||
| T387 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2892215239 | Aug 21 04:40:04 PM UTC 24 | Aug 21 04:53:36 PM UTC 24 | 4374899632 ps | ||
| T386 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.4000144244 | Aug 21 04:43:47 PM UTC 24 | Aug 21 04:54:37 PM UTC 24 | 7920346447 ps | ||
| T174 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3719724356 | Aug 21 04:44:01 PM UTC 24 | Aug 21 04:54:46 PM UTC 24 | 64140026905 ps | ||
| T156 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2058529257 | Aug 21 04:42:53 PM UTC 24 | Aug 21 04:56:03 PM UTC 24 | 4447908377 ps | ||
| T166 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2153813423 | Aug 21 04:45:23 PM UTC 24 | Aug 21 04:57:12 PM UTC 24 | 6228787988 ps | ||
| T173 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.123072491 | Aug 21 04:39:37 PM UTC 24 | Aug 21 04:57:17 PM UTC 24 | 50737170535 ps | ||
| T388 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4126797315 | Aug 21 04:41:16 PM UTC 24 | Aug 21 05:00:13 PM UTC 24 | 51424861061 ps | ||
| T389 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3445639886 | Aug 21 04:42:36 PM UTC 24 | Aug 21 05:01:05 PM UTC 24 | 223406067545 ps | ||
| T172 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3266282530 | Aug 21 04:44:23 PM UTC 24 | Aug 21 05:01:47 PM UTC 24 | 169516792985 ps | ||
| T390 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3431838588 | Aug 21 04:43:16 PM UTC 24 | Aug 21 05:02:21 PM UTC 24 | 15770948883 ps |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.1718328595 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 78806764 ps |
| CPU time | 7.66 seconds |
| Started | Aug 21 03:07:44 PM UTC 24 |
| Finished | Aug 21 03:07:53 PM UTC 24 |
| Peak memory | 268620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1718328595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1718328595 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.4022755546 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2140268585 ps |
| CPU time | 25.73 seconds |
| Started | Aug 21 03:07:55 PM UTC 24 |
| Finished | Aug 21 03:08:22 PM UTC 24 |
| Peak memory | 262996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4022755546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.4022755546 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.684111408 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1595477926 ps |
| CPU time | 19.42 seconds |
| Started | Aug 21 03:07:52 PM UTC 24 |
| Finished | Aug 21 03:08:12 PM UTC 24 |
| Peak memory | 295376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=684111408 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.684111408 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all_with_rand_reset.589410339 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3805117933 ps |
| CPU time | 292.41 seconds |
| Started | Aug 21 03:08:27 PM UTC 24 |
| Finished | Aug 21 03:13:24 PM UTC 24 |
| Peak memory | 285640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=589410339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.589410339 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.2933651508 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 372037988 ps |
| CPU time | 7.73 seconds |
| Started | Aug 21 03:07:45 PM UTC 24 |
| Finished | Aug 21 03:07:54 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2933651508 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2933651508 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.3859871096 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 652999208 ps |
| CPU time | 25.7 seconds |
| Started | Aug 21 03:08:04 PM UTC 24 |
| Finished | Aug 21 03:08:31 PM UTC 24 |
| Peak memory | 263056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3859871096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3859871096 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3003444656 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1749741986 ps |
| CPU time | 50.6 seconds |
| Started | Aug 21 04:32:48 PM UTC 24 |
| Finished | Aug 21 04:33:40 PM UTC 24 |
| Peak memory | 252572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3003444656 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_ intg_err.3003444656 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.1773742414 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 644458151 ps |
| CPU time | 17.18 seconds |
| Started | Aug 21 03:08:16 PM UTC 24 |
| Finished | Aug 21 03:08:34 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1773742414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1773742414 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.4148001861 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 144286292233 ps |
| CPU time | 762.63 seconds |
| Started | Aug 21 03:12:59 PM UTC 24 |
| Finished | Aug 21 03:25:50 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4148001861 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping _timeout.4148001861 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all_with_rand_reset.497180021 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 4535540895 ps |
| CPU time | 438.11 seconds |
| Started | Aug 21 03:26:38 PM UTC 24 |
| Finished | Aug 21 03:34:03 PM UTC 24 |
| Peak memory | 281620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=497180021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.497180021 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2230964116 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 4185733197 ps |
| CPU time | 307.21 seconds |
| Started | Aug 21 04:40:30 PM UTC 24 |
| Finished | Aug 21 04:45:43 PM UTC 24 |
| Peak memory | 279452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2230964116 -assert nopostpr oc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handl er_shadow_reg_errors.2230964116 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all_with_rand_reset.2278234787 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 15946046461 ps |
| CPU time | 246.99 seconds |
| Started | Aug 21 03:09:48 PM UTC 24 |
| Finished | Aug 21 03:13:59 PM UTC 24 |
| Peak memory | 279572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=2278234787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2278234787 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.1695589145 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 33934095147 ps |
| CPU time | 2088.2 seconds |
| Started | Aug 21 03:08:08 PM UTC 24 |
| Finished | Aug 21 03:43:20 PM UTC 24 |
| Peak memory | 288632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1695589145 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1695589145 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all_with_rand_reset.693599791 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 5618082734 ps |
| CPU time | 142.91 seconds |
| Started | Aug 21 03:07:51 PM UTC 24 |
| Finished | Aug 21 03:10:17 PM UTC 24 |
| Peak memory | 285688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=693599791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.693599791 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.421492698 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 3063090363 ps |
| CPU time | 319.11 seconds |
| Started | Aug 21 04:37:13 PM UTC 24 |
| Finished | Aug 21 04:42:37 PM UTC 24 |
| Peak memory | 285672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=421492698 -assert nopostpro c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handle r_shadow_reg_errors.421492698 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.10636991 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 631043998 ps |
| CPU time | 31.7 seconds |
| Started | Aug 21 03:07:44 PM UTC 24 |
| Finished | Aug 21 03:08:17 PM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10636991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.10636991 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2520805558 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 18399422115 ps |
| CPU time | 658.38 seconds |
| Started | Aug 21 04:40:56 PM UTC 24 |
| Finished | Aug 21 04:52:03 PM UTC 24 |
| Peak memory | 285600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=2520805558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2520805558 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3559977998 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 367054491 ps |
| CPU time | 64.42 seconds |
| Started | Aug 21 04:37:34 PM UTC 24 |
| Finished | Aug 21 04:38:40 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3559977998 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_ intg_err.3559977998 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all_with_rand_reset.767009564 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 28674012978 ps |
| CPU time | 357.02 seconds |
| Started | Aug 21 04:15:55 PM UTC 24 |
| Finished | Aug 21 04:21:57 PM UTC 24 |
| Peak memory | 283592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=767009564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.767009564 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.2120216947 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 44619512157 ps |
| CPU time | 512.27 seconds |
| Started | Aug 21 03:10:21 PM UTC 24 |
| Finished | Aug 21 03:18:59 PM UTC 24 |
| Peak memory | 263384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2120216947 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_ timeout.2120216947 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2031384649 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1684259622 ps |
| CPU time | 186.74 seconds |
| Started | Aug 21 04:43:49 PM UTC 24 |
| Finished | Aug 21 04:46:59 PM UTC 24 |
| Peak memory | 279460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2031384649 -assert nopostpr oc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_hand ler_shadow_reg_errors.2031384649 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.1417953075 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 74055719682 ps |
| CPU time | 1503.93 seconds |
| Started | Aug 21 03:12:55 PM UTC 24 |
| Finished | Aug 21 03:38:16 PM UTC 24 |
| Peak memory | 285848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1417953075 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1417953075 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.2419610137 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 67307631317 ps |
| CPU time | 2650.09 seconds |
| Started | Aug 21 03:18:35 PM UTC 24 |
| Finished | Aug 21 04:03:13 PM UTC 24 |
| Peak memory | 304696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2419610137 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2419610137 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.2616509743 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 53776518 ps |
| CPU time | 2.17 seconds |
| Started | Aug 21 04:38:05 PM UTC 24 |
| Finished | Aug 21 04:38:08 PM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2616509743 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2616509743 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.2757268962 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 64130925104 ps |
| CPU time | 1683.34 seconds |
| Started | Aug 21 03:07:49 PM UTC 24 |
| Finished | Aug 21 03:36:12 PM UTC 24 |
| Peak memory | 304944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27572 68962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.alert_handler_stress_all.2757268962 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3445639886 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 223406067545 ps |
| CPU time | 1095.89 seconds |
| Started | Aug 21 04:42:36 PM UTC 24 |
| Finished | Aug 21 05:01:05 PM UTC 24 |
| Peak memory | 285600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=3445639886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3445639886 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.3831085960 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 92271751655 ps |
| CPU time | 607.05 seconds |
| Started | Aug 21 03:08:19 PM UTC 24 |
| Finished | Aug 21 03:18:34 PM UTC 24 |
| Peak memory | 269208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3831085960 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_ timeout.3831085960 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.1848643309 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 89380718224 ps |
| CPU time | 2260.04 seconds |
| Started | Aug 21 03:08:01 PM UTC 24 |
| Finished | Aug 21 03:46:05 PM UTC 24 |
| Peak memory | 300132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1848643309 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1848643309 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.546864637 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 12092442207 ps |
| CPU time | 673.03 seconds |
| Started | Aug 21 04:36:03 PM UTC 24 |
| Finished | Aug 21 04:47:24 PM UTC 24 |
| Peak memory | 285592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=546864637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.546864637 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all_with_rand_reset.3050193694 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 22608955185 ps |
| CPU time | 222.82 seconds |
| Started | Aug 21 03:07:58 PM UTC 24 |
| Finished | Aug 21 03:11:44 PM UTC 24 |
| Peak memory | 281620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=3050193694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.3050193694 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.3740150777 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 27543545616 ps |
| CPU time | 598.74 seconds |
| Started | Aug 21 03:08:51 PM UTC 24 |
| Finished | Aug 21 03:18:57 PM UTC 24 |
| Peak memory | 269132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3740150777 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_ timeout.3740150777 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1135564533 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 6815901846 ps |
| CPU time | 177.96 seconds |
| Started | Aug 21 04:43:18 PM UTC 24 |
| Finished | Aug 21 04:46:19 PM UTC 24 |
| Peak memory | 285596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1135564533 -assert nopostpr oc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_hand ler_shadow_reg_errors.1135564533 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.1320181932 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 30289415220 ps |
| CPU time | 1314.94 seconds |
| Started | Aug 21 03:13:02 PM UTC 24 |
| Finished | Aug 21 03:35:11 PM UTC 24 |
| Peak memory | 285900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1320181932 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1320181932 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy.800895472 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 12487143565 ps |
| CPU time | 660.81 seconds |
| Started | Aug 21 03:08:50 PM UTC 24 |
| Finished | Aug 21 03:19:59 PM UTC 24 |
| Peak memory | 279764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=800895472 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.800895472 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.360457839 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 57781810095 ps |
| CPU time | 1089.72 seconds |
| Started | Aug 21 03:49:17 PM UTC 24 |
| Finished | Aug 21 04:07:40 PM UTC 24 |
| Peak memory | 283468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36045 7839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 27.alert_handler_stress_all.360457839 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/27.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.192550806 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 35815393233 ps |
| CPU time | 164.71 seconds |
| Started | Aug 21 04:32:31 PM UTC 24 |
| Finished | Aug 21 04:35:19 PM UTC 24 |
| Peak memory | 279592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=192550806 -assert nopostpro c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handle r_shadow_reg_errors.192550806 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.2093494917 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 60757741481 ps |
| CPU time | 3429.34 seconds |
| Started | Aug 21 04:23:14 PM UTC 24 |
| Finished | Aug 21 05:21:02 PM UTC 24 |
| Peak memory | 304612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2093494917 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2093494917 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/44.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.1475781914 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 8560999084 ps |
| CPU time | 263.44 seconds |
| Started | Aug 21 03:07:44 PM UTC 24 |
| Finished | Aug 21 03:12:11 PM UTC 24 |
| Peak memory | 265708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1475781914 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_ timeout.1475781914 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.3706859340 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3936472990 ps |
| CPU time | 53.23 seconds |
| Started | Aug 21 03:08:31 PM UTC 24 |
| Finished | Aug 21 03:09:27 PM UTC 24 |
| Peak memory | 269464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3706859340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3706859340 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.81889696 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 17379368 ps |
| CPU time | 2.08 seconds |
| Started | Aug 21 03:07:51 PM UTC 24 |
| Finished | Aug 21 03:07:55 PM UTC 24 |
| Peak memory | 263276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=81889696 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_satura tion.81889696 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.4074049481 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 12149601 ps |
| CPU time | 2.06 seconds |
| Started | Aug 21 04:33:02 PM UTC 24 |
| Finished | Aug 21 04:33:05 PM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4074049481 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.4074049481 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.2703307757 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 211123202284 ps |
| CPU time | 2897.33 seconds |
| Started | Aug 21 04:32:12 PM UTC 24 |
| Finished | Aug 21 05:21:02 PM UTC 24 |
| Peak memory | 304612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27033 07757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 49.alert_handler_stress_all.2703307757 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/49.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.486052871 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 148153509408 ps |
| CPU time | 2612.82 seconds |
| Started | Aug 21 03:08:35 PM UTC 24 |
| Finished | Aug 21 03:52:37 PM UTC 24 |
| Peak memory | 304620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=486052871 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.486052871 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2241627389 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 4379556465 ps |
| CPU time | 449.99 seconds |
| Started | Aug 21 04:32:26 PM UTC 24 |
| Finished | Aug 21 04:40:02 PM UTC 24 |
| Peak memory | 279528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=2241627389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2241627389 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2892215239 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 4374899632 ps |
| CPU time | 801.57 seconds |
| Started | Aug 21 04:40:04 PM UTC 24 |
| Finished | Aug 21 04:53:36 PM UTC 24 |
| Peak memory | 279592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=2892215239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2892215239 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.1630932579 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 11898243999 ps |
| CPU time | 465.87 seconds |
| Started | Aug 21 03:25:03 PM UTC 24 |
| Finished | Aug 21 03:32:55 PM UTC 24 |
| Peak memory | 263056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1630932579 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping _timeout.1630932579 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.3927150147 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 25777936972 ps |
| CPU time | 1782.26 seconds |
| Started | Aug 21 03:09:06 PM UTC 24 |
| Finished | Aug 21 03:39:08 PM UTC 24 |
| Peak memory | 295748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39271 50147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 7.alert_handler_stress_all.3927150147 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.2621022257 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1376110307 ps |
| CPU time | 20.23 seconds |
| Started | Aug 21 03:07:56 PM UTC 24 |
| Finished | Aug 21 03:08:18 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2621022257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2621022257 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all_with_rand_reset.1999115878 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 54950244764 ps |
| CPU time | 611.19 seconds |
| Started | Aug 21 04:30:06 PM UTC 24 |
| Finished | Aug 21 04:40:26 PM UTC 24 |
| Peak memory | 295956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=1999115878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1999115878 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.363052316 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1394066258 ps |
| CPU time | 61.8 seconds |
| Started | Aug 21 04:40:35 PM UTC 24 |
| Finished | Aug 21 04:41:39 PM UTC 24 |
| Peak memory | 250524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=363052316 -assert nopostproc +UVM _TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_i ntg_err.363052316 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.57427263 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 149116515628 ps |
| CPU time | 2518.7 seconds |
| Started | Aug 21 03:38:23 PM UTC 24 |
| Finished | Aug 21 04:20:49 PM UTC 24 |
| Peak memory | 304948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=57427263 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.57427263 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/21.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2206701841 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 69454346043 ps |
| CPU time | 667.59 seconds |
| Started | Aug 21 04:41:49 PM UTC 24 |
| Finished | Aug 21 04:53:06 PM UTC 24 |
| Peak memory | 279528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=2206701841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2206701841 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2246893739 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 40865429 ps |
| CPU time | 4.81 seconds |
| Started | Aug 21 04:42:25 PM UTC 24 |
| Finished | Aug 21 04:42:31 PM UTC 24 |
| Peak memory | 250592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2246893739 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl _intg_err.2246893739 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.3294918529 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 64882140 ps |
| CPU time | 3.48 seconds |
| Started | Aug 21 03:07:54 PM UTC 24 |
| Finished | Aug 21 03:07:58 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3294918529 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_satu ration.3294918529 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.152342165 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1109259105 ps |
| CPU time | 67.55 seconds |
| Started | Aug 21 03:07:58 PM UTC 24 |
| Finished | Aug 21 03:09:07 PM UTC 24 |
| Peak memory | 269200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=152342165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.152342165 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.2978248262 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 205062513 ps |
| CPU time | 4.52 seconds |
| Started | Aug 21 03:07:58 PM UTC 24 |
| Finished | Aug 21 03:08:03 PM UTC 24 |
| Peak memory | 263376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2978248262 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_satu ration.2978248262 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.2613582586 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 154510679134 ps |
| CPU time | 2471.82 seconds |
| Started | Aug 21 04:23:26 PM UTC 24 |
| Finished | Aug 21 05:05:06 PM UTC 24 |
| Peak memory | 304612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26135 82586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 44.alert_handler_stress_all.2613582586 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/44.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.768470028 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 132951694 ps |
| CPU time | 5.48 seconds |
| Started | Aug 21 03:21:01 PM UTC 24 |
| Finished | Aug 21 03:21:08 PM UTC 24 |
| Peak memory | 263184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=768470028 -assert nopostproc +UVM_TESTNAME=alert_handler _base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_satu ration.768470028 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.3786202216 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 24702462 ps |
| CPU time | 2.89 seconds |
| Started | Aug 21 04:42:31 PM UTC 24 |
| Finished | Aug 21 04:42:35 PM UTC 24 |
| Peak memory | 248408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3786202216 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3786202216 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.3093176801 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 124860096874 ps |
| CPU time | 2191.52 seconds |
| Started | Aug 21 03:11:48 PM UTC 24 |
| Finished | Aug 21 03:48:44 PM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3093176801 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3093176801 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all_with_rand_reset.517403710 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 17453496889 ps |
| CPU time | 473.61 seconds |
| Started | Aug 21 03:29:23 PM UTC 24 |
| Finished | Aug 21 03:37:23 PM UTC 24 |
| Peak memory | 283596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=517403710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.517403710 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.3541652730 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 126837834002 ps |
| CPU time | 3022.96 seconds |
| Started | Aug 21 03:50:51 PM UTC 24 |
| Finished | Aug 21 04:41:47 PM UTC 24 |
| Peak memory | 304696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3541652730 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3541652730 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/28.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.130858732 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 112380595772 ps |
| CPU time | 1950.38 seconds |
| Started | Aug 21 03:57:40 PM UTC 24 |
| Finished | Aug 21 04:30:32 PM UTC 24 |
| Peak memory | 321000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=13085 8732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 31.alert_handler_stress_all.130858732 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/31.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.533863752 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 291302679768 ps |
| CPU time | 1552.67 seconds |
| Started | Aug 21 03:08:09 PM UTC 24 |
| Finished | Aug 21 03:34:19 PM UTC 24 |
| Peak memory | 288232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=53386 3752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 4.alert_handler_stress_all.533863752 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.2596161503 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 1405057888 ps |
| CPU time | 30.06 seconds |
| Started | Aug 21 04:18:50 PM UTC 24 |
| Finished | Aug 21 04:19:21 PM UTC 24 |
| Peak memory | 269144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2596161503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2596161503 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/42.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.4294921016 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 120708014918 ps |
| CPU time | 2305.89 seconds |
| Started | Aug 21 03:07:54 PM UTC 24 |
| Finished | Aug 21 03:46:47 PM UTC 24 |
| Peak memory | 298468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42949 21016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.alert_handler_stress_all.4294921016 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2909445249 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 9247906815 ps |
| CPU time | 411.72 seconds |
| Started | Aug 21 04:44:03 PM UTC 24 |
| Finished | Aug 21 04:51:01 PM UTC 24 |
| Peak memory | 279452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2909445249 -assert nopostpr oc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_hand ler_shadow_reg_errors.2909445249 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.1953872031 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1223743870 ps |
| CPU time | 35.15 seconds |
| Started | Aug 21 03:07:55 PM UTC 24 |
| Finished | Aug 21 03:08:32 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1953872031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1953872031 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2058529257 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 4447908377 ps |
| CPU time | 778.73 seconds |
| Started | Aug 21 04:42:53 PM UTC 24 |
| Finished | Aug 21 04:56:03 PM UTC 24 |
| Peak memory | 279528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=2058529257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2058529257 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.4256249280 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 501782787 ps |
| CPU time | 37.23 seconds |
| Started | Aug 21 03:07:59 PM UTC 24 |
| Finished | Aug 21 03:08:38 PM UTC 24 |
| Peak memory | 269400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4256249280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.4256249280 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1858516082 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 31741011215 ps |
| CPU time | 288.58 seconds |
| Started | Aug 21 04:33:21 PM UTC 24 |
| Finished | Aug 21 04:38:14 PM UTC 24 |
| Peak memory | 250588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1858516082 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bi t_bash.1858516082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg.4150117692 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 38951815515 ps |
| CPU time | 2132.31 seconds |
| Started | Aug 21 03:07:53 PM UTC 24 |
| Finished | Aug 21 03:43:49 PM UTC 24 |
| Peak memory | 304952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4150117692 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.4150117692 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.1145065192 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 6786944229 ps |
| CPU time | 727.17 seconds |
| Started | Aug 21 03:07:53 PM UTC 24 |
| Finished | Aug 21 03:20:09 PM UTC 24 |
| Peak memory | 282092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1145065192 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_s tub_clk.1145065192 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.2836958283 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 8138026467 ps |
| CPU time | 471.65 seconds |
| Started | Aug 21 03:12:14 PM UTC 24 |
| Finished | Aug 21 03:20:12 PM UTC 24 |
| Peak memory | 269392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28369 58283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 10.alert_handler_stress_all.2836958283 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.2865918231 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 38269197905 ps |
| CPU time | 1669.85 seconds |
| Started | Aug 21 03:33:37 PM UTC 24 |
| Finished | Aug 21 04:01:46 PM UTC 24 |
| Peak memory | 302564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2865918231 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2865918231 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.2712891347 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 611482708 ps |
| CPU time | 37.97 seconds |
| Started | Aug 21 03:31:59 PM UTC 24 |
| Finished | Aug 21 03:32:38 PM UTC 24 |
| Peak memory | 269400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2712891347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2712891347 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.4037583724 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 549478707 ps |
| CPU time | 51.93 seconds |
| Started | Aug 21 03:34:54 PM UTC 24 |
| Finished | Aug 21 03:35:48 PM UTC 24 |
| Peak memory | 269200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4037583724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.4037583724 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.4007449159 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 8577503717 ps |
| CPU time | 185.72 seconds |
| Started | Aug 21 03:35:37 PM UTC 24 |
| Finished | Aug 21 03:38:46 PM UTC 24 |
| Peak memory | 269456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40074 49159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 19.alert_handler_stress_all.4007449159 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.278740150 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3041345335 ps |
| CPU time | 132.05 seconds |
| Started | Aug 21 03:07:57 PM UTC 24 |
| Finished | Aug 21 03:10:12 PM UTC 24 |
| Peak memory | 262988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=278740150 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_t imeout.278740150 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.1804394916 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 9042875674 ps |
| CPU time | 202.71 seconds |
| Started | Aug 21 03:38:18 PM UTC 24 |
| Finished | Aug 21 03:41:44 PM UTC 24 |
| Peak memory | 263056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1804394916 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping _timeout.1804394916 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.4132966863 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3287117722 ps |
| CPU time | 64.29 seconds |
| Started | Aug 21 03:43:24 PM UTC 24 |
| Finished | Aug 21 03:44:31 PM UTC 24 |
| Peak memory | 263320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4132966863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.4132966863 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/24.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.540424240 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 484265421 ps |
| CPU time | 39.1 seconds |
| Started | Aug 21 03:56:13 PM UTC 24 |
| Finished | Aug 21 03:56:53 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=540424240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.540424240 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/31.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.1209300300 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 86855279549 ps |
| CPU time | 1695.14 seconds |
| Started | Aug 21 03:59:28 PM UTC 24 |
| Finished | Aug 21 04:28:03 PM UTC 24 |
| Peak memory | 301968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1209300300 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_ stub_clk.1209300300 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.3940520105 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 41199349079 ps |
| CPU time | 812.96 seconds |
| Started | Aug 21 04:01:39 PM UTC 24 |
| Finished | Aug 21 04:15:23 PM UTC 24 |
| Peak memory | 269124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39405 20105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 33.alert_handler_stress_all.3940520105 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/33.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.1565251280 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 7332822040 ps |
| CPU time | 62.28 seconds |
| Started | Aug 21 04:02:21 PM UTC 24 |
| Finished | Aug 21 04:03:26 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1565251280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1565251280 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all_with_rand_reset.3699858457 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 12118141700 ps |
| CPU time | 455.05 seconds |
| Started | Aug 21 04:06:40 PM UTC 24 |
| Finished | Aug 21 04:14:21 PM UTC 24 |
| Peak memory | 285644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=3699858457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3699858457 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.4065352831 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 145712150431 ps |
| CPU time | 1753.54 seconds |
| Started | Aug 21 04:13:12 PM UTC 24 |
| Finished | Aug 21 04:42:44 PM UTC 24 |
| Peak memory | 297288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4065352831 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.4065352831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/39.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.4086797357 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 672184020 ps |
| CPU time | 63.93 seconds |
| Started | Aug 21 04:14:55 PM UTC 24 |
| Finished | Aug 21 04:16:00 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4086797357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.4086797357 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.2678797477 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 355568567 ps |
| CPU time | 24.58 seconds |
| Started | Aug 21 03:07:53 PM UTC 24 |
| Finished | Aug 21 03:08:19 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2678797477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2678797477 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all_with_rand_reset.1943011173 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 12169969247 ps |
| CPU time | 228.38 seconds |
| Started | Aug 21 03:21:07 PM UTC 24 |
| Finished | Aug 21 03:24:59 PM UTC 24 |
| Peak memory | 285716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=1943011173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1943011173 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.16482859 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1915076443 ps |
| CPU time | 250.82 seconds |
| Started | Aug 21 04:40:56 PM UTC 24 |
| Finished | Aug 21 04:45:11 PM UTC 24 |
| Peak memory | 285540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16482859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler _shadow_reg_errors.16482859 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.470957557 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 308143861 ps |
| CPU time | 30.59 seconds |
| Started | Aug 21 04:43:53 PM UTC 24 |
| Finished | Aug 21 04:44:25 PM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=470957557 -assert nopostproc +UVM _TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_ intg_err.470957557 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.440684658 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 58620979 ps |
| CPU time | 6.49 seconds |
| Started | Aug 21 04:41:54 PM UTC 24 |
| Finished | Aug 21 04:42:01 PM UTC 24 |
| Peak memory | 250388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=440684658 -assert nopostproc +UVM _TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_ intg_err.440684658 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1620399848 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 29805503552 ps |
| CPU time | 226.39 seconds |
| Started | Aug 21 04:42:56 PM UTC 24 |
| Finished | Aug 21 04:46:46 PM UTC 24 |
| Peak memory | 283544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1620399848 -assert nopostpr oc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_hand ler_shadow_reg_errors.1620399848 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2429270423 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4381103176 ps |
| CPU time | 92.96 seconds |
| Started | Aug 21 04:43:04 PM UTC 24 |
| Finished | Aug 21 04:44:39 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2429270423 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl _intg_err.2429270423 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.685311645 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 56999529 ps |
| CPU time | 4.4 seconds |
| Started | Aug 21 04:44:09 PM UTC 24 |
| Finished | Aug 21 04:44:14 PM UTC 24 |
| Peak memory | 250524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=685311645 -assert nopostproc +UVM _TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_ intg_err.685311645 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3347446810 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 98859604 ps |
| CPU time | 8.79 seconds |
| Started | Aug 21 04:36:31 PM UTC 24 |
| Finished | Aug 21 04:36:42 PM UTC 24 |
| Peak memory | 250524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3347446810 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_ intg_err.3347446810 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3924712025 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 455422957 ps |
| CPU time | 52.95 seconds |
| Started | Aug 21 04:38:42 PM UTC 24 |
| Finished | Aug 21 04:39:36 PM UTC 24 |
| Peak memory | 250392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3924712025 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_ intg_err.3924712025 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2425515471 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 453366671 ps |
| CPU time | 67.41 seconds |
| Started | Aug 21 04:40:16 PM UTC 24 |
| Finished | Aug 21 04:41:25 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2425515471 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_ intg_err.2425515471 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1477807804 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 104300501 ps |
| CPU time | 4.53 seconds |
| Started | Aug 21 04:42:46 PM UTC 24 |
| Finished | Aug 21 04:42:52 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1477807804 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl _intg_err.1477807804 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2831301064 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 253735113 ps |
| CPU time | 4.23 seconds |
| Started | Aug 21 04:43:24 PM UTC 24 |
| Finished | Aug 21 04:43:30 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2831301064 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl _intg_err.2831301064 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2147282778 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 40304842 ps |
| CPU time | 2.13 seconds |
| Started | Aug 21 04:39:52 PM UTC 24 |
| Finished | Aug 21 04:39:55 PM UTC 24 |
| Peak memory | 250588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2147282778 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_ intg_err.2147282778 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3596850559 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 162201587 ps |
| CPU time | 23.25 seconds |
| Started | Aug 21 04:41:36 PM UTC 24 |
| Finished | Aug 21 04:42:01 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3596850559 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_ intg_err.3596850559 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.3124748556 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1985536163 ps |
| CPU time | 49.54 seconds |
| Started | Aug 21 03:07:52 PM UTC 24 |
| Finished | Aug 21 03:08:43 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3124748556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3124748556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.979533476 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 82389645201 ps |
| CPU time | 3491.9 seconds |
| Started | Aug 21 03:08:36 PM UTC 24 |
| Finished | Aug 21 04:07:26 PM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=97953 3476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 6.alert_handler_stress_all.979533476 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3712048726 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2905213308 ps |
| CPU time | 202.7 seconds |
| Started | Aug 21 04:33:22 PM UTC 24 |
| Finished | Aug 21 04:36:48 PM UTC 24 |
| Peak memory | 252500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3712048726 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_al iasing.3712048726 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2776804052 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 40406334 ps |
| CPU time | 5.02 seconds |
| Started | Aug 21 04:33:06 PM UTC 24 |
| Finished | Aug 21 04:33:12 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2776804052 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw _reset.2776804052 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.129812807 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 80466093 ps |
| CPU time | 10.65 seconds |
| Started | Aug 21 04:33:56 PM UTC 24 |
| Finished | Aug 21 04:34:08 PM UTC 24 |
| Peak memory | 252572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=129812807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.alert_handler_csr_mem_rw_with_rand_reset.129812807 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.3498858041 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 244985528 ps |
| CPU time | 6.25 seconds |
| Started | Aug 21 04:33:13 PM UTC 24 |
| Finished | Aug 21 04:33:21 PM UTC 24 |
| Peak memory | 250396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3498858041 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3498858041 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2314813507 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 717290305 ps |
| CPU time | 55.29 seconds |
| Started | Aug 21 04:33:41 PM UTC 24 |
| Finished | Aug 21 04:34:38 PM UTC 24 |
| Peak memory | 260624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2314813507 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_ha ndler_same_csr_outstanding.2314813507 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.3256368484 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 65676763 ps |
| CPU time | 14.99 seconds |
| Started | Aug 21 04:32:44 PM UTC 24 |
| Finished | Aug 21 04:33:00 PM UTC 24 |
| Peak memory | 266896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3256368484 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3256368484 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2518948 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3471522733 ps |
| CPU time | 189.27 seconds |
| Started | Aug 21 04:35:23 PM UTC 24 |
| Finished | Aug 21 04:38:36 PM UTC 24 |
| Peak memory | 250556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2518948 -assert nopostproc +UVM_TEST NAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2518948 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1545049107 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 8650241918 ps |
| CPU time | 506.76 seconds |
| Started | Aug 21 04:35:19 PM UTC 24 |
| Finished | Aug 21 04:43:52 PM UTC 24 |
| Peak memory | 250524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1545049107 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bi t_bash.1545049107 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.385181285 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 40556587 ps |
| CPU time | 4.43 seconds |
| Started | Aug 21 04:35:17 PM UTC 24 |
| Finished | Aug 21 04:35:23 PM UTC 24 |
| Peak memory | 262684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=385181285 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_ reset.385181285 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1501575209 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 464126951 ps |
| CPU time | 16.26 seconds |
| Started | Aug 21 04:35:57 PM UTC 24 |
| Finished | Aug 21 04:36:14 PM UTC 24 |
| Peak memory | 269016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=1501575209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.alert_handler_csr_mem_rw_with_rand_reset.1501575209 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.2251230247 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 239091877 ps |
| CPU time | 8.67 seconds |
| Started | Aug 21 04:35:19 PM UTC 24 |
| Finished | Aug 21 04:35:29 PM UTC 24 |
| Peak memory | 250320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2251230247 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2251230247 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.719233624 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 7774177 ps |
| CPU time | 1.84 seconds |
| Started | Aug 21 04:35:16 PM UTC 24 |
| Finished | Aug 21 04:35:19 PM UTC 24 |
| Peak memory | 248832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=719233624 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.719233624 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1762219004 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 594238986 ps |
| CPU time | 31.66 seconds |
| Started | Aug 21 04:35:30 PM UTC 24 |
| Finished | Aug 21 04:36:02 PM UTC 24 |
| Peak memory | 260824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1762219004 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_ha ndler_same_csr_outstanding.1762219004 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1930092577 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 2424975684 ps |
| CPU time | 221.44 seconds |
| Started | Aug 21 04:34:39 PM UTC 24 |
| Finished | Aug 21 04:38:24 PM UTC 24 |
| Peak memory | 285592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1930092577 -assert nopostpr oc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handl er_shadow_reg_errors.1930092577 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1708965693 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 9377890404 ps |
| CPU time | 771.41 seconds |
| Started | Aug 21 04:34:10 PM UTC 24 |
| Finished | Aug 21 04:47:11 PM UTC 24 |
| Peak memory | 285736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=1708965693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1708965693 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.2421047600 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 173424118 ps |
| CPU time | 10.48 seconds |
| Started | Aug 21 04:34:58 PM UTC 24 |
| Finished | Aug 21 04:35:10 PM UTC 24 |
| Peak memory | 264856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2421047600 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2421047600 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.236620911 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 172812029 ps |
| CPU time | 3.07 seconds |
| Started | Aug 21 04:35:11 PM UTC 24 |
| Finished | Aug 21 04:35:15 PM UTC 24 |
| Peak memory | 250524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=236620911 -assert nopostproc +UVM _TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_i ntg_err.236620911 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2041942860 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 97409046 ps |
| CPU time | 12.75 seconds |
| Started | Aug 21 04:42:07 PM UTC 24 |
| Finished | Aug 21 04:42:21 PM UTC 24 |
| Peak memory | 252496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=2041942860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 10.alert_handler_csr_mem_rw_with_rand_reset.2041942860 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.3502919431 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 67068173 ps |
| CPU time | 4.9 seconds |
| Started | Aug 21 04:42:02 PM UTC 24 |
| Finished | Aug 21 04:42:08 PM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3502919431 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3502919431 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.2402912291 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 7365219 ps |
| CPU time | 2.15 seconds |
| Started | Aug 21 04:42:02 PM UTC 24 |
| Finished | Aug 21 04:42:06 PM UTC 24 |
| Peak memory | 250320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2402912291 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2402912291 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.4150528365 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 601386764 ps |
| CPU time | 26.43 seconds |
| Started | Aug 21 04:42:04 PM UTC 24 |
| Finished | Aug 21 04:42:32 PM UTC 24 |
| Peak memory | 260696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4150528365 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_h andler_same_csr_outstanding.4150528365 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2897271061 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1544706257 ps |
| CPU time | 112.78 seconds |
| Started | Aug 21 04:41:51 PM UTC 24 |
| Finished | Aug 21 04:43:46 PM UTC 24 |
| Peak memory | 279324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2897271061 -assert nopostpr oc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_hand ler_shadow_reg_errors.2897271061 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.1896899456 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 120491980 ps |
| CPU time | 11.26 seconds |
| Started | Aug 21 04:41:51 PM UTC 24 |
| Finished | Aug 21 04:42:03 PM UTC 24 |
| Peak memory | 266832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1896899456 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1896899456 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1279927550 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 313729255 ps |
| CPU time | 12.44 seconds |
| Started | Aug 21 04:42:33 PM UTC 24 |
| Finished | Aug 21 04:42:46 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=1279927550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.alert_handler_csr_mem_rw_with_rand_reset.1279927550 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.1252012819 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 102410776 ps |
| CPU time | 13 seconds |
| Started | Aug 21 04:42:31 PM UTC 24 |
| Finished | Aug 21 04:42:46 PM UTC 24 |
| Peak memory | 250396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1252012819 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1252012819 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.948340470 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 342181006 ps |
| CPU time | 34.2 seconds |
| Started | Aug 21 04:42:33 PM UTC 24 |
| Finished | Aug 21 04:43:08 PM UTC 24 |
| Peak memory | 260624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=948340470 -assert nopost proc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_ha ndler_same_csr_outstanding.948340470 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3166618960 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 22751562635 ps |
| CPU time | 445.79 seconds |
| Started | Aug 21 04:42:24 PM UTC 24 |
| Finished | Aug 21 04:49:56 PM UTC 24 |
| Peak memory | 285596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3166618960 -assert nopostpr oc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_hand ler_shadow_reg_errors.3166618960 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1527360265 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 11250665942 ps |
| CPU time | 463.13 seconds |
| Started | Aug 21 04:42:10 PM UTC 24 |
| Finished | Aug 21 04:49:59 PM UTC 24 |
| Peak memory | 279592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=1527360265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1527360265 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.523919178 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 274815882 ps |
| CPU time | 5.76 seconds |
| Started | Aug 21 04:42:24 PM UTC 24 |
| Finished | Aug 21 04:42:31 PM UTC 24 |
| Peak memory | 262872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=523919178 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.523919178 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.238058199 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 409163472 ps |
| CPU time | 11.16 seconds |
| Started | Aug 21 04:42:51 PM UTC 24 |
| Finished | Aug 21 04:43:03 PM UTC 24 |
| Peak memory | 252500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=238058199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.alert_handler_csr_mem_rw_with_rand_reset.238058199 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.1115071157 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 163656855 ps |
| CPU time | 6.79 seconds |
| Started | Aug 21 04:42:48 PM UTC 24 |
| Finished | Aug 21 04:42:56 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1115071157 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1115071157 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.2386789454 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 12141023 ps |
| CPU time | 2.44 seconds |
| Started | Aug 21 04:42:46 PM UTC 24 |
| Finished | Aug 21 04:42:50 PM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2386789454 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2386789454 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3741318211 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 652589247 ps |
| CPU time | 26.13 seconds |
| Started | Aug 21 04:42:48 PM UTC 24 |
| Finished | Aug 21 04:43:15 PM UTC 24 |
| Peak memory | 262672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3741318211 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_h andler_same_csr_outstanding.3741318211 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.278458587 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 6040475348 ps |
| CPU time | 198.91 seconds |
| Started | Aug 21 04:42:38 PM UTC 24 |
| Finished | Aug 21 04:46:00 PM UTC 24 |
| Peak memory | 279452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=278458587 -assert nopostpro c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handl er_shadow_reg_errors.278458587 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.3714269567 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 198586057 ps |
| CPU time | 13.07 seconds |
| Started | Aug 21 04:42:42 PM UTC 24 |
| Finished | Aug 21 04:42:56 PM UTC 24 |
| Peak memory | 266832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3714269567 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3714269567 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3927863880 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 191390452 ps |
| CPU time | 7.1 seconds |
| Started | Aug 21 04:43:15 PM UTC 24 |
| Finished | Aug 21 04:43:23 PM UTC 24 |
| Peak memory | 252636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=3927863880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 13.alert_handler_csr_mem_rw_with_rand_reset.3927863880 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.1080002637 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 192608707 ps |
| CPU time | 7.04 seconds |
| Started | Aug 21 04:43:09 PM UTC 24 |
| Finished | Aug 21 04:43:17 PM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1080002637 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1080002637 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.4159553685 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 7893070 ps |
| CPU time | 2.2 seconds |
| Started | Aug 21 04:43:06 PM UTC 24 |
| Finished | Aug 21 04:43:09 PM UTC 24 |
| Peak memory | 250520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4159553685 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.4159553685 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2016407892 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 1451972474 ps |
| CPU time | 36.64 seconds |
| Started | Aug 21 04:43:10 PM UTC 24 |
| Finished | Aug 21 04:43:48 PM UTC 24 |
| Peak memory | 260624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2016407892 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_h andler_same_csr_outstanding.2016407892 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.2231842273 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 72777502 ps |
| CPU time | 16.2 seconds |
| Started | Aug 21 04:42:58 PM UTC 24 |
| Finished | Aug 21 04:43:15 PM UTC 24 |
| Peak memory | 269016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2231842273 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2231842273 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3775160892 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 56716613 ps |
| CPU time | 8.3 seconds |
| Started | Aug 21 04:43:44 PM UTC 24 |
| Finished | Aug 21 04:43:54 PM UTC 24 |
| Peak memory | 264784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=3775160892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.alert_handler_csr_mem_rw_with_rand_reset.3775160892 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.801542702 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 93290975 ps |
| CPU time | 11.95 seconds |
| Started | Aug 21 04:43:34 PM UTC 24 |
| Finished | Aug 21 04:43:47 PM UTC 24 |
| Peak memory | 250328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=801542702 -assert nopostproc +UVM_TESTNAME =alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.801542702 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.4250812495 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 23509056 ps |
| CPU time | 2 seconds |
| Started | Aug 21 04:43:30 PM UTC 24 |
| Finished | Aug 21 04:43:33 PM UTC 24 |
| Peak memory | 248700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4250812495 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4250812495 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.198930735 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 306046521 ps |
| CPU time | 31.45 seconds |
| Started | Aug 21 04:43:35 PM UTC 24 |
| Finished | Aug 21 04:44:08 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=198930735 -assert nopost proc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_ha ndler_same_csr_outstanding.198930735 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3431838588 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 15770948883 ps |
| CPU time | 1130.41 seconds |
| Started | Aug 21 04:43:16 PM UTC 24 |
| Finished | Aug 21 05:02:21 PM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=3431838588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3431838588 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.43488205 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 259564458 ps |
| CPU time | 27.37 seconds |
| Started | Aug 21 04:43:24 PM UTC 24 |
| Finished | Aug 21 04:43:53 PM UTC 24 |
| Peak memory | 266832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=43488205 -assert nopostproc +UVM_TESTNAME=ale rt_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.43488205 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3835132867 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 39952225 ps |
| CPU time | 9.46 seconds |
| Started | Aug 21 04:43:58 PM UTC 24 |
| Finished | Aug 21 04:44:08 PM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=3835132867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.alert_handler_csr_mem_rw_with_rand_reset.3835132867 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.3560966878 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 190312825 ps |
| CPU time | 6.89 seconds |
| Started | Aug 21 04:43:55 PM UTC 24 |
| Finished | Aug 21 04:44:03 PM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3560966878 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3560966878 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.2164673898 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 41390532 ps |
| CPU time | 2.07 seconds |
| Started | Aug 21 04:43:54 PM UTC 24 |
| Finished | Aug 21 04:43:57 PM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2164673898 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2164673898 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1645221942 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 665945575 ps |
| CPU time | 69 seconds |
| Started | Aug 21 04:43:57 PM UTC 24 |
| Finished | Aug 21 04:45:08 PM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1645221942 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_h andler_same_csr_outstanding.1645221942 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.4000144244 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 7920346447 ps |
| CPU time | 641.68 seconds |
| Started | Aug 21 04:43:47 PM UTC 24 |
| Finished | Aug 21 04:54:37 PM UTC 24 |
| Peak memory | 283548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=4000144244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.4000144244 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.1635888864 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 204714456 ps |
| CPU time | 10.29 seconds |
| Started | Aug 21 04:43:49 PM UTC 24 |
| Finished | Aug 21 04:44:00 PM UTC 24 |
| Peak memory | 262736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1635888864 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1635888864 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4051767437 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 243864368 ps |
| CPU time | 7.94 seconds |
| Started | Aug 21 04:44:20 PM UTC 24 |
| Finished | Aug 21 04:44:29 PM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=4051767437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 16.alert_handler_csr_mem_rw_with_rand_reset.4051767437 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.266191687 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 36375087 ps |
| CPU time | 7.78 seconds |
| Started | Aug 21 04:44:13 PM UTC 24 |
| Finished | Aug 21 04:44:22 PM UTC 24 |
| Peak memory | 250396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=266191687 -assert nopostproc +UVM_TESTNAME =alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.266191687 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.761457194 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 8342607 ps |
| CPU time | 2.13 seconds |
| Started | Aug 21 04:44:09 PM UTC 24 |
| Finished | Aug 21 04:44:12 PM UTC 24 |
| Peak memory | 250320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=761457194 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.761457194 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3624066178 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 172852889 ps |
| CPU time | 25.78 seconds |
| Started | Aug 21 04:44:15 PM UTC 24 |
| Finished | Aug 21 04:44:42 PM UTC 24 |
| Peak memory | 262876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3624066178 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_h andler_same_csr_outstanding.3624066178 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3719724356 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 64140026905 ps |
| CPU time | 636.87 seconds |
| Started | Aug 21 04:44:01 PM UTC 24 |
| Finished | Aug 21 04:54:46 PM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=3719724356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3719724356 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.1762210491 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 150348833 ps |
| CPU time | 9.63 seconds |
| Started | Aug 21 04:44:08 PM UTC 24 |
| Finished | Aug 21 04:44:18 PM UTC 24 |
| Peak memory | 266832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1762210491 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1762210491 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3377919782 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 194578470 ps |
| CPU time | 12.55 seconds |
| Started | Aug 21 04:44:59 PM UTC 24 |
| Finished | Aug 21 04:45:12 PM UTC 24 |
| Peak memory | 252500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=3377919782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 17.alert_handler_csr_mem_rw_with_rand_reset.3377919782 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.1839068844 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 911271539 ps |
| CPU time | 7.17 seconds |
| Started | Aug 21 04:44:47 PM UTC 24 |
| Finished | Aug 21 04:44:56 PM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1839068844 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1839068844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.545715264 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 15604386 ps |
| CPU time | 2.42 seconds |
| Started | Aug 21 04:44:43 PM UTC 24 |
| Finished | Aug 21 04:44:47 PM UTC 24 |
| Peak memory | 250320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=545715264 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.545715264 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1204359216 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 362935129 ps |
| CPU time | 18.87 seconds |
| Started | Aug 21 04:44:57 PM UTC 24 |
| Finished | Aug 21 04:45:17 PM UTC 24 |
| Peak memory | 260696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1204359216 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_h andler_same_csr_outstanding.1204359216 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.903768002 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 6107117928 ps |
| CPU time | 224.12 seconds |
| Started | Aug 21 04:44:26 PM UTC 24 |
| Finished | Aug 21 04:48:14 PM UTC 24 |
| Peak memory | 279448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=903768002 -assert nopostpro c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handl er_shadow_reg_errors.903768002 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3266282530 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 169516792985 ps |
| CPU time | 1031.31 seconds |
| Started | Aug 21 04:44:23 PM UTC 24 |
| Finished | Aug 21 05:01:47 PM UTC 24 |
| Peak memory | 279528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=3266282530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3266282530 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.2467599209 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 859524294 ps |
| CPU time | 42.22 seconds |
| Started | Aug 21 04:44:29 PM UTC 24 |
| Finished | Aug 21 04:45:13 PM UTC 24 |
| Peak memory | 262936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2467599209 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2467599209 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3884554945 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 1360519172 ps |
| CPU time | 27.87 seconds |
| Started | Aug 21 04:44:39 PM UTC 24 |
| Finished | Aug 21 04:45:08 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3884554945 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl _intg_err.3884554945 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.690998400 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 304965934 ps |
| CPU time | 8.78 seconds |
| Started | Aug 21 04:45:20 PM UTC 24 |
| Finished | Aug 21 04:45:30 PM UTC 24 |
| Peak memory | 250452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=690998400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.alert_handler_csr_mem_rw_with_rand_reset.690998400 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.1073031364 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 82813450 ps |
| CPU time | 4.82 seconds |
| Started | Aug 21 04:45:18 PM UTC 24 |
| Finished | Aug 21 04:45:24 PM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1073031364 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1073031364 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.269248887 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 18893038 ps |
| CPU time | 2.17 seconds |
| Started | Aug 21 04:45:13 PM UTC 24 |
| Finished | Aug 21 04:45:17 PM UTC 24 |
| Peak memory | 250320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=269248887 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.269248887 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.4055675984 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 747669316 ps |
| CPU time | 31.65 seconds |
| Started | Aug 21 04:45:18 PM UTC 24 |
| Finished | Aug 21 04:45:51 PM UTC 24 |
| Peak memory | 262676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4055675984 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_h andler_same_csr_outstanding.4055675984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1720224844 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 26050700534 ps |
| CPU time | 215.26 seconds |
| Started | Aug 21 04:45:09 PM UTC 24 |
| Finished | Aug 21 04:48:48 PM UTC 24 |
| Peak memory | 279448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1720224844 -assert nopostpr oc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_hand ler_shadow_reg_errors.1720224844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.54330067 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 4815763861 ps |
| CPU time | 286.32 seconds |
| Started | Aug 21 04:45:09 PM UTC 24 |
| Finished | Aug 21 04:50:00 PM UTC 24 |
| Peak memory | 279592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=54330067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.54330067 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.2141805049 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 201695465 ps |
| CPU time | 8.77 seconds |
| Started | Aug 21 04:45:12 PM UTC 24 |
| Finished | Aug 21 04:45:22 PM UTC 24 |
| Peak memory | 262808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2141805049 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2141805049 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3840757743 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 163171669 ps |
| CPU time | 4.66 seconds |
| Started | Aug 21 04:45:13 PM UTC 24 |
| Finished | Aug 21 04:45:19 PM UTC 24 |
| Peak memory | 250396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3840757743 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl _intg_err.3840757743 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3019219267 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 74925206 ps |
| CPU time | 10.33 seconds |
| Started | Aug 21 04:45:43 PM UTC 24 |
| Finished | Aug 21 04:45:55 PM UTC 24 |
| Peak memory | 252500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=3019219267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 19.alert_handler_csr_mem_rw_with_rand_reset.3019219267 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.3460978956 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 19890213 ps |
| CPU time | 5.24 seconds |
| Started | Aug 21 04:45:42 PM UTC 24 |
| Finished | Aug 21 04:45:48 PM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3460978956 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3460978956 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.3422121195 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 7107730 ps |
| CPU time | 2.01 seconds |
| Started | Aug 21 04:45:38 PM UTC 24 |
| Finished | Aug 21 04:45:41 PM UTC 24 |
| Peak memory | 248828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3422121195 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3422121195 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1660598503 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 257118884 ps |
| CPU time | 29.44 seconds |
| Started | Aug 21 04:45:42 PM UTC 24 |
| Finished | Aug 21 04:46:13 PM UTC 24 |
| Peak memory | 260696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1660598503 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_h andler_same_csr_outstanding.1660598503 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.549219838 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 3819658795 ps |
| CPU time | 281.72 seconds |
| Started | Aug 21 04:45:24 PM UTC 24 |
| Finished | Aug 21 04:50:10 PM UTC 24 |
| Peak memory | 279592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=549219838 -assert nopostpro c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handl er_shadow_reg_errors.549219838 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2153813423 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 6228787988 ps |
| CPU time | 700.17 seconds |
| Started | Aug 21 04:45:23 PM UTC 24 |
| Finished | Aug 21 04:57:12 PM UTC 24 |
| Peak memory | 279452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=2153813423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2153813423 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.238638556 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 4415707175 ps |
| CPU time | 33.88 seconds |
| Started | Aug 21 04:45:30 PM UTC 24 |
| Finished | Aug 21 04:46:06 PM UTC 24 |
| Peak memory | 263000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=238638556 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.238638556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1962557730 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 36746226 ps |
| CPU time | 4.71 seconds |
| Started | Aug 21 04:45:35 PM UTC 24 |
| Finished | Aug 21 04:45:41 PM UTC 24 |
| Peak memory | 250392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1962557730 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl _intg_err.1962557730 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3507113764 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 7629354363 ps |
| CPU time | 181.2 seconds |
| Started | Aug 21 04:36:49 PM UTC 24 |
| Finished | Aug 21 04:39:53 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3507113764 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_al iasing.3507113764 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1283775377 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 30917690471 ps |
| CPU time | 299.38 seconds |
| Started | Aug 21 04:36:44 PM UTC 24 |
| Finished | Aug 21 04:41:48 PM UTC 24 |
| Peak memory | 252496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1283775377 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bi t_bash.1283775377 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2169718989 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 141865271 ps |
| CPU time | 8.04 seconds |
| Started | Aug 21 04:36:42 PM UTC 24 |
| Finished | Aug 21 04:36:51 PM UTC 24 |
| Peak memory | 262612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2169718989 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw _reset.2169718989 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.4223571706 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 74868381 ps |
| CPU time | 11.04 seconds |
| Started | Aug 21 04:36:52 PM UTC 24 |
| Finished | Aug 21 04:37:04 PM UTC 24 |
| Peak memory | 252568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=4223571706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.alert_handler_csr_mem_rw_with_rand_reset.4223571706 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.3365546195 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 187371465 ps |
| CPU time | 7.34 seconds |
| Started | Aug 21 04:36:43 PM UTC 24 |
| Finished | Aug 21 04:36:51 PM UTC 24 |
| Peak memory | 250320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3365546195 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3365546195 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.3515682210 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 16178208 ps |
| CPU time | 2.27 seconds |
| Started | Aug 21 04:36:36 PM UTC 24 |
| Finished | Aug 21 04:36:41 PM UTC 24 |
| Peak memory | 250316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3515682210 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3515682210 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.989026443 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2562720641 ps |
| CPU time | 69.69 seconds |
| Started | Aug 21 04:36:52 PM UTC 24 |
| Finished | Aug 21 04:38:03 PM UTC 24 |
| Peak memory | 262800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=989026443 -assert nopost proc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_han dler_same_csr_outstanding.989026443 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.619523646 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 9106273782 ps |
| CPU time | 253.56 seconds |
| Started | Aug 21 04:36:16 PM UTC 24 |
| Finished | Aug 21 04:40:34 PM UTC 24 |
| Peak memory | 269216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=619523646 -assert nopostpro c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handle r_shadow_reg_errors.619523646 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.2869157661 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 275090826 ps |
| CPU time | 16.59 seconds |
| Started | Aug 21 04:36:25 PM UTC 24 |
| Finished | Aug 21 04:36:43 PM UTC 24 |
| Peak memory | 262736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2869157661 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2869157661 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.222647552 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 27746897 ps |
| CPU time | 2.12 seconds |
| Started | Aug 21 04:45:49 PM UTC 24 |
| Finished | Aug 21 04:45:52 PM UTC 24 |
| Peak memory | 250320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=222647552 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.222647552 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/20.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.3030498664 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 6562336 ps |
| CPU time | 2.03 seconds |
| Started | Aug 21 04:45:49 PM UTC 24 |
| Finished | Aug 21 04:45:52 PM UTC 24 |
| Peak memory | 248536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3030498664 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3030498664 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/21.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.2053958446 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 7083658 ps |
| CPU time | 2.03 seconds |
| Started | Aug 21 04:45:51 PM UTC 24 |
| Finished | Aug 21 04:45:54 PM UTC 24 |
| Peak memory | 250392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2053958446 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2053958446 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/22.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.603182542 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 22334212 ps |
| CPU time | 2.12 seconds |
| Started | Aug 21 04:45:54 PM UTC 24 |
| Finished | Aug 21 04:45:57 PM UTC 24 |
| Peak memory | 248272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=603182542 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.603182542 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/23.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.2604732092 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 9673790 ps |
| CPU time | 2.36 seconds |
| Started | Aug 21 04:45:54 PM UTC 24 |
| Finished | Aug 21 04:45:57 PM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2604732092 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2604732092 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/24.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.372896094 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 13903278 ps |
| CPU time | 2.01 seconds |
| Started | Aug 21 04:45:55 PM UTC 24 |
| Finished | Aug 21 04:45:58 PM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=372896094 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.372896094 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/25.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.3055981736 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 11348109 ps |
| CPU time | 2.13 seconds |
| Started | Aug 21 04:45:56 PM UTC 24 |
| Finished | Aug 21 04:45:59 PM UTC 24 |
| Peak memory | 248272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3055981736 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3055981736 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/26.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.2380698003 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 7865478 ps |
| CPU time | 2.05 seconds |
| Started | Aug 21 04:45:57 PM UTC 24 |
| Finished | Aug 21 04:46:00 PM UTC 24 |
| Peak memory | 248408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2380698003 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2380698003 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/27.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.144991773 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 18007068 ps |
| CPU time | 2 seconds |
| Started | Aug 21 04:45:58 PM UTC 24 |
| Finished | Aug 21 04:46:01 PM UTC 24 |
| Peak memory | 246716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=144991773 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.144991773 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/28.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.2424479580 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 7742727 ps |
| CPU time | 2.26 seconds |
| Started | Aug 21 04:45:58 PM UTC 24 |
| Finished | Aug 21 04:46:02 PM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2424479580 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2424479580 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/29.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1567604309 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 6867827659 ps |
| CPU time | 137.69 seconds |
| Started | Aug 21 04:38:18 PM UTC 24 |
| Finished | Aug 21 04:40:38 PM UTC 24 |
| Peak memory | 250452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1567604309 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_al iasing.1567604309 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.309572510 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 2984844047 ps |
| CPU time | 202.15 seconds |
| Started | Aug 21 04:38:15 PM UTC 24 |
| Finished | Aug 21 04:41:41 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=309572510 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit _bash.309572510 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3718429022 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 53384198 ps |
| CPU time | 7.75 seconds |
| Started | Aug 21 04:38:09 PM UTC 24 |
| Finished | Aug 21 04:38:17 PM UTC 24 |
| Peak memory | 262684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3718429022 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw _reset.3718429022 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.782186559 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 121657959 ps |
| CPU time | 5.84 seconds |
| Started | Aug 21 04:38:25 PM UTC 24 |
| Finished | Aug 21 04:38:32 PM UTC 24 |
| Peak memory | 252500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=782186559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.alert_handler_csr_mem_rw_with_rand_reset.782186559 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.58797454 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 350339012 ps |
| CPU time | 12.17 seconds |
| Started | Aug 21 04:38:12 PM UTC 24 |
| Finished | Aug 21 04:38:25 PM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=58797454 -assert nopostproc +UVM_TESTNAME= alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.58797454 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2106684955 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 259033919 ps |
| CPU time | 15.4 seconds |
| Started | Aug 21 04:38:25 PM UTC 24 |
| Finished | Aug 21 04:38:42 PM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2106684955 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_ha ndler_same_csr_outstanding.2106684955 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2396170414 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 13759560284 ps |
| CPU time | 334.19 seconds |
| Started | Aug 21 04:37:05 PM UTC 24 |
| Finished | Aug 21 04:42:44 PM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=2396170414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2396170414 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.1080605556 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 56352220 ps |
| CPU time | 9.79 seconds |
| Started | Aug 21 04:37:22 PM UTC 24 |
| Finished | Aug 21 04:37:33 PM UTC 24 |
| Peak memory | 262736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1080605556 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1080605556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.3623161838 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 9625280 ps |
| CPU time | 1.93 seconds |
| Started | Aug 21 04:46:00 PM UTC 24 |
| Finished | Aug 21 04:46:02 PM UTC 24 |
| Peak memory | 248828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3623161838 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3623161838 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/30.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.207847561 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 7760200 ps |
| CPU time | 1.97 seconds |
| Started | Aug 21 04:46:01 PM UTC 24 |
| Finished | Aug 21 04:46:04 PM UTC 24 |
| Peak memory | 246716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=207847561 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.207847561 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/31.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.341286327 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 27630446 ps |
| CPU time | 2.24 seconds |
| Started | Aug 21 04:46:01 PM UTC 24 |
| Finished | Aug 21 04:46:04 PM UTC 24 |
| Peak memory | 250392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=341286327 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.341286327 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/32.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.3478174364 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 14992891 ps |
| CPU time | 2.3 seconds |
| Started | Aug 21 04:46:02 PM UTC 24 |
| Finished | Aug 21 04:46:05 PM UTC 24 |
| Peak memory | 250392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3478174364 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3478174364 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/33.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.2055437513 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 9178875 ps |
| CPU time | 2.35 seconds |
| Started | Aug 21 04:46:02 PM UTC 24 |
| Finished | Aug 21 04:46:05 PM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2055437513 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2055437513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/34.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.832309180 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 11862785 ps |
| CPU time | 2.57 seconds |
| Started | Aug 21 04:46:03 PM UTC 24 |
| Finished | Aug 21 04:46:07 PM UTC 24 |
| Peak memory | 250520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=832309180 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.832309180 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/35.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.1401610985 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 20644918 ps |
| CPU time | 2.21 seconds |
| Started | Aug 21 04:46:04 PM UTC 24 |
| Finished | Aug 21 04:46:08 PM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1401610985 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1401610985 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/36.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.667885666 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 10524977 ps |
| CPU time | 2.51 seconds |
| Started | Aug 21 04:46:06 PM UTC 24 |
| Finished | Aug 21 04:46:09 PM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=667885666 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.667885666 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/37.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.769517716 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 18726519 ps |
| CPU time | 1.94 seconds |
| Started | Aug 21 04:46:07 PM UTC 24 |
| Finished | Aug 21 04:46:10 PM UTC 24 |
| Peak memory | 248564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=769517716 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.769517716 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/38.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.3110074470 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 8615612 ps |
| CPU time | 2.33 seconds |
| Started | Aug 21 04:46:07 PM UTC 24 |
| Finished | Aug 21 04:46:10 PM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3110074470 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3110074470 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/39.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2786021224 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 6410637926 ps |
| CPU time | 118.06 seconds |
| Started | Aug 21 04:39:08 PM UTC 24 |
| Finished | Aug 21 04:41:08 PM UTC 24 |
| Peak memory | 250524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2786021224 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_al iasing.2786021224 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.258167950 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 6804548321 ps |
| CPU time | 258.65 seconds |
| Started | Aug 21 04:39:00 PM UTC 24 |
| Finished | Aug 21 04:43:23 PM UTC 24 |
| Peak memory | 250448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=258167950 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit _bash.258167950 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2563340073 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 323247453 ps |
| CPU time | 8.21 seconds |
| Started | Aug 21 04:38:47 PM UTC 24 |
| Finished | Aug 21 04:38:56 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2563340073 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw _reset.2563340073 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3187721191 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 295754693 ps |
| CPU time | 17.83 seconds |
| Started | Aug 21 04:39:17 PM UTC 24 |
| Finished | Aug 21 04:39:36 PM UTC 24 |
| Peak memory | 268880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=3187721191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.alert_handler_csr_mem_rw_with_rand_reset.3187721191 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.3931895513 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 51377312 ps |
| CPU time | 7.37 seconds |
| Started | Aug 21 04:38:57 PM UTC 24 |
| Finished | Aug 21 04:39:05 PM UTC 24 |
| Peak memory | 250320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3931895513 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3931895513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.3200173765 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 7842600 ps |
| CPU time | 2.18 seconds |
| Started | Aug 21 04:38:43 PM UTC 24 |
| Finished | Aug 21 04:38:46 PM UTC 24 |
| Peak memory | 250316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3200173765 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3200173765 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2049811238 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 166052758 ps |
| CPU time | 34.87 seconds |
| Started | Aug 21 04:39:09 PM UTC 24 |
| Finished | Aug 21 04:39:45 PM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2049811238 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_ha ndler_same_csr_outstanding.2049811238 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2265137482 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 10187747669 ps |
| CPU time | 305.82 seconds |
| Started | Aug 21 04:38:33 PM UTC 24 |
| Finished | Aug 21 04:43:43 PM UTC 24 |
| Peak memory | 285668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2265137482 -assert nopostpr oc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handl er_shadow_reg_errors.2265137482 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.267799801 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 24772356602 ps |
| CPU time | 424.39 seconds |
| Started | Aug 21 04:38:26 PM UTC 24 |
| Finished | Aug 21 04:45:36 PM UTC 24 |
| Peak memory | 279448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=267799801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.267799801 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.1412027275 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 622079083 ps |
| CPU time | 21.58 seconds |
| Started | Aug 21 04:38:37 PM UTC 24 |
| Finished | Aug 21 04:38:59 PM UTC 24 |
| Peak memory | 262740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1412027275 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1412027275 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.263432318 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 10987904 ps |
| CPU time | 2.35 seconds |
| Started | Aug 21 04:46:07 PM UTC 24 |
| Finished | Aug 21 04:46:10 PM UTC 24 |
| Peak memory | 250392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=263432318 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.263432318 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/40.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.3941760127 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 12728482 ps |
| CPU time | 2.35 seconds |
| Started | Aug 21 04:46:08 PM UTC 24 |
| Finished | Aug 21 04:46:11 PM UTC 24 |
| Peak memory | 248272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3941760127 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3941760127 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/41.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.2190980817 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 13679618 ps |
| CPU time | 1.93 seconds |
| Started | Aug 21 04:46:08 PM UTC 24 |
| Finished | Aug 21 04:46:11 PM UTC 24 |
| Peak memory | 248764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2190980817 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2190980817 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/42.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.966400467 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 8887935 ps |
| CPU time | 2.35 seconds |
| Started | Aug 21 04:46:10 PM UTC 24 |
| Finished | Aug 21 04:46:14 PM UTC 24 |
| Peak memory | 248276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=966400467 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.966400467 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/43.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.2749049334 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 76907103 ps |
| CPU time | 2.1 seconds |
| Started | Aug 21 04:46:10 PM UTC 24 |
| Finished | Aug 21 04:46:14 PM UTC 24 |
| Peak memory | 250520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2749049334 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2749049334 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/44.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.2467446071 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 21572264 ps |
| CPU time | 1.97 seconds |
| Started | Aug 21 04:46:12 PM UTC 24 |
| Finished | Aug 21 04:46:15 PM UTC 24 |
| Peak memory | 248804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2467446071 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2467446071 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/45.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.1323644923 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 10637884 ps |
| CPU time | 1.96 seconds |
| Started | Aug 21 04:46:12 PM UTC 24 |
| Finished | Aug 21 04:46:15 PM UTC 24 |
| Peak memory | 248788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1323644923 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1323644923 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/46.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.2691670995 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 9301424 ps |
| CPU time | 1.87 seconds |
| Started | Aug 21 04:46:12 PM UTC 24 |
| Finished | Aug 21 04:46:15 PM UTC 24 |
| Peak memory | 248700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2691670995 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2691670995 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/47.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.4009844580 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 15604736 ps |
| CPU time | 2.8 seconds |
| Started | Aug 21 04:46:13 PM UTC 24 |
| Finished | Aug 21 04:46:17 PM UTC 24 |
| Peak memory | 250392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4009844580 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.4009844580 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/48.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.2558485264 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 9804092 ps |
| CPU time | 1.92 seconds |
| Started | Aug 21 04:46:14 PM UTC 24 |
| Finished | Aug 21 04:46:17 PM UTC 24 |
| Peak memory | 248828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2558485264 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2558485264 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/49.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3216115574 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 257056359 ps |
| CPU time | 16.34 seconds |
| Started | Aug 21 04:39:59 PM UTC 24 |
| Finished | Aug 21 04:40:16 PM UTC 24 |
| Peak memory | 264784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=3216115574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.alert_handler_csr_mem_rw_with_rand_reset.3216115574 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.2026217862 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 55618430 ps |
| CPU time | 6.52 seconds |
| Started | Aug 21 04:39:56 PM UTC 24 |
| Finished | Aug 21 04:40:03 PM UTC 24 |
| Peak memory | 250320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2026217862 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2026217862 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.42317664 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 19439415 ps |
| CPU time | 2.21 seconds |
| Started | Aug 21 04:39:54 PM UTC 24 |
| Finished | Aug 21 04:39:57 PM UTC 24 |
| Peak memory | 250464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42317664 -assert nopostproc +UVM_TESTNAME=ale rt_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.42317664 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.277648498 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1459073747 ps |
| CPU time | 29.02 seconds |
| Started | Aug 21 04:39:59 PM UTC 24 |
| Finished | Aug 21 04:40:29 PM UTC 24 |
| Peak memory | 260696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=277648498 -assert nopost proc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_han dler_same_csr_outstanding.277648498 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1550518395 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 25158436291 ps |
| CPU time | 204.58 seconds |
| Started | Aug 21 04:39:37 PM UTC 24 |
| Finished | Aug 21 04:43:05 PM UTC 24 |
| Peak memory | 279524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1550518395 -assert nopostpr oc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handl er_shadow_reg_errors.1550518395 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.123072491 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 50737170535 ps |
| CPU time | 1047.87 seconds |
| Started | Aug 21 04:39:37 PM UTC 24 |
| Finished | Aug 21 04:57:17 PM UTC 24 |
| Peak memory | 279448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=123072491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.123072491 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.676572636 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 860741050 ps |
| CPU time | 20.57 seconds |
| Started | Aug 21 04:39:46 PM UTC 24 |
| Finished | Aug 21 04:40:08 PM UTC 24 |
| Peak memory | 268880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=676572636 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.676572636 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1736497977 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 500723824 ps |
| CPU time | 7.83 seconds |
| Started | Aug 21 04:40:27 PM UTC 24 |
| Finished | Aug 21 04:40:36 PM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=1736497977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.alert_handler_csr_mem_rw_with_rand_reset.1736497977 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.3731348263 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 54147870 ps |
| CPU time | 7.1 seconds |
| Started | Aug 21 04:40:18 PM UTC 24 |
| Finished | Aug 21 04:40:27 PM UTC 24 |
| Peak memory | 250396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3731348263 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3731348263 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.4101204 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 25032101 ps |
| CPU time | 2.09 seconds |
| Started | Aug 21 04:40:18 PM UTC 24 |
| Finished | Aug 21 04:40:21 PM UTC 24 |
| Peak memory | 250400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4101204 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.4101204 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.4108241084 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 696464430 ps |
| CPU time | 38.17 seconds |
| Started | Aug 21 04:40:23 PM UTC 24 |
| Finished | Aug 21 04:41:02 PM UTC 24 |
| Peak memory | 262676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4108241084 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_ha ndler_same_csr_outstanding.4108241084 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.851674961 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1695148563 ps |
| CPU time | 155.12 seconds |
| Started | Aug 21 04:40:04 PM UTC 24 |
| Finished | Aug 21 04:42:42 PM UTC 24 |
| Peak memory | 279464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=851674961 -assert nopostpro c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handle r_shadow_reg_errors.851674961 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.4077272709 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 184482153 ps |
| CPU time | 23.12 seconds |
| Started | Aug 21 04:40:09 PM UTC 24 |
| Finished | Aug 21 04:40:33 PM UTC 24 |
| Peak memory | 262732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4077272709 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.4077272709 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.268497747 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 98604905 ps |
| CPU time | 7.63 seconds |
| Started | Aug 21 04:40:50 PM UTC 24 |
| Finished | Aug 21 04:40:58 PM UTC 24 |
| Peak memory | 252496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=268497747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.alert_handler_csr_mem_rw_with_rand_reset.268497747 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.1263109364 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 65585031 ps |
| CPU time | 8.62 seconds |
| Started | Aug 21 04:40:39 PM UTC 24 |
| Finished | Aug 21 04:40:49 PM UTC 24 |
| Peak memory | 250320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1263109364 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1263109364 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.617160015 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 15431718 ps |
| CPU time | 2.41 seconds |
| Started | Aug 21 04:40:37 PM UTC 24 |
| Finished | Aug 21 04:40:41 PM UTC 24 |
| Peak memory | 250328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=617160015 -assert nopostproc +UVM_TESTNAME=al ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.617160015 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2389129006 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 363368008 ps |
| CPU time | 18.22 seconds |
| Started | Aug 21 04:40:41 PM UTC 24 |
| Finished | Aug 21 04:41:01 PM UTC 24 |
| Peak memory | 262812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2389129006 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_ha ndler_same_csr_outstanding.2389129006 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3203294839 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 4335949634 ps |
| CPU time | 315.27 seconds |
| Started | Aug 21 04:40:27 PM UTC 24 |
| Finished | Aug 21 04:45:47 PM UTC 24 |
| Peak memory | 283548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=3203294839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3203294839 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.1822897884 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 283437284 ps |
| CPU time | 17.54 seconds |
| Started | Aug 21 04:40:35 PM UTC 24 |
| Finished | Aug 21 04:40:54 PM UTC 24 |
| Peak memory | 262732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1822897884 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1822897884 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3877864488 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 163077559 ps |
| CPU time | 11.92 seconds |
| Started | Aug 21 04:41:16 PM UTC 24 |
| Finished | Aug 21 04:41:29 PM UTC 24 |
| Peak memory | 264784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=3877864488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.alert_handler_csr_mem_rw_with_rand_reset.3877864488 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.1413297335 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 23266561 ps |
| CPU time | 5.07 seconds |
| Started | Aug 21 04:41:08 PM UTC 24 |
| Finished | Aug 21 04:41:14 PM UTC 24 |
| Peak memory | 250320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1413297335 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1413297335 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.2621396405 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 6769870 ps |
| CPU time | 2.22 seconds |
| Started | Aug 21 04:41:04 PM UTC 24 |
| Finished | Aug 21 04:41:07 PM UTC 24 |
| Peak memory | 250316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2621396405 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2621396405 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.986366289 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 8917913178 ps |
| CPU time | 79.9 seconds |
| Started | Aug 21 04:41:09 PM UTC 24 |
| Finished | Aug 21 04:42:31 PM UTC 24 |
| Peak memory | 260752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=986366289 -assert nopost proc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_han dler_same_csr_outstanding.986366289 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.4218704062 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 473937370 ps |
| CPU time | 13.64 seconds |
| Started | Aug 21 04:40:59 PM UTC 24 |
| Finished | Aug 21 04:41:14 PM UTC 24 |
| Peak memory | 262796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4218704062 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.4218704062 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3119176242 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 295375118 ps |
| CPU time | 32.07 seconds |
| Started | Aug 21 04:41:02 PM UTC 24 |
| Finished | Aug 21 04:41:35 PM UTC 24 |
| Peak memory | 250384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3119176242 -assert nopostproc +UV M_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_ intg_err.3119176242 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.946444352 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 65466661 ps |
| CPU time | 8.05 seconds |
| Started | Aug 21 04:41:44 PM UTC 24 |
| Finished | Aug 21 04:41:53 PM UTC 24 |
| Peak memory | 252500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_r andom_seed=946444352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.alert_handler_csr_mem_rw_with_rand_reset.946444352 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.3408096445 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 51711087 ps |
| CPU time | 6.44 seconds |
| Started | Aug 21 04:41:41 PM UTC 24 |
| Finished | Aug 21 04:41:48 PM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3408096445 -assert nopostproc +UVM_TESTNAM E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3408096445 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.1685836282 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 13958092 ps |
| CPU time | 1.83 seconds |
| Started | Aug 21 04:41:41 PM UTC 24 |
| Finished | Aug 21 04:41:43 PM UTC 24 |
| Peak memory | 248892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1685836282 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1685836282 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2923458800 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 179517022 ps |
| CPU time | 38.3 seconds |
| Started | Aug 21 04:41:42 PM UTC 24 |
| Finished | Aug 21 04:42:22 PM UTC 24 |
| Peak memory | 260624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2923458800 -assert nopos tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_ha ndler_same_csr_outstanding.2923458800 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2067597325 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 48914028784 ps |
| CPU time | 314.11 seconds |
| Started | Aug 21 04:41:27 PM UTC 24 |
| Finished | Aug 21 04:46:46 PM UTC 24 |
| Peak memory | 279452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2067597325 -assert nopostpr oc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handl er_shadow_reg_errors.2067597325 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4126797315 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 51424861061 ps |
| CPU time | 1123.65 seconds |
| Started | Aug 21 04:41:16 PM UTC 24 |
| Finished | Aug 21 05:00:13 PM UTC 24 |
| Peak memory | 279460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_ reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt b_random_seed=4126797315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.4126797315 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.1882933390 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 153038781 ps |
| CPU time | 8.95 seconds |
| Started | Aug 21 04:41:29 PM UTC 24 |
| Finished | Aug 21 04:41:39 PM UTC 24 |
| Peak memory | 262732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1882933390 -assert nopostproc +UVM_TESTNAME=a lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1882933390 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.1788474557 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 37512030091 ps |
| CPU time | 1921.95 seconds |
| Started | Aug 21 03:07:44 PM UTC 24 |
| Finished | Aug 21 03:40:06 PM UTC 24 |
| Peak memory | 288456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1788474557 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1788474557 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.427011432 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2390954251 ps |
| CPU time | 43.4 seconds |
| Started | Aug 21 03:07:44 PM UTC 24 |
| Finished | Aug 21 03:08:29 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=427011432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.427011432 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.1759702999 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 30057231 ps |
| CPU time | 3.4 seconds |
| Started | Aug 21 03:07:44 PM UTC 24 |
| Finished | Aug 21 03:07:49 PM UTC 24 |
| Peak memory | 262708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1759702999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1759702999 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.3537227831 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 54588346393 ps |
| CPU time | 1608.68 seconds |
| Started | Aug 21 03:07:45 PM UTC 24 |
| Finished | Aug 21 03:34:53 PM UTC 24 |
| Peak memory | 288236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3537227831 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3537227831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg_stub_clk.4189735369 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 15621767519 ps |
| CPU time | 1024.88 seconds |
| Started | Aug 21 03:07:45 PM UTC 24 |
| Finished | Aug 21 03:25:02 PM UTC 24 |
| Peak memory | 288568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4189735369 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_s tub_clk.4189735369 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.3055370657 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 4492308521 ps |
| CPU time | 53.73 seconds |
| Started | Aug 21 03:07:44 PM UTC 24 |
| Finished | Aug 21 03:08:39 PM UTC 24 |
| Peak memory | 269444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3055370657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3055370657 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.428470436 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 217410825 ps |
| CPU time | 9.72 seconds |
| Started | Aug 21 03:07:44 PM UTC 24 |
| Finished | Aug 21 03:07:55 PM UTC 24 |
| Peak memory | 269024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=428470436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.428470436 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/0.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.1113659917 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 58781202389 ps |
| CPU time | 1624.25 seconds |
| Started | Aug 21 03:07:53 PM UTC 24 |
| Finished | Aug 21 03:35:14 PM UTC 24 |
| Peak memory | 288232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1113659917 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1113659917 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.29333813 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1126393077 ps |
| CPU time | 11.17 seconds |
| Started | Aug 21 03:07:53 PM UTC 24 |
| Finished | Aug 21 03:08:05 PM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29333813 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.29333813 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.2507590470 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 523404545 ps |
| CPU time | 16.08 seconds |
| Started | Aug 21 03:07:53 PM UTC 24 |
| Finished | Aug 21 03:08:10 PM UTC 24 |
| Peak memory | 269464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2507590470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2507590470 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.2107572920 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 17477824238 ps |
| CPU time | 136.58 seconds |
| Started | Aug 21 03:07:53 PM UTC 24 |
| Finished | Aug 21 03:10:12 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2107572920 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_ timeout.2107572920 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.730334719 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 939894329 ps |
| CPU time | 24.82 seconds |
| Started | Aug 21 03:07:52 PM UTC 24 |
| Finished | Aug 21 03:08:18 PM UTC 24 |
| Peak memory | 263128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=730334719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.730334719 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.3914818866 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 396827067 ps |
| CPU time | 13.13 seconds |
| Started | Aug 21 03:07:54 PM UTC 24 |
| Finished | Aug 21 03:08:08 PM UTC 24 |
| Peak memory | 299376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3914818866 -assert nopostproc +UVM_TESTNA ME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3914818866 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.3838958607 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 2944695873 ps |
| CPU time | 39.75 seconds |
| Started | Aug 21 03:07:53 PM UTC 24 |
| Finished | Aug 21 03:08:34 PM UTC 24 |
| Peak memory | 263064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3838958607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3838958607 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.820999652 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 613917000 ps |
| CPU time | 18.8 seconds |
| Started | Aug 21 03:07:52 PM UTC 24 |
| Finished | Aug 21 03:08:11 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=820999652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.820999652 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.536738790 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 172211445 ps |
| CPU time | 3.34 seconds |
| Started | Aug 21 03:12:15 PM UTC 24 |
| Finished | Aug 21 03:12:20 PM UTC 24 |
| Peak memory | 263580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=536738790 -assert nopostproc +UVM_TESTNAME=alert_handler _base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_satu ration.536738790 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.2095357307 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 779592262 ps |
| CPU time | 8.9 seconds |
| Started | Aug 21 03:12:12 PM UTC 24 |
| Finished | Aug 21 03:12:22 PM UTC 24 |
| Peak memory | 262920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2095357307 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2095357307 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.2600726154 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 168510233 ps |
| CPU time | 6.35 seconds |
| Started | Aug 21 03:11:43 PM UTC 24 |
| Finished | Aug 21 03:11:51 PM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2600726154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2600726154 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.1430309295 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3394958341 ps |
| CPU time | 58.2 seconds |
| Started | Aug 21 03:11:22 PM UTC 24 |
| Finished | Aug 21 03:12:22 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1430309295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1430309295 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.620965349 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 36216880116 ps |
| CPU time | 877.04 seconds |
| Started | Aug 21 03:11:53 PM UTC 24 |
| Finished | Aug 21 03:26:40 PM UTC 24 |
| Peak memory | 285524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=620965349 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.620965349 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.3275656250 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 35520179343 ps |
| CPU time | 2436.74 seconds |
| Started | Aug 21 03:11:57 PM UTC 24 |
| Finished | Aug 21 03:53:02 PM UTC 24 |
| Peak memory | 288228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3275656250 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_ stub_clk.3275656250 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.2278332479 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 10002701560 ps |
| CPU time | 183.57 seconds |
| Started | Aug 21 03:11:52 PM UTC 24 |
| Finished | Aug 21 03:14:58 PM UTC 24 |
| Peak memory | 269200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2278332479 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping _timeout.2278332479 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.2379132610 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 832187356 ps |
| CPU time | 75.56 seconds |
| Started | Aug 21 03:11:05 PM UTC 24 |
| Finished | Aug 21 03:12:23 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2379132610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2379132610 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.2614998185 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 570902476 ps |
| CPU time | 26.52 seconds |
| Started | Aug 21 03:11:14 PM UTC 24 |
| Finished | Aug 21 03:11:42 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2614998185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2614998185 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.3727584786 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 412436914 ps |
| CPU time | 26.91 seconds |
| Started | Aug 21 03:11:45 PM UTC 24 |
| Finished | Aug 21 03:12:14 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3727584786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3727584786 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.613932447 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 825546370 ps |
| CPU time | 81.79 seconds |
| Started | Aug 21 03:10:51 PM UTC 24 |
| Finished | Aug 21 03:12:15 PM UTC 24 |
| Peak memory | 269268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=613932447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.613932447 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all_with_rand_reset.2173056267 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 4181747038 ps |
| CPU time | 444.97 seconds |
| Started | Aug 21 03:12:17 PM UTC 24 |
| Finished | Aug 21 03:19:48 PM UTC 24 |
| Peak memory | 283924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=2173056267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2173056267 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.2153481353 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 40548019 ps |
| CPU time | 5.54 seconds |
| Started | Aug 21 03:13:25 PM UTC 24 |
| Finished | Aug 21 03:13:32 PM UTC 24 |
| Peak memory | 263516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2153481353 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_sat uration.2153481353 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.466730234 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2479465335 ps |
| CPU time | 22.41 seconds |
| Started | Aug 21 03:13:13 PM UTC 24 |
| Finished | Aug 21 03:13:37 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=466730234 -assert nopostproc +UVM_TESTNAME=alert_handler _base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.466730234 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.2721190643 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2367426258 ps |
| CPU time | 49.17 seconds |
| Started | Aug 21 03:12:33 PM UTC 24 |
| Finished | Aug 21 03:13:24 PM UTC 24 |
| Peak memory | 269464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2721190643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2721190643 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.2066032832 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 5155041812 ps |
| CPU time | 46.8 seconds |
| Started | Aug 21 03:12:24 PM UTC 24 |
| Finished | Aug 21 03:13:12 PM UTC 24 |
| Peak memory | 269124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2066032832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2066032832 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.1051906664 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 86183878214 ps |
| CPU time | 1335.71 seconds |
| Started | Aug 21 03:13:05 PM UTC 24 |
| Finished | Aug 21 03:35:35 PM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1051906664 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_ stub_clk.1051906664 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.122400289 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2422740474 ps |
| CPU time | 39.85 seconds |
| Started | Aug 21 03:12:23 PM UTC 24 |
| Finished | Aug 21 03:13:04 PM UTC 24 |
| Peak memory | 263384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=122400289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.122400289 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.2506792554 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 459525246 ps |
| CPU time | 33.89 seconds |
| Started | Aug 21 03:12:23 PM UTC 24 |
| Finished | Aug 21 03:12:58 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2506792554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2506792554 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.36673584 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 168920427 ps |
| CPU time | 17.11 seconds |
| Started | Aug 21 03:12:41 PM UTC 24 |
| Finished | Aug 21 03:13:01 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36673584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.36673584 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.2919881320 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1086149792 ps |
| CPU time | 32.22 seconds |
| Started | Aug 21 03:12:21 PM UTC 24 |
| Finished | Aug 21 03:12:54 PM UTC 24 |
| Peak memory | 269460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2919881320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2919881320 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.916035949 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 3811730782 ps |
| CPU time | 100.77 seconds |
| Started | Aug 21 03:13:25 PM UTC 24 |
| Finished | Aug 21 03:15:08 PM UTC 24 |
| Peak memory | 265032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=91603 5949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 11.alert_handler_stress_all.916035949 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all_with_rand_reset.1288061820 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 13445564956 ps |
| CPU time | 317.59 seconds |
| Started | Aug 21 03:13:32 PM UTC 24 |
| Finished | Aug 21 03:18:55 PM UTC 24 |
| Peak memory | 285716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=1288061820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1288061820 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.2550599764 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 14014096 ps |
| CPU time | 3.53 seconds |
| Started | Aug 21 03:15:17 PM UTC 24 |
| Finished | Aug 21 03:15:21 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2550599764 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_sat uration.2550599764 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.632438970 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 242686099136 ps |
| CPU time | 1925.54 seconds |
| Started | Aug 21 03:14:31 PM UTC 24 |
| Finished | Aug 21 03:46:56 PM UTC 24 |
| Peak memory | 295756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=632438970 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.632438970 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.1260388139 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 280413970 ps |
| CPU time | 11.56 seconds |
| Started | Aug 21 03:15:09 PM UTC 24 |
| Finished | Aug 21 03:15:22 PM UTC 24 |
| Peak memory | 263316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1260388139 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1260388139 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.3789966144 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 7411357574 ps |
| CPU time | 210 seconds |
| Started | Aug 21 03:14:08 PM UTC 24 |
| Finished | Aug 21 03:17:42 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3789966144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3789966144 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.2129633934 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 3659129198 ps |
| CPU time | 72.25 seconds |
| Started | Aug 21 03:14:01 PM UTC 24 |
| Finished | Aug 21 03:15:15 PM UTC 24 |
| Peak memory | 269200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2129633934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2129633934 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.4288963761 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 369129911281 ps |
| CPU time | 3015.73 seconds |
| Started | Aug 21 03:14:47 PM UTC 24 |
| Finished | Aug 21 04:05:35 PM UTC 24 |
| Peak memory | 304684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4288963761 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.4288963761 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.3425461528 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 27432161535 ps |
| CPU time | 1143.66 seconds |
| Started | Aug 21 03:14:59 PM UTC 24 |
| Finished | Aug 21 03:34:16 PM UTC 24 |
| Peak memory | 301968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3425461528 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_ stub_clk.3425461528 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.2128225399 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 23814618950 ps |
| CPU time | 579.52 seconds |
| Started | Aug 21 03:14:46 PM UTC 24 |
| Finished | Aug 21 03:24:32 PM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2128225399 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping _timeout.2128225399 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.3331840090 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2430139129 ps |
| CPU time | 48.38 seconds |
| Started | Aug 21 03:13:55 PM UTC 24 |
| Finished | Aug 21 03:14:45 PM UTC 24 |
| Peak memory | 262988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3331840090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3331840090 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.1898869299 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 536460861 ps |
| CPU time | 28.12 seconds |
| Started | Aug 21 03:14:00 PM UTC 24 |
| Finished | Aug 21 03:14:29 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1898869299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1898869299 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.3005412461 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 278869721 ps |
| CPU time | 31.3 seconds |
| Started | Aug 21 03:14:13 PM UTC 24 |
| Finished | Aug 21 03:14:46 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3005412461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3005412461 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.3026318513 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 923531647 ps |
| CPU time | 21.3 seconds |
| Started | Aug 21 03:13:37 PM UTC 24 |
| Finished | Aug 21 03:14:00 PM UTC 24 |
| Peak memory | 269268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3026318513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3026318513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all.3544048426 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 96564175645 ps |
| CPU time | 2625.08 seconds |
| Started | Aug 21 03:15:11 PM UTC 24 |
| Finished | Aug 21 03:59:25 PM UTC 24 |
| Peak memory | 304612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35440 48426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 12.alert_handler_stress_all.3544048426 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all_with_rand_reset.932264001 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2754628616 ps |
| CPU time | 377.32 seconds |
| Started | Aug 21 03:15:22 PM UTC 24 |
| Finished | Aug 21 03:21:44 PM UTC 24 |
| Peak memory | 281544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=932264001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.932264001 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.3419652696 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 142446170 ps |
| CPU time | 4.9 seconds |
| Started | Aug 21 03:19:00 PM UTC 24 |
| Finished | Aug 21 03:19:07 PM UTC 24 |
| Peak memory | 263516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3419652696 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_sat uration.3419652696 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.2493986246 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 19436769368 ps |
| CPU time | 1582.23 seconds |
| Started | Aug 21 03:17:48 PM UTC 24 |
| Finished | Aug 21 03:44:28 PM UTC 24 |
| Peak memory | 301900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2493986246 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2493986246 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.1459520291 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 5319899528 ps |
| CPU time | 49.07 seconds |
| Started | Aug 21 03:18:56 PM UTC 24 |
| Finished | Aug 21 03:19:47 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1459520291 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1459520291 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.3708262597 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 8518043491 ps |
| CPU time | 197.02 seconds |
| Started | Aug 21 03:17:28 PM UTC 24 |
| Finished | Aug 21 03:20:48 PM UTC 24 |
| Peak memory | 269464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3708262597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3708262597 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.808440834 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1255221787 ps |
| CPU time | 49.11 seconds |
| Started | Aug 21 03:16:57 PM UTC 24 |
| Finished | Aug 21 03:17:47 PM UTC 24 |
| Peak memory | 269400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=808440834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.808440834 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.989592132 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 287252821497 ps |
| CPU time | 1294.62 seconds |
| Started | Aug 21 03:18:40 PM UTC 24 |
| Finished | Aug 21 03:40:29 PM UTC 24 |
| Peak memory | 301900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=989592132 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_s tub_clk.989592132 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.3052709574 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 21995523467 ps |
| CPU time | 397.27 seconds |
| Started | Aug 21 03:18:24 PM UTC 24 |
| Finished | Aug 21 03:25:07 PM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3052709574 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping _timeout.3052709574 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.1141450687 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 530271351 ps |
| CPU time | 46.18 seconds |
| Started | Aug 21 03:15:32 PM UTC 24 |
| Finished | Aug 21 03:16:20 PM UTC 24 |
| Peak memory | 269396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1141450687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1141450687 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.3817845735 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3209215380 ps |
| CPU time | 63.63 seconds |
| Started | Aug 21 03:16:21 PM UTC 24 |
| Finished | Aug 21 03:17:27 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3817845735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3817845735 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.2540239759 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3890802025 ps |
| CPU time | 39 seconds |
| Started | Aug 21 03:17:43 PM UTC 24 |
| Finished | Aug 21 03:18:23 PM UTC 24 |
| Peak memory | 269456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2540239759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2540239759 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.1014239539 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 56305243 ps |
| CPU time | 7.59 seconds |
| Started | Aug 21 03:15:23 PM UTC 24 |
| Finished | Aug 21 03:15:31 PM UTC 24 |
| Peak memory | 262996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1014239539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1014239539 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.1713541962 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 490272272 ps |
| CPU time | 66.08 seconds |
| Started | Aug 21 03:18:58 PM UTC 24 |
| Finished | Aug 21 03:20:06 PM UTC 24 |
| Peak memory | 269060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17135 41962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 13.alert_handler_stress_all.1713541962 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all_with_rand_reset.2486176672 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 7773588062 ps |
| CPU time | 210.89 seconds |
| Started | Aug 21 03:19:07 PM UTC 24 |
| Finished | Aug 21 03:22:42 PM UTC 24 |
| Peak memory | 281620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=2486176672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2486176672 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.2045020466 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 10742712539 ps |
| CPU time | 839.7 seconds |
| Started | Aug 21 03:20:11 PM UTC 24 |
| Finished | Aug 21 03:34:21 PM UTC 24 |
| Peak memory | 285844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2045020466 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2045020466 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.1582542047 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1388674893 ps |
| CPU time | 19.14 seconds |
| Started | Aug 21 03:20:49 PM UTC 24 |
| Finished | Aug 21 03:21:09 PM UTC 24 |
| Peak memory | 263124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1582542047 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1582542047 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.3669451695 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1532706413 ps |
| CPU time | 129.55 seconds |
| Started | Aug 21 03:20:01 PM UTC 24 |
| Finished | Aug 21 03:22:13 PM UTC 24 |
| Peak memory | 264976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3669451695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3669451695 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.1695360599 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 448845394 ps |
| CPU time | 34.73 seconds |
| Started | Aug 21 03:19:58 PM UTC 24 |
| Finished | Aug 21 03:20:34 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1695360599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1695360599 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.4118757418 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 24945426526 ps |
| CPU time | 1138.3 seconds |
| Started | Aug 21 03:20:36 PM UTC 24 |
| Finished | Aug 21 03:39:47 PM UTC 24 |
| Peak memory | 295832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4118757418 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.4118757418 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.3214177101 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 144792714532 ps |
| CPU time | 1785.58 seconds |
| Started | Aug 21 03:20:43 PM UTC 24 |
| Finished | Aug 21 03:50:48 PM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3214177101 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_ stub_clk.3214177101 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.214428716 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 3202136587 ps |
| CPU time | 139.08 seconds |
| Started | Aug 21 03:20:13 PM UTC 24 |
| Finished | Aug 21 03:22:35 PM UTC 24 |
| Peak memory | 263060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=214428716 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_ timeout.214428716 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.2076603188 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 125876981 ps |
| CPU time | 7.08 seconds |
| Started | Aug 21 03:19:49 PM UTC 24 |
| Finished | Aug 21 03:19:57 PM UTC 24 |
| Peak memory | 267020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2076603188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2076603188 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.2608446608 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 569735376 ps |
| CPU time | 44.61 seconds |
| Started | Aug 21 03:19:54 PM UTC 24 |
| Finished | Aug 21 03:20:42 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2608446608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2608446608 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.3073907082 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1920716489 ps |
| CPU time | 50.74 seconds |
| Started | Aug 21 03:20:07 PM UTC 24 |
| Finished | Aug 21 03:20:59 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3073907082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3073907082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.4174460348 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 3134732734 ps |
| CPU time | 70.73 seconds |
| Started | Aug 21 03:19:48 PM UTC 24 |
| Finished | Aug 21 03:21:00 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4174460348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.4174460348 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.2941081888 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 212644545770 ps |
| CPU time | 3063.68 seconds |
| Started | Aug 21 03:21:00 PM UTC 24 |
| Finished | Aug 21 04:12:38 PM UTC 24 |
| Peak memory | 304612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29410 81888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 14.alert_handler_stress_all.2941081888 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/14.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.738080747 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 141450760 ps |
| CPU time | 5.04 seconds |
| Started | Aug 21 03:23:09 PM UTC 24 |
| Finished | Aug 21 03:23:15 PM UTC 24 |
| Peak memory | 263516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=738080747 -assert nopostproc +UVM_TESTNAME=alert_handler _base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_satu ration.738080747 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.3179989990 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 580579740 ps |
| CPU time | 23.76 seconds |
| Started | Aug 21 03:22:42 PM UTC 24 |
| Finished | Aug 21 03:23:07 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3179989990 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3179989990 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.1154110763 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 5269646677 ps |
| CPU time | 149.55 seconds |
| Started | Aug 21 03:21:50 PM UTC 24 |
| Finished | Aug 21 03:24:22 PM UTC 24 |
| Peak memory | 269132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1154110763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1154110763 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.2104467374 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 459437975 ps |
| CPU time | 22.69 seconds |
| Started | Aug 21 03:21:49 PM UTC 24 |
| Finished | Aug 21 03:22:13 PM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2104467374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2104467374 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.2543582352 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 22245583569 ps |
| CPU time | 1243.64 seconds |
| Started | Aug 21 03:22:20 PM UTC 24 |
| Finished | Aug 21 03:43:18 PM UTC 24 |
| Peak memory | 279756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2543582352 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2543582352 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.3702149885 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 617925446534 ps |
| CPU time | 2930.74 seconds |
| Started | Aug 21 03:22:36 PM UTC 24 |
| Finished | Aug 21 04:11:58 PM UTC 24 |
| Peak memory | 304612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3702149885 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_ stub_clk.3702149885 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.3179736626 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 9918144011 ps |
| CPU time | 411.31 seconds |
| Started | Aug 21 03:22:15 PM UTC 24 |
| Finished | Aug 21 03:29:11 PM UTC 24 |
| Peak memory | 269200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3179736626 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping _timeout.3179736626 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.219848501 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1728234526 ps |
| CPU time | 37.72 seconds |
| Started | Aug 21 03:21:11 PM UTC 24 |
| Finished | Aug 21 03:21:50 PM UTC 24 |
| Peak memory | 269144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=219848501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.219848501 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.3060485929 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 336457178 ps |
| CPU time | 13.17 seconds |
| Started | Aug 21 03:21:45 PM UTC 24 |
| Finished | Aug 21 03:21:59 PM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3060485929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3060485929 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.3968103828 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 648361176 ps |
| CPU time | 59.51 seconds |
| Started | Aug 21 03:22:00 PM UTC 24 |
| Finished | Aug 21 03:23:02 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3968103828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3968103828 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.3611352548 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 246891202 ps |
| CPU time | 38.13 seconds |
| Started | Aug 21 03:21:08 PM UTC 24 |
| Finished | Aug 21 03:21:48 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3611352548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3611352548 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.17048666 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 35726204586 ps |
| CPU time | 2083.38 seconds |
| Started | Aug 21 03:23:03 PM UTC 24 |
| Finished | Aug 21 03:58:09 PM UTC 24 |
| Peak memory | 304692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17048 666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 15.alert_handler_stress_all.17048666 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.2229020943 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 16284042 ps |
| CPU time | 3.95 seconds |
| Started | Aug 21 03:26:32 PM UTC 24 |
| Finished | Aug 21 03:26:38 PM UTC 24 |
| Peak memory | 263188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2229020943 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_sat uration.2229020943 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.1514725830 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 18855254892 ps |
| CPU time | 1218.74 seconds |
| Started | Aug 21 03:25:00 PM UTC 24 |
| Finished | Aug 21 03:45:34 PM UTC 24 |
| Peak memory | 295828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1514725830 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1514725830 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.2816966003 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1270367969 ps |
| CPU time | 39.28 seconds |
| Started | Aug 21 03:25:50 PM UTC 24 |
| Finished | Aug 21 03:26:31 PM UTC 24 |
| Peak memory | 262996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2816966003 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2816966003 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.4193564265 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1547940812 ps |
| CPU time | 132.85 seconds |
| Started | Aug 21 03:24:43 PM UTC 24 |
| Finished | Aug 21 03:26:58 PM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4193564265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.4193564265 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.3162250838 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 44155862 ps |
| CPU time | 8.06 seconds |
| Started | Aug 21 03:24:33 PM UTC 24 |
| Finished | Aug 21 03:24:42 PM UTC 24 |
| Peak memory | 262916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3162250838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3162250838 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.1742482272 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 31254730742 ps |
| CPU time | 1318.07 seconds |
| Started | Aug 21 03:25:07 PM UTC 24 |
| Finished | Aug 21 03:47:21 PM UTC 24 |
| Peak memory | 302220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1742482272 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1742482272 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.1229655995 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 247558285223 ps |
| CPU time | 1444.13 seconds |
| Started | Aug 21 03:25:10 PM UTC 24 |
| Finished | Aug 21 03:49:31 PM UTC 24 |
| Peak memory | 285512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1229655995 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_ stub_clk.1229655995 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.199709759 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 871532537 ps |
| CPU time | 46.75 seconds |
| Started | Aug 21 03:24:20 PM UTC 24 |
| Finished | Aug 21 03:25:09 PM UTC 24 |
| Peak memory | 269144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=199709759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.199709759 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.2240155850 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 751582767 ps |
| CPU time | 19.83 seconds |
| Started | Aug 21 03:24:24 PM UTC 24 |
| Finished | Aug 21 03:24:45 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2240155850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2240155850 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.2697424520 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 648380224 ps |
| CPU time | 61.92 seconds |
| Started | Aug 21 03:24:45 PM UTC 24 |
| Finished | Aug 21 03:25:49 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2697424520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2697424520 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.2071215166 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2886525180 ps |
| CPU time | 60.3 seconds |
| Started | Aug 21 03:23:17 PM UTC 24 |
| Finished | Aug 21 03:24:19 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2071215166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2071215166 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.3147608650 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 16936877618 ps |
| CPU time | 1695.37 seconds |
| Started | Aug 21 03:25:52 PM UTC 24 |
| Finished | Aug 21 03:54:27 PM UTC 24 |
| Peak memory | 301892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31476 08650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 16.alert_handler_stress_all.3147608650 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/16.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.1686715685 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 58130348 ps |
| CPU time | 4.85 seconds |
| Started | Aug 21 03:29:16 PM UTC 24 |
| Finished | Aug 21 03:29:22 PM UTC 24 |
| Peak memory | 263188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1686715685 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_sat uration.1686715685 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.3155179794 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 10605415471 ps |
| CPU time | 994.14 seconds |
| Started | Aug 21 03:27:50 PM UTC 24 |
| Finished | Aug 21 03:44:37 PM UTC 24 |
| Peak memory | 285588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3155179794 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3155179794 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.1626923141 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1582602532 ps |
| CPU time | 13.27 seconds |
| Started | Aug 21 03:29:01 PM UTC 24 |
| Finished | Aug 21 03:29:15 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1626923141 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1626923141 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.3403383316 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1589192465 ps |
| CPU time | 165.2 seconds |
| Started | Aug 21 03:27:18 PM UTC 24 |
| Finished | Aug 21 03:30:06 PM UTC 24 |
| Peak memory | 269400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3403383316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3403383316 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.395955377 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 7797257798 ps |
| CPU time | 67.79 seconds |
| Started | Aug 21 03:27:16 PM UTC 24 |
| Finished | Aug 21 03:28:25 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=395955377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.395955377 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.621104988 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 39116147818 ps |
| CPU time | 945.79 seconds |
| Started | Aug 21 03:28:20 PM UTC 24 |
| Finished | Aug 21 03:44:17 PM UTC 24 |
| Peak memory | 285524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=621104988 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.621104988 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.399260042 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 19634564113 ps |
| CPU time | 1116.81 seconds |
| Started | Aug 21 03:28:27 PM UTC 24 |
| Finished | Aug 21 03:47:17 PM UTC 24 |
| Peak memory | 301900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=399260042 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_s tub_clk.399260042 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.4240149844 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 21039626364 ps |
| CPU time | 324.82 seconds |
| Started | Aug 21 03:28:14 PM UTC 24 |
| Finished | Aug 21 03:33:43 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4240149844 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping _timeout.4240149844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.4187202137 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1804451845 ps |
| CPU time | 78.75 seconds |
| Started | Aug 21 03:26:59 PM UTC 24 |
| Finished | Aug 21 03:28:20 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4187202137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.4187202137 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.3212098467 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1278361501 ps |
| CPU time | 26.41 seconds |
| Started | Aug 21 03:27:03 PM UTC 24 |
| Finished | Aug 21 03:27:31 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3212098467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3212098467 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.3650048973 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 275528795 ps |
| CPU time | 15.65 seconds |
| Started | Aug 21 03:27:32 PM UTC 24 |
| Finished | Aug 21 03:27:50 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3650048973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3650048973 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.1827530604 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 591895863 ps |
| CPU time | 33.87 seconds |
| Started | Aug 21 03:26:42 PM UTC 24 |
| Finished | Aug 21 03:27:17 PM UTC 24 |
| Peak memory | 269460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1827530604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1827530604 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.2030843575 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 9708784419 ps |
| CPU time | 393.59 seconds |
| Started | Aug 21 03:29:12 PM UTC 24 |
| Finished | Aug 21 03:35:51 PM UTC 24 |
| Peak memory | 269456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20308 43575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 17.alert_handler_stress_all.2030843575 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/17.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.2177013354 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 124499704 ps |
| CPU time | 4.43 seconds |
| Started | Aug 21 03:34:06 PM UTC 24 |
| Finished | Aug 21 03:34:12 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2177013354 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_sat uration.2177013354 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.1921593325 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 52242793774 ps |
| CPU time | 1380.12 seconds |
| Started | Aug 21 03:33:02 PM UTC 24 |
| Finished | Aug 21 03:56:19 PM UTC 24 |
| Peak memory | 295756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1921593325 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1921593325 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.2601699509 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 187635479 ps |
| CPU time | 13.64 seconds |
| Started | Aug 21 03:33:51 PM UTC 24 |
| Finished | Aug 21 03:34:06 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2601699509 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2601699509 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.2571041634 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 607432066 ps |
| CPU time | 54.79 seconds |
| Started | Aug 21 03:32:39 PM UTC 24 |
| Finished | Aug 21 03:33:36 PM UTC 24 |
| Peak memory | 269400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2571041634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2571041634 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.470718843 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 853153070 ps |
| CPU time | 71.62 seconds |
| Started | Aug 21 03:32:04 PM UTC 24 |
| Finished | Aug 21 03:33:17 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=470718843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.470718843 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.3851882240 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 407613853650 ps |
| CPU time | 2263.91 seconds |
| Started | Aug 21 03:33:44 PM UTC 24 |
| Finished | Aug 21 04:11:53 PM UTC 24 |
| Peak memory | 304612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3851882240 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_ stub_clk.3851882240 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.3414831978 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 25487483750 ps |
| CPU time | 473.05 seconds |
| Started | Aug 21 03:33:19 PM UTC 24 |
| Finished | Aug 21 03:41:17 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3414831978 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping _timeout.3414831978 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.3243212394 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 809995340 ps |
| CPU time | 46.74 seconds |
| Started | Aug 21 03:31:15 PM UTC 24 |
| Finished | Aug 21 03:32:03 PM UTC 24 |
| Peak memory | 269396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3243212394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3243212394 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.509086254 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 171576429 ps |
| CPU time | 5.44 seconds |
| Started | Aug 21 03:32:55 PM UTC 24 |
| Finished | Aug 21 03:33:02 PM UTC 24 |
| Peak memory | 252884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=509086254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.509086254 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.2270091834 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2176485423 ps |
| CPU time | 64.5 seconds |
| Started | Aug 21 03:30:07 PM UTC 24 |
| Finished | Aug 21 03:31:14 PM UTC 24 |
| Peak memory | 269460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2270091834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2270091834 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.2099315419 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 5872856841 ps |
| CPU time | 148.29 seconds |
| Started | Aug 21 03:34:04 PM UTC 24 |
| Finished | Aug 21 03:36:35 PM UTC 24 |
| Peak memory | 265104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20993 15419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 18.alert_handler_stress_all.2099315419 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/18.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.2619385406 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 625648126 ps |
| CPU time | 4.81 seconds |
| Started | Aug 21 03:35:48 PM UTC 24 |
| Finished | Aug 21 03:35:54 PM UTC 24 |
| Peak memory | 263184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2619385406 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_sat uration.2619385406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.4160656602 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 287172806313 ps |
| CPU time | 2290.74 seconds |
| Started | Aug 21 03:35:12 PM UTC 24 |
| Finished | Aug 21 04:13:48 PM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4160656602 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.4160656602 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.154436149 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2483637778 ps |
| CPU time | 43.54 seconds |
| Started | Aug 21 03:35:30 PM UTC 24 |
| Finished | Aug 21 03:36:15 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=154436149 -assert nopostproc +UVM_TESTNAME=alert_handler _base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.154436149 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.2689476955 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 10849830611 ps |
| CPU time | 238.84 seconds |
| Started | Aug 21 03:34:31 PM UTC 24 |
| Finished | Aug 21 03:38:34 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2689476955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2689476955 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.1600923671 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 10563093564 ps |
| CPU time | 54.54 seconds |
| Started | Aug 21 03:34:27 PM UTC 24 |
| Finished | Aug 21 03:35:23 PM UTC 24 |
| Peak memory | 269124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1600923671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1600923671 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.2841065405 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 181074914795 ps |
| CPU time | 2410.19 seconds |
| Started | Aug 21 03:35:17 PM UTC 24 |
| Finished | Aug 21 04:15:53 PM UTC 24 |
| Peak memory | 288232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2841065405 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2841065405 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.1336996918 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 19841995710 ps |
| CPU time | 1626.53 seconds |
| Started | Aug 21 03:35:24 PM UTC 24 |
| Finished | Aug 21 04:02:50 PM UTC 24 |
| Peak memory | 301892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1336996918 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_ stub_clk.1336996918 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.103585699 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3418062812 ps |
| CPU time | 112.4 seconds |
| Started | Aug 21 03:35:16 PM UTC 24 |
| Finished | Aug 21 03:37:10 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=103585699 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_ timeout.103585699 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.3652652997 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 235380444 ps |
| CPU time | 8.26 seconds |
| Started | Aug 21 03:34:20 PM UTC 24 |
| Finished | Aug 21 03:34:30 PM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3652652997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3652652997 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.3852495773 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 9101710200 ps |
| CPU time | 50.26 seconds |
| Started | Aug 21 03:34:23 PM UTC 24 |
| Finished | Aug 21 03:35:15 PM UTC 24 |
| Peak memory | 263320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3852495773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3852495773 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.2517477774 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 107141729 ps |
| CPU time | 6.21 seconds |
| Started | Aug 21 03:34:18 PM UTC 24 |
| Finished | Aug 21 03:34:26 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2517477774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2517477774 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.1350077868 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 86003024276 ps |
| CPU time | 2615.12 seconds |
| Started | Aug 21 03:07:57 PM UTC 24 |
| Finished | Aug 21 03:52:02 PM UTC 24 |
| Peak memory | 298544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1350077868 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1350077868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.1343154412 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 977150872 ps |
| CPU time | 22.73 seconds |
| Started | Aug 21 03:07:58 PM UTC 24 |
| Finished | Aug 21 03:08:22 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1343154412 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1343154412 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.3792387650 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 833769514 ps |
| CPU time | 65.37 seconds |
| Started | Aug 21 03:07:57 PM UTC 24 |
| Finished | Aug 21 03:09:04 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3792387650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3792387650 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.1734483962 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 48353446997 ps |
| CPU time | 3187.52 seconds |
| Started | Aug 21 03:07:58 PM UTC 24 |
| Finished | Aug 21 04:01:43 PM UTC 24 |
| Peak memory | 300512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1734483962 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1734483962 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.3324480620 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 44345667522 ps |
| CPU time | 2422.71 seconds |
| Started | Aug 21 03:07:58 PM UTC 24 |
| Finished | Aug 21 03:48:48 PM UTC 24 |
| Peak memory | 302576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3324480620 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_s tub_clk.3324480620 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.1214524369 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1366116084 ps |
| CPU time | 50.72 seconds |
| Started | Aug 21 03:07:58 PM UTC 24 |
| Finished | Aug 21 03:08:50 PM UTC 24 |
| Peak memory | 295352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1214524369 -assert nopostproc +UVM_TESTNA ME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1214524369 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.2003709399 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1104373290 ps |
| CPU time | 40.08 seconds |
| Started | Aug 21 03:07:57 PM UTC 24 |
| Finished | Aug 21 03:08:39 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2003709399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2003709399 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.2140361550 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 644008165 ps |
| CPU time | 17.02 seconds |
| Started | Aug 21 03:07:55 PM UTC 24 |
| Finished | Aug 21 03:08:13 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2140361550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2140361550 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.673519606 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 42188947335 ps |
| CPU time | 2922.98 seconds |
| Started | Aug 21 03:36:20 PM UTC 24 |
| Finished | Aug 21 04:25:37 PM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=673519606 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.673519606 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/20.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.3466239721 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 5522829439 ps |
| CPU time | 101.99 seconds |
| Started | Aug 21 03:36:16 PM UTC 24 |
| Finished | Aug 21 03:38:01 PM UTC 24 |
| Peak memory | 269132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3466239721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3466239721 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.2102193734 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 446176727 ps |
| CPU time | 39.04 seconds |
| Started | Aug 21 03:36:15 PM UTC 24 |
| Finished | Aug 21 03:36:56 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2102193734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2102193734 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.1577774017 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 82649368729 ps |
| CPU time | 2583.66 seconds |
| Started | Aug 21 03:36:36 PM UTC 24 |
| Finished | Aug 21 04:20:09 PM UTC 24 |
| Peak memory | 300516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1577774017 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1577774017 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/20.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.2903045288 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 70654857846 ps |
| CPU time | 1158.18 seconds |
| Started | Aug 21 03:36:57 PM UTC 24 |
| Finished | Aug 21 03:56:28 PM UTC 24 |
| Peak memory | 296080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2903045288 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_ stub_clk.2903045288 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.3446788065 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 21416916960 ps |
| CPU time | 423.12 seconds |
| Started | Aug 21 03:36:30 PM UTC 24 |
| Finished | Aug 21 03:43:38 PM UTC 24 |
| Peak memory | 263056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3446788065 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping _timeout.3446788065 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.3200896169 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 7763739306 ps |
| CPU time | 34.8 seconds |
| Started | Aug 21 03:35:53 PM UTC 24 |
| Finished | Aug 21 03:36:29 PM UTC 24 |
| Peak memory | 263060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3200896169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3200896169 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.2619728315 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 493644518 ps |
| CPU time | 22.3 seconds |
| Started | Aug 21 03:35:55 PM UTC 24 |
| Finished | Aug 21 03:36:19 PM UTC 24 |
| Peak memory | 269144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2619728315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2619728315 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/20.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.4271165961 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1289505808 ps |
| CPU time | 47.69 seconds |
| Started | Aug 21 03:36:16 PM UTC 24 |
| Finished | Aug 21 03:37:06 PM UTC 24 |
| Peak memory | 263124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4271165961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.4271165961 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.3975872361 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 322000526 ps |
| CPU time | 19.64 seconds |
| Started | Aug 21 03:35:53 PM UTC 24 |
| Finished | Aug 21 03:36:14 PM UTC 24 |
| Peak memory | 269332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3975872361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3975872361 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/20.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all.2007011302 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 387475969760 ps |
| CPU time | 2708.22 seconds |
| Started | Aug 21 03:37:06 PM UTC 24 |
| Finished | Aug 21 04:22:45 PM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20070 11302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 20.alert_handler_stress_all.2007011302 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/20.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.3402730530 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 9923893051 ps |
| CPU time | 181.87 seconds |
| Started | Aug 21 03:37:11 PM UTC 24 |
| Finished | Aug 21 03:40:16 PM UTC 24 |
| Peak memory | 279500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=3402730530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3402730530 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.3850753334 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 181493583809 ps |
| CPU time | 2378.41 seconds |
| Started | Aug 21 03:38:01 PM UTC 24 |
| Finished | Aug 21 04:18:06 PM UTC 24 |
| Peak memory | 298472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3850753334 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3850753334 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/21.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.102043625 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1948186284 ps |
| CPU time | 126.17 seconds |
| Started | Aug 21 03:37:52 PM UTC 24 |
| Finished | Aug 21 03:40:00 PM UTC 24 |
| Peak memory | 269400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=102043625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.102043625 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.1152112250 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 91161020 ps |
| CPU time | 5.92 seconds |
| Started | Aug 21 03:37:47 PM UTC 24 |
| Finished | Aug 21 03:37:54 PM UTC 24 |
| Peak memory | 265040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1152112250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1152112250 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.1311155177 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 85422023102 ps |
| CPU time | 1350.61 seconds |
| Started | Aug 21 03:38:35 PM UTC 24 |
| Finished | Aug 21 04:01:20 PM UTC 24 |
| Peak memory | 285904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1311155177 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_ stub_clk.1311155177 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.659729942 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 349322067 ps |
| CPU time | 17.1 seconds |
| Started | Aug 21 03:37:24 PM UTC 24 |
| Finished | Aug 21 03:37:43 PM UTC 24 |
| Peak memory | 263320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=659729942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.659729942 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.2640846142 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 6908612925 ps |
| CPU time | 59.09 seconds |
| Started | Aug 21 03:37:43 PM UTC 24 |
| Finished | Aug 21 03:38:44 PM UTC 24 |
| Peak memory | 263320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2640846142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2640846142 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/21.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.3205025332 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1864949560 ps |
| CPU time | 24.66 seconds |
| Started | Aug 21 03:37:55 PM UTC 24 |
| Finished | Aug 21 03:38:21 PM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3205025332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3205025332 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.3009310783 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 792702849 ps |
| CPU time | 29.54 seconds |
| Started | Aug 21 03:37:21 PM UTC 24 |
| Finished | Aug 21 03:37:52 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3009310783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3009310783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/21.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.3818557887 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 4064745289 ps |
| CPU time | 314.62 seconds |
| Started | Aug 21 03:38:45 PM UTC 24 |
| Finished | Aug 21 03:44:04 PM UTC 24 |
| Peak memory | 269200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38185 57887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 21.alert_handler_stress_all.3818557887 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/21.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.2228218187 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 102630768267 ps |
| CPU time | 1763.99 seconds |
| Started | Aug 21 03:40:00 PM UTC 24 |
| Finished | Aug 21 04:09:44 PM UTC 24 |
| Peak memory | 285512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2228218187 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2228218187 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/22.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.2304557360 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1903982288 ps |
| CPU time | 33.29 seconds |
| Started | Aug 21 03:39:28 PM UTC 24 |
| Finished | Aug 21 03:40:03 PM UTC 24 |
| Peak memory | 263000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2304557360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2304557360 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.2196578186 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 445805131 ps |
| CPU time | 34.85 seconds |
| Started | Aug 21 03:39:26 PM UTC 24 |
| Finished | Aug 21 03:40:02 PM UTC 24 |
| Peak memory | 269456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2196578186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2196578186 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.4167869534 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 34918933824 ps |
| CPU time | 1703.99 seconds |
| Started | Aug 21 03:40:03 PM UTC 24 |
| Finished | Aug 21 04:08:45 PM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4167869534 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.4167869534 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/22.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.1390539897 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 26217673054 ps |
| CPU time | 1819.49 seconds |
| Started | Aug 21 03:40:04 PM UTC 24 |
| Finished | Aug 21 04:10:44 PM UTC 24 |
| Peak memory | 295824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1390539897 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_ stub_clk.1390539897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.2570185202 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 57920227954 ps |
| CPU time | 492.94 seconds |
| Started | Aug 21 03:40:02 PM UTC 24 |
| Finished | Aug 21 03:48:20 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2570185202 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping _timeout.2570185202 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.742566199 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 176765503 ps |
| CPU time | 13.23 seconds |
| Started | Aug 21 03:39:11 PM UTC 24 |
| Finished | Aug 21 03:39:25 PM UTC 24 |
| Peak memory | 262928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=742566199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.742566199 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.1409549433 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 835298598 ps |
| CPU time | 37.02 seconds |
| Started | Aug 21 03:39:20 PM UTC 24 |
| Finished | Aug 21 03:39:58 PM UTC 24 |
| Peak memory | 269400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1409549433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1409549433 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/22.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.4101052602 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1268386738 ps |
| CPU time | 24.82 seconds |
| Started | Aug 21 03:39:48 PM UTC 24 |
| Finished | Aug 21 03:40:14 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4101052602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.4101052602 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.1764069435 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 515486972 ps |
| CPU time | 18.49 seconds |
| Started | Aug 21 03:38:59 PM UTC 24 |
| Finished | Aug 21 03:39:19 PM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1764069435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1764069435 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/22.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.2388401141 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 117260162166 ps |
| CPU time | 2226.12 seconds |
| Started | Aug 21 03:40:08 PM UTC 24 |
| Finished | Aug 21 04:17:40 PM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=23884 01141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 22.alert_handler_stress_all.2388401141 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/22.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.943684282 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 40778240975 ps |
| CPU time | 778.57 seconds |
| Started | Aug 21 03:41:45 PM UTC 24 |
| Finished | Aug 21 03:54:53 PM UTC 24 |
| Peak memory | 285584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=943684282 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.943684282 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/23.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.4084967042 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 787223630 ps |
| CPU time | 94.3 seconds |
| Started | Aug 21 03:41:34 PM UTC 24 |
| Finished | Aug 21 03:43:11 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4084967042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.4084967042 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.2857111803 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1098712781 ps |
| CPU time | 45.62 seconds |
| Started | Aug 21 03:41:21 PM UTC 24 |
| Finished | Aug 21 03:42:08 PM UTC 24 |
| Peak memory | 262916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2857111803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2857111803 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.388942159 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 97191592149 ps |
| CPU time | 1302.92 seconds |
| Started | Aug 21 03:42:32 PM UTC 24 |
| Finished | Aug 21 04:04:30 PM UTC 24 |
| Peak memory | 285520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=388942159 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.388942159 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/23.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.235123082 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 827205811342 ps |
| CPU time | 2650.03 seconds |
| Started | Aug 21 03:42:32 PM UTC 24 |
| Finished | Aug 21 04:27:12 PM UTC 24 |
| Peak memory | 304948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=235123082 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_s tub_clk.235123082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.1778210795 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 12476532800 ps |
| CPU time | 494.51 seconds |
| Started | Aug 21 03:42:32 PM UTC 24 |
| Finished | Aug 21 03:50:52 PM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1778210795 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping _timeout.1778210795 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.2741979948 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 716439376 ps |
| CPU time | 46.14 seconds |
| Started | Aug 21 03:40:32 PM UTC 24 |
| Finished | Aug 21 03:41:20 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2741979948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2741979948 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.2971271917 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1059215418 ps |
| CPU time | 53.65 seconds |
| Started | Aug 21 03:41:19 PM UTC 24 |
| Finished | Aug 21 03:42:14 PM UTC 24 |
| Peak memory | 262928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2971271917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2971271917 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/23.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.4052749737 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 121316223 ps |
| CPU time | 19.08 seconds |
| Started | Aug 21 03:41:38 PM UTC 24 |
| Finished | Aug 21 03:41:58 PM UTC 24 |
| Peak memory | 269396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4052749737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4052749737 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.873259397 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 4178896040 ps |
| CPU time | 73.98 seconds |
| Started | Aug 21 03:40:17 PM UTC 24 |
| Finished | Aug 21 03:41:33 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=873259397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.873259397 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/23.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.1835449982 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 423162314450 ps |
| CPU time | 2725.84 seconds |
| Started | Aug 21 03:42:32 PM UTC 24 |
| Finished | Aug 21 04:28:29 PM UTC 24 |
| Peak memory | 304688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18354 49982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 23.alert_handler_stress_all.1835449982 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/23.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.1064111646 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 22288052573 ps |
| CPU time | 1344.76 seconds |
| Started | Aug 21 03:44:04 PM UTC 24 |
| Finished | Aug 21 04:06:43 PM UTC 24 |
| Peak memory | 285516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1064111646 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1064111646 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/24.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.832066478 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 3292542675 ps |
| CPU time | 91.32 seconds |
| Started | Aug 21 03:43:52 PM UTC 24 |
| Finished | Aug 21 03:45:25 PM UTC 24 |
| Peak memory | 269272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=832066478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.832066478 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.4039511666 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 4900370745 ps |
| CPU time | 45.76 seconds |
| Started | Aug 21 03:43:40 PM UTC 24 |
| Finished | Aug 21 03:44:27 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4039511666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.4039511666 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.1634872422 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 48548962890 ps |
| CPU time | 1236.75 seconds |
| Started | Aug 21 03:44:17 PM UTC 24 |
| Finished | Aug 21 04:05:09 PM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1634872422 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1634872422 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/24.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.634777573 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 90442918995 ps |
| CPU time | 1480.04 seconds |
| Started | Aug 21 03:44:19 PM UTC 24 |
| Finished | Aug 21 04:09:16 PM UTC 24 |
| Peak memory | 285588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=634777573 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_s tub_clk.634777573 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.2800139482 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 27229038131 ps |
| CPU time | 446.94 seconds |
| Started | Aug 21 03:44:05 PM UTC 24 |
| Finished | Aug 21 03:51:37 PM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2800139482 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping _timeout.2800139482 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.3957766224 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 446685968 ps |
| CPU time | 38.27 seconds |
| Started | Aug 21 03:43:23 PM UTC 24 |
| Finished | Aug 21 03:44:03 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3957766224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3957766224 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.3128942067 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1022049531 ps |
| CPU time | 16.7 seconds |
| Started | Aug 21 03:43:58 PM UTC 24 |
| Finished | Aug 21 03:44:16 PM UTC 24 |
| Peak memory | 263120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3128942067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3128942067 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.2589515563 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 3352033289 ps |
| CPU time | 35.33 seconds |
| Started | Aug 21 03:43:20 PM UTC 24 |
| Finished | Aug 21 03:43:57 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2589515563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2589515563 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/24.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.2962823536 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 11247807373 ps |
| CPU time | 583.75 seconds |
| Started | Aug 21 03:44:19 PM UTC 24 |
| Finished | Aug 21 03:54:11 PM UTC 24 |
| Peak memory | 269124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29628 23536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 24.alert_handler_stress_all.2962823536 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/24.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.4004400905 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 35060141701 ps |
| CPU time | 1123.31 seconds |
| Started | Aug 21 03:45:26 PM UTC 24 |
| Finished | Aug 21 04:04:23 PM UTC 24 |
| Peak memory | 285512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4004400905 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.4004400905 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/25.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.908423544 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 4770702664 ps |
| CPU time | 118.07 seconds |
| Started | Aug 21 03:45:17 PM UTC 24 |
| Finished | Aug 21 03:47:18 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=908423544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.908423544 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.2198208303 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1773923294 ps |
| CPU time | 39.12 seconds |
| Started | Aug 21 03:44:56 PM UTC 24 |
| Finished | Aug 21 03:45:37 PM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2198208303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2198208303 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.3679477082 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 21766781644 ps |
| CPU time | 1064.18 seconds |
| Started | Aug 21 03:45:36 PM UTC 24 |
| Finished | Aug 21 04:03:34 PM UTC 24 |
| Peak memory | 285836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3679477082 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3679477082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/25.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.3181548292 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 36977440560 ps |
| CPU time | 944.58 seconds |
| Started | Aug 21 03:45:37 PM UTC 24 |
| Finished | Aug 21 04:01:34 PM UTC 24 |
| Peak memory | 285584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3181548292 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_ stub_clk.3181548292 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.2505488470 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 9823856758 ps |
| CPU time | 85.35 seconds |
| Started | Aug 21 03:45:31 PM UTC 24 |
| Finished | Aug 21 03:46:59 PM UTC 24 |
| Peak memory | 267076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2505488470 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping _timeout.2505488470 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.3435800134 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 740158234 ps |
| CPU time | 57.16 seconds |
| Started | Aug 21 03:44:32 PM UTC 24 |
| Finished | Aug 21 03:45:31 PM UTC 24 |
| Peak memory | 269396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3435800134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3435800134 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.674154985 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 3636518302 ps |
| CPU time | 58.76 seconds |
| Started | Aug 21 03:44:39 PM UTC 24 |
| Finished | Aug 21 03:45:39 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=674154985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.674154985 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/25.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.1521561872 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1060897992 ps |
| CPU time | 54.42 seconds |
| Started | Aug 21 03:45:18 PM UTC 24 |
| Finished | Aug 21 03:46:15 PM UTC 24 |
| Peak memory | 262920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1521561872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1521561872 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.2009536640 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 3248250648 ps |
| CPU time | 43.61 seconds |
| Started | Aug 21 03:44:31 PM UTC 24 |
| Finished | Aug 21 03:45:16 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2009536640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2009536640 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/25.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.1513684336 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 178791353936 ps |
| CPU time | 2392.41 seconds |
| Started | Aug 21 03:45:40 PM UTC 24 |
| Finished | Aug 21 04:25:58 PM UTC 24 |
| Peak memory | 304688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15136 84336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 25.alert_handler_stress_all.1513684336 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/25.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all_with_rand_reset.3537836729 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 4019523746 ps |
| CPU time | 221.96 seconds |
| Started | Aug 21 03:46:08 PM UTC 24 |
| Finished | Aug 21 03:49:54 PM UTC 24 |
| Peak memory | 281620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=3537836729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3537836729 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/25.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.3243989674 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 16206074459 ps |
| CPU time | 1730.75 seconds |
| Started | Aug 21 03:47:08 PM UTC 24 |
| Finished | Aug 21 04:16:19 PM UTC 24 |
| Peak memory | 302036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3243989674 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3243989674 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/26.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.256784869 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1715698348 ps |
| CPU time | 40.24 seconds |
| Started | Aug 21 03:46:59 PM UTC 24 |
| Finished | Aug 21 03:47:40 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=256784869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.256784869 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.2167832369 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1427021684 ps |
| CPU time | 11.87 seconds |
| Started | Aug 21 03:46:56 PM UTC 24 |
| Finished | Aug 21 03:47:09 PM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2167832369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2167832369 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.1499169651 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 8005959815 ps |
| CPU time | 880.13 seconds |
| Started | Aug 21 03:47:12 PM UTC 24 |
| Finished | Aug 21 04:02:03 PM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1499169651 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1499169651 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/26.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.3748914519 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 64163088172 ps |
| CPU time | 1850.67 seconds |
| Started | Aug 21 03:47:13 PM UTC 24 |
| Finished | Aug 21 04:18:23 PM UTC 24 |
| Peak memory | 288300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3748914519 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_ stub_clk.3748914519 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.1207309099 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 8089865721 ps |
| CPU time | 255.61 seconds |
| Started | Aug 21 03:47:11 PM UTC 24 |
| Finished | Aug 21 03:51:30 PM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1207309099 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping _timeout.1207309099 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.2985075450 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 339722074 ps |
| CPU time | 26.03 seconds |
| Started | Aug 21 03:46:39 PM UTC 24 |
| Finished | Aug 21 03:47:07 PM UTC 24 |
| Peak memory | 263060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2985075450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2985075450 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.3748171210 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 464400914 ps |
| CPU time | 21.92 seconds |
| Started | Aug 21 03:46:49 PM UTC 24 |
| Finished | Aug 21 03:47:12 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3748171210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3748171210 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/26.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.670064474 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3215181379 ps |
| CPU time | 38.31 seconds |
| Started | Aug 21 03:47:00 PM UTC 24 |
| Finished | Aug 21 03:47:39 PM UTC 24 |
| Peak memory | 269204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=670064474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.670064474 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.1503891831 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 855391697 ps |
| CPU time | 38.91 seconds |
| Started | Aug 21 03:46:15 PM UTC 24 |
| Finished | Aug 21 03:46:56 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1503891831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1503891831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/26.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.2059301876 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 25596379600 ps |
| CPU time | 415.61 seconds |
| Started | Aug 21 03:47:19 PM UTC 24 |
| Finished | Aug 21 03:54:20 PM UTC 24 |
| Peak memory | 269456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20593 01876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 26.alert_handler_stress_all.2059301876 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/26.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.487015285 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 22714727844 ps |
| CPU time | 1078.95 seconds |
| Started | Aug 21 03:48:47 PM UTC 24 |
| Finished | Aug 21 04:06:59 PM UTC 24 |
| Peak memory | 285904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=487015285 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.487015285 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/27.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.560276489 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 4552730729 ps |
| CPU time | 113.42 seconds |
| Started | Aug 21 03:48:21 PM UTC 24 |
| Finished | Aug 21 03:50:17 PM UTC 24 |
| Peak memory | 269208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=560276489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.560276489 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.2595861023 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2789889109 ps |
| CPU time | 65.37 seconds |
| Started | Aug 21 03:48:12 PM UTC 24 |
| Finished | Aug 21 03:49:20 PM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2595861023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2595861023 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.636766792 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 166680847880 ps |
| CPU time | 2427.51 seconds |
| Started | Aug 21 03:48:52 PM UTC 24 |
| Finished | Aug 21 04:29:47 PM UTC 24 |
| Peak memory | 304636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=636766792 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.636766792 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/27.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.1380413868 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 209762447179 ps |
| CPU time | 2153.59 seconds |
| Started | Aug 21 03:49:07 PM UTC 24 |
| Finished | Aug 21 04:25:25 PM UTC 24 |
| Peak memory | 304944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1380413868 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_ stub_clk.1380413868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.2264167187 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 11672301758 ps |
| CPU time | 561.14 seconds |
| Started | Aug 21 03:48:50 PM UTC 24 |
| Finished | Aug 21 03:58:18 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2264167187 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping _timeout.2264167187 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.3894244731 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1957670788 ps |
| CPU time | 69.33 seconds |
| Started | Aug 21 03:47:40 PM UTC 24 |
| Finished | Aug 21 03:48:51 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3894244731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3894244731 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.1738795332 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 2944014544 ps |
| CPU time | 59.73 seconds |
| Started | Aug 21 03:47:41 PM UTC 24 |
| Finished | Aug 21 03:48:43 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1738795332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1738795332 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/27.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.2628336527 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 247503188 ps |
| CPU time | 21.9 seconds |
| Started | Aug 21 03:48:44 PM UTC 24 |
| Finished | Aug 21 03:49:07 PM UTC 24 |
| Peak memory | 267092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2628336527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2628336527 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.2533941429 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 561967030 ps |
| CPU time | 47.32 seconds |
| Started | Aug 21 03:47:23 PM UTC 24 |
| Finished | Aug 21 03:48:12 PM UTC 24 |
| Peak memory | 269396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2533941429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2533941429 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/27.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.1412731164 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 19068161723 ps |
| CPU time | 1450.54 seconds |
| Started | Aug 21 03:50:24 PM UTC 24 |
| Finished | Aug 21 04:14:52 PM UTC 24 |
| Peak memory | 301972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1412731164 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1412731164 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/28.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.155803825 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 17451358200 ps |
| CPU time | 258.48 seconds |
| Started | Aug 21 03:50:15 PM UTC 24 |
| Finished | Aug 21 03:54:37 PM UTC 24 |
| Peak memory | 269464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=155803825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.155803825 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.2686265251 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1138053376 ps |
| CPU time | 77.02 seconds |
| Started | Aug 21 03:49:55 PM UTC 24 |
| Finished | Aug 21 03:51:13 PM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2686265251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2686265251 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.3529702926 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 143651756686 ps |
| CPU time | 1093.15 seconds |
| Started | Aug 21 03:50:53 PM UTC 24 |
| Finished | Aug 21 04:09:19 PM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3529702926 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_ stub_clk.3529702926 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.3218388902 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 22566585769 ps |
| CPU time | 440.65 seconds |
| Started | Aug 21 03:50:48 PM UTC 24 |
| Finished | Aug 21 03:58:14 PM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3218388902 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping _timeout.3218388902 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.2098501653 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1187593518 ps |
| CPU time | 92.87 seconds |
| Started | Aug 21 03:49:33 PM UTC 24 |
| Finished | Aug 21 03:51:08 PM UTC 24 |
| Peak memory | 269396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2098501653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2098501653 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.2108766725 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 305699022 ps |
| CPU time | 26.64 seconds |
| Started | Aug 21 03:49:45 PM UTC 24 |
| Finished | Aug 21 03:50:13 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2108766725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2108766725 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/28.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.1046010312 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 83694089 ps |
| CPU time | 4.65 seconds |
| Started | Aug 21 03:50:18 PM UTC 24 |
| Finished | Aug 21 03:50:24 PM UTC 24 |
| Peak memory | 253008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1046010312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1046010312 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.2418380527 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 720069949 ps |
| CPU time | 17.3 seconds |
| Started | Aug 21 03:49:26 PM UTC 24 |
| Finished | Aug 21 03:49:45 PM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2418380527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2418380527 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/28.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.3811885140 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 163368506758 ps |
| CPU time | 3036 seconds |
| Started | Aug 21 03:51:09 PM UTC 24 |
| Finished | Aug 21 04:42:21 PM UTC 24 |
| Peak memory | 304612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38118 85140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 28.alert_handler_stress_all.3811885140 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/28.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all_with_rand_reset.2115958413 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1064364775 ps |
| CPU time | 46.3 seconds |
| Started | Aug 21 03:51:14 PM UTC 24 |
| Finished | Aug 21 03:52:02 PM UTC 24 |
| Peak memory | 279436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=2115958413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.2115958413 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.1820001006 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 59153398329 ps |
| CPU time | 1912.89 seconds |
| Started | Aug 21 03:52:18 PM UTC 24 |
| Finished | Aug 21 04:24:32 PM UTC 24 |
| Peak memory | 295764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1820001006 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1820001006 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/29.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.1435848889 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 5236131255 ps |
| CPU time | 214.59 seconds |
| Started | Aug 21 03:52:04 PM UTC 24 |
| Finished | Aug 21 03:55:42 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1435848889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1435848889 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.692469407 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 119940305 ps |
| CPU time | 10.26 seconds |
| Started | Aug 21 03:52:04 PM UTC 24 |
| Finished | Aug 21 03:52:16 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=692469407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.692469407 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.2996914562 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 36126531511 ps |
| CPU time | 932.27 seconds |
| Started | Aug 21 03:52:25 PM UTC 24 |
| Finished | Aug 21 04:08:09 PM UTC 24 |
| Peak memory | 285836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2996914562 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2996914562 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/29.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.3904889177 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 62072391146 ps |
| CPU time | 1141.27 seconds |
| Started | Aug 21 03:52:32 PM UTC 24 |
| Finished | Aug 21 04:11:46 PM UTC 24 |
| Peak memory | 301968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3904889177 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_ stub_clk.3904889177 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.2903500969 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 8758011853 ps |
| CPU time | 312.78 seconds |
| Started | Aug 21 03:52:22 PM UTC 24 |
| Finished | Aug 21 03:57:39 PM UTC 24 |
| Peak memory | 269200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2903500969 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping _timeout.2903500969 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.794801769 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 699179361 ps |
| CPU time | 50.68 seconds |
| Started | Aug 21 03:51:39 PM UTC 24 |
| Finished | Aug 21 03:52:31 PM UTC 24 |
| Peak memory | 269400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=794801769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.794801769 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.1770269064 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 946725254 ps |
| CPU time | 22.01 seconds |
| Started | Aug 21 03:51:58 PM UTC 24 |
| Finished | Aug 21 03:52:21 PM UTC 24 |
| Peak memory | 267352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1770269064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1770269064 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/29.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.1690394533 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1720431689 ps |
| CPU time | 25.91 seconds |
| Started | Aug 21 03:52:16 PM UTC 24 |
| Finished | Aug 21 03:52:44 PM UTC 24 |
| Peak memory | 269456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1690394533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1690394533 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.489155968 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 554268161 ps |
| CPU time | 51.13 seconds |
| Started | Aug 21 03:51:30 PM UTC 24 |
| Finished | Aug 21 03:52:24 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=489155968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.489155968 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/29.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.1784827292 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 70646048787 ps |
| CPU time | 4222.26 seconds |
| Started | Aug 21 03:52:39 PM UTC 24 |
| Finished | Aug 21 05:03:48 PM UTC 24 |
| Peak memory | 317040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17848 27292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 29.alert_handler_stress_all.1784827292 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/29.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.3380804985 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 29461664 ps |
| CPU time | 3.72 seconds |
| Started | Aug 21 03:08:02 PM UTC 24 |
| Finished | Aug 21 03:08:07 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3380804985 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_satu ration.3380804985 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.3504152037 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 13828859217 ps |
| CPU time | 774.74 seconds |
| Started | Aug 21 03:08:01 PM UTC 24 |
| Finished | Aug 21 03:21:05 PM UTC 24 |
| Peak memory | 285584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3504152037 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3504152037 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.661512862 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 111006523 ps |
| CPU time | 11.74 seconds |
| Started | Aug 21 03:08:02 PM UTC 24 |
| Finished | Aug 21 03:08:15 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=661512862 -assert nopostproc +UVM_TESTNAME=alert_handler _base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.661512862 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.1158449654 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 200306199 ps |
| CPU time | 16 seconds |
| Started | Aug 21 03:07:59 PM UTC 24 |
| Finished | Aug 21 03:08:16 PM UTC 24 |
| Peak memory | 269144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1158449654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1158449654 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.1398139670 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 74057862800 ps |
| CPU time | 2320.81 seconds |
| Started | Aug 21 03:08:01 PM UTC 24 |
| Finished | Aug 21 03:47:08 PM UTC 24 |
| Peak memory | 304164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1398139670 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_s tub_clk.1398139670 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.3964621662 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 9599582600 ps |
| CPU time | 361.51 seconds |
| Started | Aug 21 03:08:01 PM UTC 24 |
| Finished | Aug 21 03:14:07 PM UTC 24 |
| Peak memory | 263320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3964621662 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_ timeout.3964621662 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.253365942 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 702292795 ps |
| CPU time | 33.43 seconds |
| Started | Aug 21 03:07:58 PM UTC 24 |
| Finished | Aug 21 03:08:33 PM UTC 24 |
| Peak memory | 269464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=253365942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.253365942 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.1266907741 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 582231435 ps |
| CPU time | 35.09 seconds |
| Started | Aug 21 03:07:58 PM UTC 24 |
| Finished | Aug 21 03:08:34 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1266907741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1266907741 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.1858230385 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 2363844091 ps |
| CPU time | 21.08 seconds |
| Started | Aug 21 03:08:02 PM UTC 24 |
| Finished | Aug 21 03:08:25 PM UTC 24 |
| Peak memory | 295344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1858230385 -assert nopostproc +UVM_TESTNA ME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1858230385 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.873343939 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 820451613 ps |
| CPU time | 28.47 seconds |
| Started | Aug 21 03:07:58 PM UTC 24 |
| Finished | Aug 21 03:08:28 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=873343939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.873343939 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.721514399 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 68326377958 ps |
| CPU time | 2206.19 seconds |
| Started | Aug 21 03:08:02 PM UTC 24 |
| Finished | Aug 21 03:45:15 PM UTC 24 |
| Peak memory | 304620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=72151 4399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 3.alert_handler_stress_all.721514399 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all_with_rand_reset.1750644488 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 33250714626 ps |
| CPU time | 364.78 seconds |
| Started | Aug 21 03:08:02 PM UTC 24 |
| Finished | Aug 21 03:14:12 PM UTC 24 |
| Peak memory | 281620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=1750644488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1750644488 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.473907021 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 6948933271 ps |
| CPU time | 596.17 seconds |
| Started | Aug 21 03:54:30 PM UTC 24 |
| Finished | Aug 21 04:04:34 PM UTC 24 |
| Peak memory | 279368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=473907021 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.473907021 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/30.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.2743569919 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 2151079951 ps |
| CPU time | 179.62 seconds |
| Started | Aug 21 03:54:21 PM UTC 24 |
| Finished | Aug 21 03:57:24 PM UTC 24 |
| Peak memory | 269208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2743569919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2743569919 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.1810953309 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 234033993 ps |
| CPU time | 25.67 seconds |
| Started | Aug 21 03:54:12 PM UTC 24 |
| Finished | Aug 21 03:54:39 PM UTC 24 |
| Peak memory | 262916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1810953309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1810953309 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.2829498663 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 18150491399 ps |
| CPU time | 798.3 seconds |
| Started | Aug 21 03:54:40 PM UTC 24 |
| Finished | Aug 21 04:08:08 PM UTC 24 |
| Peak memory | 285580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2829498663 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2829498663 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/30.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.3534234427 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 74473349987 ps |
| CPU time | 2896.33 seconds |
| Started | Aug 21 03:54:41 PM UTC 24 |
| Finished | Aug 21 04:43:32 PM UTC 24 |
| Peak memory | 304612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3534234427 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_ stub_clk.3534234427 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.4063331346 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 21744469620 ps |
| CPU time | 318.6 seconds |
| Started | Aug 21 03:54:38 PM UTC 24 |
| Finished | Aug 21 04:00:01 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4063331346 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping _timeout.4063331346 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.4002534635 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 832260714 ps |
| CPU time | 35.49 seconds |
| Started | Aug 21 03:53:18 PM UTC 24 |
| Finished | Aug 21 03:53:55 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4002534635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4002534635 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.2189679314 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 522086717 ps |
| CPU time | 42.3 seconds |
| Started | Aug 21 03:53:56 PM UTC 24 |
| Finished | Aug 21 03:54:40 PM UTC 24 |
| Peak memory | 263128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2189679314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2189679314 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/30.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.2567184806 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 629215312 ps |
| CPU time | 36.1 seconds |
| Started | Aug 21 03:54:30 PM UTC 24 |
| Finished | Aug 21 03:55:08 PM UTC 24 |
| Peak memory | 262920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2567184806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2567184806 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.2891935633 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1628099841 ps |
| CPU time | 10.42 seconds |
| Started | Aug 21 03:53:05 PM UTC 24 |
| Finished | Aug 21 03:53:16 PM UTC 24 |
| Peak memory | 265044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2891935633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2891935633 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/30.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.2269690614 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 8267256426 ps |
| CPU time | 311.56 seconds |
| Started | Aug 21 03:54:55 PM UTC 24 |
| Finished | Aug 21 04:00:11 PM UTC 24 |
| Peak memory | 269520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22696 90614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 30.alert_handler_stress_all.2269690614 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/30.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.1328043304 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 103252532176 ps |
| CPU time | 1888.88 seconds |
| Started | Aug 21 03:56:48 PM UTC 24 |
| Finished | Aug 21 04:28:38 PM UTC 24 |
| Peak memory | 286984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1328043304 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1328043304 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/31.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.656492960 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 6461862927 ps |
| CPU time | 108.46 seconds |
| Started | Aug 21 03:56:31 PM UTC 24 |
| Finished | Aug 21 03:58:22 PM UTC 24 |
| Peak memory | 269208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=656492960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.656492960 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.2865644452 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 165811639 ps |
| CPU time | 24.17 seconds |
| Started | Aug 21 03:56:21 PM UTC 24 |
| Finished | Aug 21 03:56:47 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2865644452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2865644452 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.2820103189 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 70704747256 ps |
| CPU time | 1621.37 seconds |
| Started | Aug 21 03:57:25 PM UTC 24 |
| Finished | Aug 21 04:24:45 PM UTC 24 |
| Peak memory | 301892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2820103189 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2820103189 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/31.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.4270803144 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 25075458403 ps |
| CPU time | 1263.29 seconds |
| Started | Aug 21 03:57:29 PM UTC 24 |
| Finished | Aug 21 04:18:47 PM UTC 24 |
| Peak memory | 297800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4270803144 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_ stub_clk.4270803144 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.558175615 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 12733745801 ps |
| CPU time | 111.78 seconds |
| Started | Aug 21 03:56:54 PM UTC 24 |
| Finished | Aug 21 03:58:48 PM UTC 24 |
| Peak memory | 263380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=558175615 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_ timeout.558175615 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.3537212006 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 968499269 ps |
| CPU time | 43.52 seconds |
| Started | Aug 21 03:55:59 PM UTC 24 |
| Finished | Aug 21 03:56:44 PM UTC 24 |
| Peak memory | 269396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3537212006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3537212006 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.3484182554 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2204438968 ps |
| CPU time | 42.47 seconds |
| Started | Aug 21 03:56:44 PM UTC 24 |
| Finished | Aug 21 03:57:28 PM UTC 24 |
| Peak memory | 269200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3484182554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3484182554 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.3290408327 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 355661666 ps |
| CPU time | 26.76 seconds |
| Started | Aug 21 03:55:43 PM UTC 24 |
| Finished | Aug 21 03:56:12 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3290408327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3290408327 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/31.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.2658550844 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 93178283737 ps |
| CPU time | 2825.07 seconds |
| Started | Aug 21 03:59:11 PM UTC 24 |
| Finished | Aug 21 04:46:47 PM UTC 24 |
| Peak memory | 304632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2658550844 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2658550844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/32.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.2613497731 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 5000674887 ps |
| CPU time | 102.44 seconds |
| Started | Aug 21 03:59:07 PM UTC 24 |
| Finished | Aug 21 04:00:52 PM UTC 24 |
| Peak memory | 269208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2613497731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2613497731 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.3999988700 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1180837367 ps |
| CPU time | 33.81 seconds |
| Started | Aug 21 03:58:49 PM UTC 24 |
| Finished | Aug 21 03:59:26 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3999988700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3999988700 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.3631789471 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 11059894014 ps |
| CPU time | 1170.15 seconds |
| Started | Aug 21 03:59:28 PM UTC 24 |
| Finished | Aug 21 04:19:12 PM UTC 24 |
| Peak memory | 301964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3631789471 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3631789471 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/32.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.4174351621 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 9747242056 ps |
| CPU time | 267.61 seconds |
| Started | Aug 21 03:59:23 PM UTC 24 |
| Finished | Aug 21 04:03:55 PM UTC 24 |
| Peak memory | 263056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4174351621 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping _timeout.4174351621 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.3165940531 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2419727057 ps |
| CPU time | 49.83 seconds |
| Started | Aug 21 03:58:19 PM UTC 24 |
| Finished | Aug 21 03:59:10 PM UTC 24 |
| Peak memory | 269132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3165940531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3165940531 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.2531083610 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1954335528 ps |
| CPU time | 45.22 seconds |
| Started | Aug 21 03:58:22 PM UTC 24 |
| Finished | Aug 21 03:59:09 PM UTC 24 |
| Peak memory | 262928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2531083610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2531083610 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/32.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.1626790186 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 597766819 ps |
| CPU time | 60.96 seconds |
| Started | Aug 21 03:59:10 PM UTC 24 |
| Finished | Aug 21 04:00:13 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1626790186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1626790186 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.1335010717 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 714504394 ps |
| CPU time | 65.12 seconds |
| Started | Aug 21 03:58:15 PM UTC 24 |
| Finished | Aug 21 03:59:22 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1335010717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1335010717 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/32.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.1609346407 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 41871486361 ps |
| CPU time | 1521.31 seconds |
| Started | Aug 21 03:59:34 PM UTC 24 |
| Finished | Aug 21 04:25:13 PM UTC 24 |
| Peak memory | 314180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16093 46407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 32.alert_handler_stress_all.1609346407 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/32.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all_with_rand_reset.686500285 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 4239467709 ps |
| CPU time | 66.21 seconds |
| Started | Aug 21 04:00:02 PM UTC 24 |
| Finished | Aug 21 04:01:13 PM UTC 24 |
| Peak memory | 279496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=686500285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.686500285 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/33.alert_handler_entropy.1764607852 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 32334444671 ps |
| CPU time | 1924.82 seconds |
| Started | Aug 21 04:00:53 PM UTC 24 |
| Finished | Aug 21 04:33:18 PM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1764607852 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1764607852 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/33.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.4091564673 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 543021093 ps |
| CPU time | 67.84 seconds |
| Started | Aug 21 04:00:37 PM UTC 24 |
| Finished | Aug 21 04:01:47 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4091564673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.4091564673 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.656231497 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 736371855 ps |
| CPU time | 60.54 seconds |
| Started | Aug 21 04:00:36 PM UTC 24 |
| Finished | Aug 21 04:01:39 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=656231497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.656231497 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.3802008870 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 13848046743 ps |
| CPU time | 1462.92 seconds |
| Started | Aug 21 04:01:22 PM UTC 24 |
| Finished | Aug 21 04:26:03 PM UTC 24 |
| Peak memory | 301964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3802008870 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3802008870 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/33.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.4035865059 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 30502140303 ps |
| CPU time | 1610.43 seconds |
| Started | Aug 21 04:01:36 PM UTC 24 |
| Finished | Aug 21 04:28:45 PM UTC 24 |
| Peak memory | 285520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4035865059 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_ stub_clk.4035865059 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.1459420037 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 18374148322 ps |
| CPU time | 278.05 seconds |
| Started | Aug 21 04:01:14 PM UTC 24 |
| Finished | Aug 21 04:05:56 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1459420037 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping _timeout.1459420037 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.2689727016 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 314999304 ps |
| CPU time | 8.88 seconds |
| Started | Aug 21 04:00:13 PM UTC 24 |
| Finished | Aug 21 04:00:23 PM UTC 24 |
| Peak memory | 264972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2689727016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2689727016 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.304685658 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 94285214 ps |
| CPU time | 10.61 seconds |
| Started | Aug 21 04:00:24 PM UTC 24 |
| Finished | Aug 21 04:00:36 PM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=304685658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.304685658 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/33.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.1194114531 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 2239873970 ps |
| CPU time | 96.73 seconds |
| Started | Aug 21 04:00:53 PM UTC 24 |
| Finished | Aug 21 04:02:32 PM UTC 24 |
| Peak memory | 269460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1194114531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1194114531 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.433373575 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 936801193 ps |
| CPU time | 38.32 seconds |
| Started | Aug 21 04:00:12 PM UTC 24 |
| Finished | Aug 21 04:00:52 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=433373575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.433373575 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/33.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.2508787601 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 35330788583 ps |
| CPU time | 1775.06 seconds |
| Started | Aug 21 04:02:33 PM UTC 24 |
| Finished | Aug 21 04:32:28 PM UTC 24 |
| Peak memory | 301896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2508787601 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2508787601 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/34.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.3140194074 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2809036765 ps |
| CPU time | 64.79 seconds |
| Started | Aug 21 04:02:05 PM UTC 24 |
| Finished | Aug 21 04:03:12 PM UTC 24 |
| Peak memory | 269200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3140194074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3140194074 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.2027311923 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1805090494 ps |
| CPU time | 67.66 seconds |
| Started | Aug 21 04:02:04 PM UTC 24 |
| Finished | Aug 21 04:03:14 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2027311923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2027311923 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.1272930701 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 156664057657 ps |
| CPU time | 2580.61 seconds |
| Started | Aug 21 04:03:13 PM UTC 24 |
| Finished | Aug 21 04:46:43 PM UTC 24 |
| Peak memory | 302564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1272930701 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1272930701 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/34.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.3328274935 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 72418049992 ps |
| CPU time | 1642.97 seconds |
| Started | Aug 21 04:03:16 PM UTC 24 |
| Finished | Aug 21 04:30:58 PM UTC 24 |
| Peak memory | 302096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3328274935 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_ stub_clk.3328274935 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.2291527850 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 6638443326 ps |
| CPU time | 214.92 seconds |
| Started | Aug 21 04:02:53 PM UTC 24 |
| Finished | Aug 21 04:06:31 PM UTC 24 |
| Peak memory | 263056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2291527850 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping _timeout.2291527850 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.3128686484 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 256804105 ps |
| CPU time | 8.19 seconds |
| Started | Aug 21 04:01:49 PM UTC 24 |
| Finished | Aug 21 04:01:58 PM UTC 24 |
| Peak memory | 262928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3128686484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3128686484 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.345714817 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 116151896 ps |
| CPU time | 19.99 seconds |
| Started | Aug 21 04:01:59 PM UTC 24 |
| Finished | Aug 21 04:02:20 PM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=345714817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.345714817 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/34.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.4150864377 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 403599516 ps |
| CPU time | 14.07 seconds |
| Started | Aug 21 04:01:49 PM UTC 24 |
| Finished | Aug 21 04:02:04 PM UTC 24 |
| Peak memory | 269396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4150864377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.4150864377 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/34.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.1052416206 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 37814797558 ps |
| CPU time | 577.68 seconds |
| Started | Aug 21 04:03:17 PM UTC 24 |
| Finished | Aug 21 04:13:02 PM UTC 24 |
| Peak memory | 279696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10524 16206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 34.alert_handler_stress_all.1052416206 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/34.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.1078001914 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 53093478840 ps |
| CPU time | 1094.85 seconds |
| Started | Aug 21 04:04:32 PM UTC 24 |
| Finished | Aug 21 04:23:00 PM UTC 24 |
| Peak memory | 295752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1078001914 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1078001914 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/35.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.2268701854 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 4314260204 ps |
| CPU time | 106.86 seconds |
| Started | Aug 21 04:04:24 PM UTC 24 |
| Finished | Aug 21 04:06:13 PM UTC 24 |
| Peak memory | 269208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2268701854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2268701854 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.1613748405 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1426498742 ps |
| CPU time | 15.45 seconds |
| Started | Aug 21 04:04:10 PM UTC 24 |
| Finished | Aug 21 04:04:27 PM UTC 24 |
| Peak memory | 269060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1613748405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1613748405 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.4221005508 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 37901281121 ps |
| CPU time | 1526.85 seconds |
| Started | Aug 21 04:04:35 PM UTC 24 |
| Finished | Aug 21 04:30:19 PM UTC 24 |
| Peak memory | 301892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4221005508 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.4221005508 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/35.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.1358987429 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 140357459551 ps |
| CPU time | 1889.52 seconds |
| Started | Aug 21 04:04:44 PM UTC 24 |
| Finished | Aug 21 04:36:34 PM UTC 24 |
| Peak memory | 288304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1358987429 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_ stub_clk.1358987429 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.3697985909 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 11209821838 ps |
| CPU time | 106.94 seconds |
| Started | Aug 21 04:04:32 PM UTC 24 |
| Finished | Aug 21 04:06:21 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3697985909 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping _timeout.3697985909 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.911345880 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 412414914 ps |
| CPU time | 34.1 seconds |
| Started | Aug 21 04:03:56 PM UTC 24 |
| Finished | Aug 21 04:04:31 PM UTC 24 |
| Peak memory | 263192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=911345880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.911345880 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.4039501339 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 234498873 ps |
| CPU time | 32.56 seconds |
| Started | Aug 21 04:04:09 PM UTC 24 |
| Finished | Aug 21 04:04:43 PM UTC 24 |
| Peak memory | 269080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4039501339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.4039501339 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/35.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.2409912962 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 128208251 ps |
| CPU time | 22.99 seconds |
| Started | Aug 21 04:04:28 PM UTC 24 |
| Finished | Aug 21 04:04:52 PM UTC 24 |
| Peak memory | 269392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2409912962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2409912962 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.3612266683 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 610821133 ps |
| CPU time | 31.37 seconds |
| Started | Aug 21 04:03:36 PM UTC 24 |
| Finished | Aug 21 04:04:09 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3612266683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3612266683 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/35.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.4207050010 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 2954342385 ps |
| CPU time | 66.58 seconds |
| Started | Aug 21 04:04:53 PM UTC 24 |
| Finished | Aug 21 04:06:02 PM UTC 24 |
| Peak memory | 269124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42070 50010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 35.alert_handler_stress_all.4207050010 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/35.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all_with_rand_reset.3500689484 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 19006594990 ps |
| CPU time | 515.39 seconds |
| Started | Aug 21 04:05:12 PM UTC 24 |
| Finished | Aug 21 04:13:53 PM UTC 24 |
| Peak memory | 285716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=3500689484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3500689484 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.3737501850 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 142615605755 ps |
| CPU time | 2332.78 seconds |
| Started | Aug 21 04:06:15 PM UTC 24 |
| Finished | Aug 21 04:45:34 PM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3737501850 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3737501850 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/36.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.3536658020 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 3347915861 ps |
| CPU time | 138.69 seconds |
| Started | Aug 21 04:06:12 PM UTC 24 |
| Finished | Aug 21 04:08:33 PM UTC 24 |
| Peak memory | 269208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3536658020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3536658020 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.4251400235 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 962261159 ps |
| CPU time | 25.56 seconds |
| Started | Aug 21 04:06:03 PM UTC 24 |
| Finished | Aug 21 04:06:30 PM UTC 24 |
| Peak memory | 269060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4251400235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.4251400235 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg.2762605688 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 29545722366 ps |
| CPU time | 676.06 seconds |
| Started | Aug 21 04:06:31 PM UTC 24 |
| Finished | Aug 21 04:17:55 PM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2762605688 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2762605688 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/36.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.1318881250 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 10145921966 ps |
| CPU time | 988.37 seconds |
| Started | Aug 21 04:06:32 PM UTC 24 |
| Finished | Aug 21 04:23:12 PM UTC 24 |
| Peak memory | 301892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1318881250 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_ stub_clk.1318881250 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.469236449 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 50614227723 ps |
| CPU time | 374.57 seconds |
| Started | Aug 21 04:06:23 PM UTC 24 |
| Finished | Aug 21 04:12:42 PM UTC 24 |
| Peak memory | 262988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=469236449 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_ timeout.469236449 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.2202499743 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 247284177 ps |
| CPU time | 19.32 seconds |
| Started | Aug 21 04:05:51 PM UTC 24 |
| Finished | Aug 21 04:06:11 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2202499743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2202499743 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.3927003747 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 956004839 ps |
| CPU time | 34.37 seconds |
| Started | Aug 21 04:05:57 PM UTC 24 |
| Finished | Aug 21 04:06:33 PM UTC 24 |
| Peak memory | 263000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3927003747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3927003747 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/36.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.3907224021 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 243837308 ps |
| CPU time | 23.39 seconds |
| Started | Aug 21 04:06:14 PM UTC 24 |
| Finished | Aug 21 04:06:39 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3907224021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3907224021 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.349496507 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 69771436 ps |
| CPU time | 11.68 seconds |
| Started | Aug 21 04:05:38 PM UTC 24 |
| Finished | Aug 21 04:05:50 PM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=349496507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.349496507 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/36.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.4287446585 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 39659816991 ps |
| CPU time | 2227.64 seconds |
| Started | Aug 21 04:06:33 PM UTC 24 |
| Finished | Aug 21 04:44:05 PM UTC 24 |
| Peak memory | 298468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42874 46585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 36.alert_handler_stress_all.4287446585 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/36.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.1522200104 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 104043669873 ps |
| CPU time | 1897.47 seconds |
| Started | Aug 21 04:07:50 PM UTC 24 |
| Finished | Aug 21 04:39:50 PM UTC 24 |
| Peak memory | 295756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1522200104 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1522200104 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/37.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.2087119556 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 1389717144 ps |
| CPU time | 145.38 seconds |
| Started | Aug 21 04:07:39 PM UTC 24 |
| Finished | Aug 21 04:10:07 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2087119556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2087119556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.1117127495 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 1424460213 ps |
| CPU time | 30.21 seconds |
| Started | Aug 21 04:07:29 PM UTC 24 |
| Finished | Aug 21 04:08:01 PM UTC 24 |
| Peak memory | 269456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1117127495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1117127495 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.2629670735 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 29010468493 ps |
| CPU time | 1605.65 seconds |
| Started | Aug 21 04:08:09 PM UTC 24 |
| Finished | Aug 21 04:35:14 PM UTC 24 |
| Peak memory | 302220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2629670735 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2629670735 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/37.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.1834636394 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 10347990967 ps |
| CPU time | 1278.59 seconds |
| Started | Aug 21 04:08:11 PM UTC 24 |
| Finished | Aug 21 04:29:45 PM UTC 24 |
| Peak memory | 301968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1834636394 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_ stub_clk.1834636394 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.386600514 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 31576421238 ps |
| CPU time | 435.7 seconds |
| Started | Aug 21 04:08:02 PM UTC 24 |
| Finished | Aug 21 04:15:24 PM UTC 24 |
| Peak memory | 263124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=386600514 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_ timeout.386600514 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.3165631911 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 931708594 ps |
| CPU time | 76.72 seconds |
| Started | Aug 21 04:07:01 PM UTC 24 |
| Finished | Aug 21 04:08:19 PM UTC 24 |
| Peak memory | 269396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3165631911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3165631911 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.1353740978 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 695430679 ps |
| CPU time | 25.26 seconds |
| Started | Aug 21 04:07:12 PM UTC 24 |
| Finished | Aug 21 04:07:38 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1353740978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1353740978 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/37.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.2761002898 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 238722145 ps |
| CPU time | 6.04 seconds |
| Started | Aug 21 04:07:42 PM UTC 24 |
| Finished | Aug 21 04:07:49 PM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2761002898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2761002898 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.773034560 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 170624694 ps |
| CPU time | 24.41 seconds |
| Started | Aug 21 04:06:45 PM UTC 24 |
| Finished | Aug 21 04:07:11 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=773034560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.773034560 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/37.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.518858340 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 19475621363 ps |
| CPU time | 1823.23 seconds |
| Started | Aug 21 04:08:20 PM UTC 24 |
| Finished | Aug 21 04:39:04 PM UTC 24 |
| Peak memory | 312140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=51885 8340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 37.alert_handler_stress_all.518858340 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/37.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all_with_rand_reset.4091402504 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 4417750393 ps |
| CPU time | 604.21 seconds |
| Started | Aug 21 04:08:34 PM UTC 24 |
| Finished | Aug 21 04:18:47 PM UTC 24 |
| Peak memory | 283596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=4091402504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.4091402504 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.2549347203 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 31192540351 ps |
| CPU time | 1538.41 seconds |
| Started | Aug 21 04:09:59 PM UTC 24 |
| Finished | Aug 21 04:35:55 PM UTC 24 |
| Peak memory | 285720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2549347203 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2549347203 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/38.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.2967123471 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 5762390739 ps |
| CPU time | 215.48 seconds |
| Started | Aug 21 04:09:33 PM UTC 24 |
| Finished | Aug 21 04:13:12 PM UTC 24 |
| Peak memory | 269132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2967123471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2967123471 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.310099013 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1578682862 ps |
| CPU time | 37.31 seconds |
| Started | Aug 21 04:09:20 PM UTC 24 |
| Finished | Aug 21 04:09:59 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=310099013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.310099013 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.2423700149 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 242132572886 ps |
| CPU time | 1604.42 seconds |
| Started | Aug 21 04:10:07 PM UTC 24 |
| Finished | Aug 21 04:37:11 PM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2423700149 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2423700149 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/38.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.1571628852 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 22744853632 ps |
| CPU time | 1450.79 seconds |
| Started | Aug 21 04:10:28 PM UTC 24 |
| Finished | Aug 21 04:34:56 PM UTC 24 |
| Peak memory | 285512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1571628852 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_ stub_clk.1571628852 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.631850364 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 54845692963 ps |
| CPU time | 676.95 seconds |
| Started | Aug 21 04:10:00 PM UTC 24 |
| Finished | Aug 21 04:21:25 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=631850364 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_ timeout.631850364 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.155287209 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1769928634 ps |
| CPU time | 37.25 seconds |
| Started | Aug 21 04:08:53 PM UTC 24 |
| Finished | Aug 21 04:09:32 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=155287209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.155287209 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.4149127838 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 330370047 ps |
| CPU time | 38.85 seconds |
| Started | Aug 21 04:09:18 PM UTC 24 |
| Finished | Aug 21 04:09:58 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4149127838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.4149127838 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/38.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.3168266499 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 1825937497 ps |
| CPU time | 38.25 seconds |
| Started | Aug 21 04:09:47 PM UTC 24 |
| Finished | Aug 21 04:10:27 PM UTC 24 |
| Peak memory | 269200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3168266499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3168266499 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.710138096 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 37597568 ps |
| CPU time | 4.03 seconds |
| Started | Aug 21 04:08:47 PM UTC 24 |
| Finished | Aug 21 04:08:52 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=710138096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.710138096 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/38.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.1640648169 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 281881839681 ps |
| CPU time | 2687.8 seconds |
| Started | Aug 21 04:10:46 PM UTC 24 |
| Finished | Aug 21 04:56:04 PM UTC 24 |
| Peak memory | 317040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16406 48169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 38.alert_handler_stress_all.1640648169 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/38.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all_with_rand_reset.4004744890 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 11078272323 ps |
| CPU time | 390.59 seconds |
| Started | Aug 21 04:11:48 PM UTC 24 |
| Finished | Aug 21 04:18:24 PM UTC 24 |
| Peak memory | 281620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=4004744890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.4004744890 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/38.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.4076411588 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 22878337438 ps |
| CPU time | 1616.49 seconds |
| Started | Aug 21 04:12:59 PM UTC 24 |
| Finished | Aug 21 04:40:14 PM UTC 24 |
| Peak memory | 285512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4076411588 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.4076411588 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/39.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.1685533291 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 7151292885 ps |
| CPU time | 179.64 seconds |
| Started | Aug 21 04:12:42 PM UTC 24 |
| Finished | Aug 21 04:15:45 PM UTC 24 |
| Peak memory | 269132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1685533291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1685533291 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.3032415138 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 372816763 ps |
| CPU time | 44.36 seconds |
| Started | Aug 21 04:12:40 PM UTC 24 |
| Finished | Aug 21 04:13:26 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3032415138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3032415138 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.3568747767 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 80743341954 ps |
| CPU time | 1579.77 seconds |
| Started | Aug 21 04:13:19 PM UTC 24 |
| Finished | Aug 21 04:39:57 PM UTC 24 |
| Peak memory | 285512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3568747767 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_ stub_clk.3568747767 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.2104183346 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 19615950192 ps |
| CPU time | 351.6 seconds |
| Started | Aug 21 04:13:03 PM UTC 24 |
| Finished | Aug 21 04:18:59 PM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2104183346 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping _timeout.2104183346 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.613394462 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1462515923 ps |
| CPU time | 46.11 seconds |
| Started | Aug 21 04:12:00 PM UTC 24 |
| Finished | Aug 21 04:12:48 PM UTC 24 |
| Peak memory | 263000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=613394462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.613394462 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.2292070726 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 559783138 ps |
| CPU time | 19.69 seconds |
| Started | Aug 21 04:12:36 PM UTC 24 |
| Finished | Aug 21 04:12:58 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2292070726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2292070726 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/39.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.608457427 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 431326781 ps |
| CPU time | 28.17 seconds |
| Started | Aug 21 04:12:49 PM UTC 24 |
| Finished | Aug 21 04:13:18 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=608457427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.608457427 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.3288511117 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 540334044 ps |
| CPU time | 37.69 seconds |
| Started | Aug 21 04:11:56 PM UTC 24 |
| Finished | Aug 21 04:12:35 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3288511117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3288511117 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/39.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.1759991681 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 34046919704 ps |
| CPU time | 2112.76 seconds |
| Started | Aug 21 04:13:27 PM UTC 24 |
| Finished | Aug 21 04:49:03 PM UTC 24 |
| Peak memory | 304688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17599 91681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 39.alert_handler_stress_all.1759991681 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/39.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.2416304241 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 28013695 ps |
| CPU time | 3.59 seconds |
| Started | Aug 21 03:08:10 PM UTC 24 |
| Finished | Aug 21 03:08:15 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2416304241 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_satu ration.2416304241 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.3012142226 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 45570074787 ps |
| CPU time | 1122.27 seconds |
| Started | Aug 21 03:08:06 PM UTC 24 |
| Finished | Aug 21 03:27:01 PM UTC 24 |
| Peak memory | 299848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3012142226 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3012142226 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.1209381103 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 257549192 ps |
| CPU time | 15.51 seconds |
| Started | Aug 21 03:08:08 PM UTC 24 |
| Finished | Aug 21 03:08:25 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1209381103 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1209381103 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.447259963 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 26147565338 ps |
| CPU time | 419.88 seconds |
| Started | Aug 21 03:08:05 PM UTC 24 |
| Finished | Aug 21 03:15:11 PM UTC 24 |
| Peak memory | 269464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=447259963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.447259963 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.2999545927 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 149768119426 ps |
| CPU time | 2528.66 seconds |
| Started | Aug 21 03:08:08 PM UTC 24 |
| Finished | Aug 21 03:50:46 PM UTC 24 |
| Peak memory | 300600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2999545927 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_s tub_clk.2999545927 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.40593857 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 13450777343 ps |
| CPU time | 522.54 seconds |
| Started | Aug 21 03:08:07 PM UTC 24 |
| Finished | Aug 21 03:16:56 PM UTC 24 |
| Peak memory | 263056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40593857 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_ti meout.40593857 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.1891813725 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1369836488 ps |
| CPU time | 16.72 seconds |
| Started | Aug 21 03:08:03 PM UTC 24 |
| Finished | Aug 21 03:08:20 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1891813725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1891813725 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.2932094096 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 646771581 ps |
| CPU time | 23.3 seconds |
| Started | Aug 21 03:08:04 PM UTC 24 |
| Finished | Aug 21 03:08:28 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2932094096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2932094096 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.1947369950 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 877053879 ps |
| CPU time | 23.78 seconds |
| Started | Aug 21 03:08:14 PM UTC 24 |
| Finished | Aug 21 03:08:39 PM UTC 24 |
| Peak memory | 295352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1947369950 -assert nopostproc +UVM_TESTNA ME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1947369950 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.337978118 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1213662950 ps |
| CPU time | 33.83 seconds |
| Started | Aug 21 03:08:05 PM UTC 24 |
| Finished | Aug 21 03:08:40 PM UTC 24 |
| Peak memory | 269144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=337978118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.337978118 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.1233504516 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3550545356 ps |
| CPU time | 46.63 seconds |
| Started | Aug 21 03:08:02 PM UTC 24 |
| Finished | Aug 21 03:08:51 PM UTC 24 |
| Peak memory | 269132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1233504516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1233504516 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all_with_rand_reset.3867431620 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 6933548372 ps |
| CPU time | 126.4 seconds |
| Started | Aug 21 03:08:13 PM UTC 24 |
| Finished | Aug 21 03:10:21 PM UTC 24 |
| Peak memory | 283988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=3867431620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3867431620 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.348904916 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 61506721659 ps |
| CPU time | 1928.48 seconds |
| Started | Aug 21 04:14:57 PM UTC 24 |
| Finished | Aug 21 04:47:28 PM UTC 24 |
| Peak memory | 288368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=348904916 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.348904916 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/40.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.315252074 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 2914788259 ps |
| CPU time | 239.1 seconds |
| Started | Aug 21 04:14:35 PM UTC 24 |
| Finished | Aug 21 04:18:38 PM UTC 24 |
| Peak memory | 269208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=315252074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.315252074 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.2502575261 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 2989727016 ps |
| CPU time | 27.66 seconds |
| Started | Aug 21 04:14:27 PM UTC 24 |
| Finished | Aug 21 04:14:56 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2502575261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2502575261 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.3037700499 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 93332312701 ps |
| CPU time | 1513.18 seconds |
| Started | Aug 21 04:15:24 PM UTC 24 |
| Finished | Aug 21 04:40:54 PM UTC 24 |
| Peak memory | 285580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3037700499 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3037700499 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/40.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.1364335079 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 24699670159 ps |
| CPU time | 2006.62 seconds |
| Started | Aug 21 04:15:26 PM UTC 24 |
| Finished | Aug 21 04:49:17 PM UTC 24 |
| Peak memory | 300592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1364335079 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_ stub_clk.1364335079 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.4114387696 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 8101105116 ps |
| CPU time | 410.7 seconds |
| Started | Aug 21 04:15:24 PM UTC 24 |
| Finished | Aug 21 04:22:21 PM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4114387696 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping _timeout.4114387696 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.1651594317 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 77787826 ps |
| CPU time | 5.48 seconds |
| Started | Aug 21 04:14:19 PM UTC 24 |
| Finished | Aug 21 04:14:26 PM UTC 24 |
| Peak memory | 267020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1651594317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1651594317 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.1384756613 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1794891210 ps |
| CPU time | 60.78 seconds |
| Started | Aug 21 04:14:23 PM UTC 24 |
| Finished | Aug 21 04:15:25 PM UTC 24 |
| Peak memory | 269400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1384756613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1384756613 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/40.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.911425472 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 259388097 ps |
| CPU time | 22.09 seconds |
| Started | Aug 21 04:13:55 PM UTC 24 |
| Finished | Aug 21 04:14:18 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=911425472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.911425472 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/40.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.1711267708 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 20744571154 ps |
| CPU time | 1007.86 seconds |
| Started | Aug 21 04:15:46 PM UTC 24 |
| Finished | Aug 21 04:32:45 PM UTC 24 |
| Peak memory | 301900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17112 67708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 40.alert_handler_stress_all.1711267708 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/40.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.1121326138 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 48003855179 ps |
| CPU time | 1554.38 seconds |
| Started | Aug 21 04:17:43 PM UTC 24 |
| Finished | Aug 21 04:43:55 PM UTC 24 |
| Peak memory | 285848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1121326138 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1121326138 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/41.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.1193353280 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 1323085915 ps |
| CPU time | 93.66 seconds |
| Started | Aug 21 04:17:10 PM UTC 24 |
| Finished | Aug 21 04:18:46 PM UTC 24 |
| Peak memory | 269144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1193353280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1193353280 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.3415904703 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1246875570 ps |
| CPU time | 38.84 seconds |
| Started | Aug 21 04:16:55 PM UTC 24 |
| Finished | Aug 21 04:17:35 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3415904703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3415904703 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.3524034444 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 56874397374 ps |
| CPU time | 3487.77 seconds |
| Started | Aug 21 04:18:02 PM UTC 24 |
| Finished | Aug 21 05:16:49 PM UTC 24 |
| Peak memory | 304612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3524034444 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3524034444 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/41.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.3503664295 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 19805294721 ps |
| CPU time | 1138.48 seconds |
| Started | Aug 21 04:18:09 PM UTC 24 |
| Finished | Aug 21 04:37:20 PM UTC 24 |
| Peak memory | 285840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3503664295 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_ stub_clk.3503664295 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.2026648379 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 5045457808 ps |
| CPU time | 157.77 seconds |
| Started | Aug 21 04:17:57 PM UTC 24 |
| Finished | Aug 21 04:20:37 PM UTC 24 |
| Peak memory | 269200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2026648379 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping _timeout.2026648379 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.1318810417 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 697536814 ps |
| CPU time | 31.4 seconds |
| Started | Aug 21 04:16:21 PM UTC 24 |
| Finished | Aug 21 04:16:54 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1318810417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1318810417 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.1371258905 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 262557669 ps |
| CPU time | 13.63 seconds |
| Started | Aug 21 04:16:55 PM UTC 24 |
| Finished | Aug 21 04:17:10 PM UTC 24 |
| Peak memory | 267024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1371258905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1371258905 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/41.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.2634239783 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 340488659 ps |
| CPU time | 23.3 seconds |
| Started | Aug 21 04:17:36 PM UTC 24 |
| Finished | Aug 21 04:18:01 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2634239783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2634239783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.2791380799 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 852861344 ps |
| CPU time | 50.36 seconds |
| Started | Aug 21 04:16:01 PM UTC 24 |
| Finished | Aug 21 04:16:54 PM UTC 24 |
| Peak memory | 269268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2791380799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2791380799 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/41.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.1680522320 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 2455457341 ps |
| CPU time | 115.02 seconds |
| Started | Aug 21 04:18:25 PM UTC 24 |
| Finished | Aug 21 04:20:23 PM UTC 24 |
| Peak memory | 269124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16805 22320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 41.alert_handler_stress_all.1680522320 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/41.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all_with_rand_reset.2036294687 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 2878324596 ps |
| CPU time | 302.86 seconds |
| Started | Aug 21 04:18:25 PM UTC 24 |
| Finished | Aug 21 04:23:32 PM UTC 24 |
| Peak memory | 279892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=2036294687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2036294687 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.580575111 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 228105928380 ps |
| CPU time | 3103.91 seconds |
| Started | Aug 21 04:19:15 PM UTC 24 |
| Finished | Aug 21 05:11:33 PM UTC 24 |
| Peak memory | 304944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=580575111 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.580575111 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/42.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.1058695530 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 4401870056 ps |
| CPU time | 220.36 seconds |
| Started | Aug 21 04:19:00 PM UTC 24 |
| Finished | Aug 21 04:22:44 PM UTC 24 |
| Peak memory | 269464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1058695530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1058695530 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.3086992915 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 868607616 ps |
| CPU time | 68.44 seconds |
| Started | Aug 21 04:18:50 PM UTC 24 |
| Finished | Aug 21 04:20:00 PM UTC 24 |
| Peak memory | 262920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3086992915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3086992915 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg.3248751835 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 20842837565 ps |
| CPU time | 999.97 seconds |
| Started | Aug 21 04:19:31 PM UTC 24 |
| Finished | Aug 21 04:36:24 PM UTC 24 |
| Peak memory | 285772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3248751835 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3248751835 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/42.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.623787208 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 35968683977 ps |
| CPU time | 1112.96 seconds |
| Started | Aug 21 04:19:38 PM UTC 24 |
| Finished | Aug 21 04:38:24 PM UTC 24 |
| Peak memory | 285908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=623787208 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_s tub_clk.623787208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.3435294034 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 49435728237 ps |
| CPU time | 283.55 seconds |
| Started | Aug 21 04:19:22 PM UTC 24 |
| Finished | Aug 21 04:24:10 PM UTC 24 |
| Peak memory | 269200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3435294034 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping _timeout.3435294034 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.1956821886 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 4616075072 ps |
| CPU time | 42.15 seconds |
| Started | Aug 21 04:18:47 PM UTC 24 |
| Finished | Aug 21 04:19:30 PM UTC 24 |
| Peak memory | 269132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1956821886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1956821886 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.4032113750 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 903546774 ps |
| CPU time | 34.74 seconds |
| Started | Aug 21 04:19:01 PM UTC 24 |
| Finished | Aug 21 04:19:37 PM UTC 24 |
| Peak memory | 262920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4032113750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.4032113750 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.3088304275 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 213255898 ps |
| CPU time | 20.59 seconds |
| Started | Aug 21 04:18:39 PM UTC 24 |
| Finished | Aug 21 04:19:00 PM UTC 24 |
| Peak memory | 269460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3088304275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3088304275 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/42.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.2691693908 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 675866978 ps |
| CPU time | 66.96 seconds |
| Started | Aug 21 04:20:01 PM UTC 24 |
| Finished | Aug 21 04:21:10 PM UTC 24 |
| Peak memory | 269456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26916 93908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 42.alert_handler_stress_all.2691693908 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/42.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all_with_rand_reset.3389486087 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 4178198045 ps |
| CPU time | 485.05 seconds |
| Started | Aug 21 04:20:12 PM UTC 24 |
| Finished | Aug 21 04:28:24 PM UTC 24 |
| Peak memory | 283668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=3389486087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3389486087 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.2552062085 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 32785030950 ps |
| CPU time | 669.67 seconds |
| Started | Aug 21 04:21:25 PM UTC 24 |
| Finished | Aug 21 04:32:43 PM UTC 24 |
| Peak memory | 285588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2552062085 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2552062085 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/43.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.1774304907 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 919295987 ps |
| CPU time | 31.03 seconds |
| Started | Aug 21 04:20:51 PM UTC 24 |
| Finished | Aug 21 04:21:24 PM UTC 24 |
| Peak memory | 269464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1774304907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1774304907 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.97892290 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 4529571147 ps |
| CPU time | 68.39 seconds |
| Started | Aug 21 04:20:44 PM UTC 24 |
| Finished | Aug 21 04:21:55 PM UTC 24 |
| Peak memory | 263056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=97892290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.97892290 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.3896436374 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 37958284547 ps |
| CPU time | 1869.83 seconds |
| Started | Aug 21 04:21:32 PM UTC 24 |
| Finished | Aug 21 04:53:02 PM UTC 24 |
| Peak memory | 298468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3896436374 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3896436374 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/43.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.3822953802 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 64399392677 ps |
| CPU time | 1658.09 seconds |
| Started | Aug 21 04:21:44 PM UTC 24 |
| Finished | Aug 21 04:49:41 PM UTC 24 |
| Peak memory | 302224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3822953802 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_ stub_clk.3822953802 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.2581812290 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 3678641073 ps |
| CPU time | 163.36 seconds |
| Started | Aug 21 04:21:26 PM UTC 24 |
| Finished | Aug 21 04:24:12 PM UTC 24 |
| Peak memory | 269456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2581812290 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping _timeout.2581812290 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.457943229 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2012784121 ps |
| CPU time | 64.33 seconds |
| Started | Aug 21 04:20:37 PM UTC 24 |
| Finished | Aug 21 04:21:43 PM UTC 24 |
| Peak memory | 269400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=457943229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.457943229 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.2995380678 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 27452836 ps |
| CPU time | 4.4 seconds |
| Started | Aug 21 04:20:38 PM UTC 24 |
| Finished | Aug 21 04:20:44 PM UTC 24 |
| Peak memory | 252760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2995380678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2995380678 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/43.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.242442083 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 337240454 ps |
| CPU time | 17.75 seconds |
| Started | Aug 21 04:21:12 PM UTC 24 |
| Finished | Aug 21 04:21:31 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=242442083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.242442083 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.787734178 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 532577529 ps |
| CPU time | 11 seconds |
| Started | Aug 21 04:20:24 PM UTC 24 |
| Finished | Aug 21 04:20:36 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=787734178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.787734178 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/43.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.1932524525 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 4732469313 ps |
| CPU time | 420.14 seconds |
| Started | Aug 21 04:21:55 PM UTC 24 |
| Finished | Aug 21 04:29:01 PM UTC 24 |
| Peak memory | 279364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19325 24525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 43.alert_handler_stress_all.1932524525 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/43.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all_with_rand_reset.3104351680 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 21953086975 ps |
| CPU time | 380.7 seconds |
| Started | Aug 21 04:21:58 PM UTC 24 |
| Finished | Aug 21 04:28:24 PM UTC 24 |
| Peak memory | 281548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=3104351680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3104351680 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.2636397896 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 22817547610 ps |
| CPU time | 1606.46 seconds |
| Started | Aug 21 04:23:10 PM UTC 24 |
| Finished | Aug 21 04:50:16 PM UTC 24 |
| Peak memory | 283472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2636397896 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2636397896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/44.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.1614674281 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 396466390 ps |
| CPU time | 32.68 seconds |
| Started | Aug 21 04:22:49 PM UTC 24 |
| Finished | Aug 21 04:23:23 PM UTC 24 |
| Peak memory | 269400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1614674281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1614674281 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.2426027464 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 209360606 ps |
| CPU time | 19.75 seconds |
| Started | Aug 21 04:22:48 PM UTC 24 |
| Finished | Aug 21 04:23:09 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2426027464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2426027464 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.3204423657 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 28166022073 ps |
| CPU time | 1794.2 seconds |
| Started | Aug 21 04:23:24 PM UTC 24 |
| Finished | Aug 21 04:53:40 PM UTC 24 |
| Peak memory | 295756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3204423657 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_ stub_clk.3204423657 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.1486581561 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 67919336457 ps |
| CPU time | 378.61 seconds |
| Started | Aug 21 04:23:11 PM UTC 24 |
| Finished | Aug 21 04:29:34 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1486581561 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping _timeout.1486581561 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.144902509 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1024814640 ps |
| CPU time | 23.68 seconds |
| Started | Aug 21 04:22:21 PM UTC 24 |
| Finished | Aug 21 04:22:47 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=144902509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.144902509 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.3969637981 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1201103231 ps |
| CPU time | 38.58 seconds |
| Started | Aug 21 04:22:45 PM UTC 24 |
| Finished | Aug 21 04:23:26 PM UTC 24 |
| Peak memory | 269400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3969637981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3969637981 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/44.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.1032961527 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 973318200 ps |
| CPU time | 26.71 seconds |
| Started | Aug 21 04:23:02 PM UTC 24 |
| Finished | Aug 21 04:23:30 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1032961527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1032961527 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.3665762197 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 638330599 ps |
| CPU time | 54.45 seconds |
| Started | Aug 21 04:22:14 PM UTC 24 |
| Finished | Aug 21 04:23:10 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3665762197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3665762197 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/44.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all_with_rand_reset.1754551616 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 1223257331 ps |
| CPU time | 56.31 seconds |
| Started | Aug 21 04:23:31 PM UTC 24 |
| Finished | Aug 21 04:24:29 PM UTC 24 |
| Peak memory | 279764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=1754551616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1754551616 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.945634799 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 35133568697 ps |
| CPU time | 2272.36 seconds |
| Started | Aug 21 04:24:35 PM UTC 24 |
| Finished | Aug 21 05:02:54 PM UTC 24 |
| Peak memory | 288232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=945634799 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.945634799 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/45.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.3982530471 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 3423124922 ps |
| CPU time | 163.93 seconds |
| Started | Aug 21 04:24:27 PM UTC 24 |
| Finished | Aug 21 04:27:14 PM UTC 24 |
| Peak memory | 269208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3982530471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3982530471 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.3614612002 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 24032830402 ps |
| CPU time | 63.9 seconds |
| Started | Aug 21 04:24:18 PM UTC 24 |
| Finished | Aug 21 04:25:24 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3614612002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3614612002 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg.1804129939 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 10321782108 ps |
| CPU time | 917.07 seconds |
| Started | Aug 21 04:24:48 PM UTC 24 |
| Finished | Aug 21 04:40:16 PM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1804129939 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1804129939 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/45.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.4042152311 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 119614211511 ps |
| CPU time | 1931.18 seconds |
| Started | Aug 21 04:24:51 PM UTC 24 |
| Finished | Aug 21 04:57:24 PM UTC 24 |
| Peak memory | 301896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4042152311 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_ stub_clk.4042152311 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.3692534556 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 5162613465 ps |
| CPU time | 116.84 seconds |
| Started | Aug 21 04:24:45 PM UTC 24 |
| Finished | Aug 21 04:26:44 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3692534556 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping _timeout.3692534556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.3676321801 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 29261292 ps |
| CPU time | 5.17 seconds |
| Started | Aug 21 04:24:11 PM UTC 24 |
| Finished | Aug 21 04:24:18 PM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3676321801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3676321801 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.2391109186 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 558498271 ps |
| CPU time | 12.4 seconds |
| Started | Aug 21 04:24:13 PM UTC 24 |
| Finished | Aug 21 04:24:27 PM UTC 24 |
| Peak memory | 265048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2391109186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2391109186 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/45.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.3623278438 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 375817699 ps |
| CPU time | 12.24 seconds |
| Started | Aug 21 04:24:30 PM UTC 24 |
| Finished | Aug 21 04:24:44 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3623278438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3623278438 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.4099234246 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 912555412 ps |
| CPU time | 75.06 seconds |
| Started | Aug 21 04:23:34 PM UTC 24 |
| Finished | Aug 21 04:24:50 PM UTC 24 |
| Peak memory | 269396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4099234246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.4099234246 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/45.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.766746626 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 62329197528 ps |
| CPU time | 3207.66 seconds |
| Started | Aug 21 04:25:16 PM UTC 24 |
| Finished | Aug 21 05:19:20 PM UTC 24 |
| Peak memory | 305012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=76674 6626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 45.alert_handler_stress_all.766746626 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/45.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all_with_rand_reset.3021894719 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 3295289413 ps |
| CPU time | 191.82 seconds |
| Started | Aug 21 04:25:25 PM UTC 24 |
| Finished | Aug 21 04:28:39 PM UTC 24 |
| Peak memory | 279572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=3021894719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3021894719 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/45.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.3250897765 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 116009292253 ps |
| CPU time | 2134.67 seconds |
| Started | Aug 21 04:26:11 PM UTC 24 |
| Finished | Aug 21 05:02:12 PM UTC 24 |
| Peak memory | 300520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3250897765 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3250897765 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/46.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.2425731814 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 2176832375 ps |
| CPU time | 97.02 seconds |
| Started | Aug 21 04:26:05 PM UTC 24 |
| Finished | Aug 21 04:27:44 PM UTC 24 |
| Peak memory | 269208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2425731814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2425731814 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.3172418434 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 101191496 ps |
| CPU time | 8.98 seconds |
| Started | Aug 21 04:26:01 PM UTC 24 |
| Finished | Aug 21 04:26:11 PM UTC 24 |
| Peak memory | 267016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3172418434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3172418434 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.2304163370 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 42241783351 ps |
| CPU time | 2573.96 seconds |
| Started | Aug 21 04:26:41 PM UTC 24 |
| Finished | Aug 21 05:10:05 PM UTC 24 |
| Peak memory | 300516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2304163370 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2304163370 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/46.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.3771180823 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 32274390272 ps |
| CPU time | 2114.95 seconds |
| Started | Aug 21 04:26:45 PM UTC 24 |
| Finished | Aug 21 05:02:25 PM UTC 24 |
| Peak memory | 301972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3771180823 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_ stub_clk.3771180823 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.3082137522 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 16397457446 ps |
| CPU time | 331.67 seconds |
| Started | Aug 21 04:26:35 PM UTC 24 |
| Finished | Aug 21 04:32:11 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3082137522 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping _timeout.3082137522 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.3067540471 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 420463992 ps |
| CPU time | 24.57 seconds |
| Started | Aug 21 04:25:39 PM UTC 24 |
| Finished | Aug 21 04:26:05 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3067540471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3067540471 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.2816546765 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 1915019844 ps |
| CPU time | 43.11 seconds |
| Started | Aug 21 04:25:56 PM UTC 24 |
| Finished | Aug 21 04:26:40 PM UTC 24 |
| Peak memory | 269144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2816546765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2816546765 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/46.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.3367915092 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 328133593 ps |
| CPU time | 26.1 seconds |
| Started | Aug 21 04:26:06 PM UTC 24 |
| Finished | Aug 21 04:26:34 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3367915092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3367915092 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.344796120 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 940618732 ps |
| CPU time | 25.49 seconds |
| Started | Aug 21 04:25:27 PM UTC 24 |
| Finished | Aug 21 04:25:55 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=344796120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.344796120 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/46.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.2699969689 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 3475756076 ps |
| CPU time | 129.36 seconds |
| Started | Aug 21 04:27:15 PM UTC 24 |
| Finished | Aug 21 04:29:27 PM UTC 24 |
| Peak memory | 269328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26999 69689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 46.alert_handler_stress_all.2699969689 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/46.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.741527969 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 50021824831 ps |
| CPU time | 2952.4 seconds |
| Started | Aug 21 04:28:31 PM UTC 24 |
| Finished | Aug 21 05:18:17 PM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=741527969 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.741527969 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/47.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.2442787152 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1793136459 ps |
| CPU time | 54.97 seconds |
| Started | Aug 21 04:28:25 PM UTC 24 |
| Finished | Aug 21 04:29:22 PM UTC 24 |
| Peak memory | 269144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2442787152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2442787152 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.2230371530 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1570155551 ps |
| CPU time | 29.44 seconds |
| Started | Aug 21 04:28:25 PM UTC 24 |
| Finished | Aug 21 04:28:56 PM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2230371530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2230371530 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.2422358094 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 28269094265 ps |
| CPU time | 1670.78 seconds |
| Started | Aug 21 04:28:42 PM UTC 24 |
| Finished | Aug 21 04:56:52 PM UTC 24 |
| Peak memory | 285900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2422358094 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2422358094 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/47.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.644656304 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 98539469827 ps |
| CPU time | 2220.09 seconds |
| Started | Aug 21 04:28:47 PM UTC 24 |
| Finished | Aug 21 05:06:13 PM UTC 24 |
| Peak memory | 300596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=644656304 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_s tub_clk.644656304 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.2317764521 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 10134447665 ps |
| CPU time | 463.89 seconds |
| Started | Aug 21 04:28:40 PM UTC 24 |
| Finished | Aug 21 04:36:30 PM UTC 24 |
| Peak memory | 263056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2317764521 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping _timeout.2317764521 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.3306699071 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 1050198356 ps |
| CPU time | 19.79 seconds |
| Started | Aug 21 04:28:05 PM UTC 24 |
| Finished | Aug 21 04:28:26 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3306699071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3306699071 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.2504137153 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 7416297946 ps |
| CPU time | 100.16 seconds |
| Started | Aug 21 04:28:19 PM UTC 24 |
| Finished | Aug 21 04:30:01 PM UTC 24 |
| Peak memory | 269464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2504137153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2504137153 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/47.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.884095735 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 726662657 ps |
| CPU time | 59.51 seconds |
| Started | Aug 21 04:28:27 PM UTC 24 |
| Finished | Aug 21 04:29:30 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=884095735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.884095735 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.889972362 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 261471518 ps |
| CPU time | 30.81 seconds |
| Started | Aug 21 04:27:45 PM UTC 24 |
| Finished | Aug 21 04:28:17 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=889972362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.889972362 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/47.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.1263634835 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 61539722432 ps |
| CPU time | 1666.77 seconds |
| Started | Aug 21 04:28:47 PM UTC 24 |
| Finished | Aug 21 04:56:54 PM UTC 24 |
| Peak memory | 318280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=12636 34835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 47.alert_handler_stress_all.1263634835 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/47.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.1293276082 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 178331206603 ps |
| CPU time | 2498.41 seconds |
| Started | Aug 21 04:29:35 PM UTC 24 |
| Finished | Aug 21 05:11:41 PM UTC 24 |
| Peak memory | 304692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1293276082 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1293276082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/48.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.2709907866 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2701246403 ps |
| CPU time | 174.72 seconds |
| Started | Aug 21 04:29:27 PM UTC 24 |
| Finished | Aug 21 04:32:25 PM UTC 24 |
| Peak memory | 265036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2709907866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2709907866 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.3090110053 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 991946010 ps |
| CPU time | 69.02 seconds |
| Started | Aug 21 04:29:23 PM UTC 24 |
| Finished | Aug 21 04:30:34 PM UTC 24 |
| Peak memory | 262916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3090110053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3090110053 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.3562483519 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 74817111212 ps |
| CPU time | 2208.64 seconds |
| Started | Aug 21 04:29:50 PM UTC 24 |
| Finished | Aug 21 05:07:04 PM UTC 24 |
| Peak memory | 302288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3562483519 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3562483519 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/48.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.177506175 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 257056668161 ps |
| CPU time | 1303.94 seconds |
| Started | Aug 21 04:30:02 PM UTC 24 |
| Finished | Aug 21 04:52:01 PM UTC 24 |
| Peak memory | 285588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=177506175 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_s tub_clk.177506175 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.1318301711 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 8050280741 ps |
| CPU time | 244.26 seconds |
| Started | Aug 21 04:29:47 PM UTC 24 |
| Finished | Aug 21 04:33:55 PM UTC 24 |
| Peak memory | 269124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1318301711 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping _timeout.1318301711 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.1058094937 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 681716576 ps |
| CPU time | 51.5 seconds |
| Started | Aug 21 04:29:10 PM UTC 24 |
| Finished | Aug 21 04:30:03 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1058094937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1058094937 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.3283348141 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 887926469 ps |
| CPU time | 43.6 seconds |
| Started | Aug 21 04:29:20 PM UTC 24 |
| Finished | Aug 21 04:30:05 PM UTC 24 |
| Peak memory | 263000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3283348141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3283348141 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/48.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.40468001 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 477388812 ps |
| CPU time | 40.92 seconds |
| Started | Aug 21 04:29:31 PM UTC 24 |
| Finished | Aug 21 04:30:13 PM UTC 24 |
| Peak memory | 269396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40468001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.40468001 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.3665060115 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 493207773 ps |
| CPU time | 15.68 seconds |
| Started | Aug 21 04:29:03 PM UTC 24 |
| Finished | Aug 21 04:29:20 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3665060115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3665060115 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/48.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.796568270 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 238039771206 ps |
| CPU time | 2984.16 seconds |
| Started | Aug 21 04:30:04 PM UTC 24 |
| Finished | Aug 21 05:20:20 PM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=79656 8270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 48.alert_handler_stress_all.796568270 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/48.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.1060575449 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 114330224878 ps |
| CPU time | 1145.33 seconds |
| Started | Aug 21 04:31:01 PM UTC 24 |
| Finished | Aug 21 04:50:21 PM UTC 24 |
| Peak memory | 285516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1060575449 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1060575449 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/49.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.4127197994 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 960507674 ps |
| CPU time | 22.05 seconds |
| Started | Aug 21 04:30:39 PM UTC 24 |
| Finished | Aug 21 04:31:02 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4127197994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.4127197994 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.827547478 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 156701028 ps |
| CPU time | 10.07 seconds |
| Started | Aug 21 04:30:37 PM UTC 24 |
| Finished | Aug 21 04:30:48 PM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=827547478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.827547478 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.1221660738 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 185687737313 ps |
| CPU time | 1162.22 seconds |
| Started | Aug 21 04:31:03 PM UTC 24 |
| Finished | Aug 21 04:50:39 PM UTC 24 |
| Peak memory | 279364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1221660738 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1221660738 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/49.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.614061497 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 7339169804 ps |
| CPU time | 793.29 seconds |
| Started | Aug 21 04:31:33 PM UTC 24 |
| Finished | Aug 21 04:44:57 PM UTC 24 |
| Peak memory | 279444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=614061497 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_s tub_clk.614061497 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.3459900590 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 130353646146 ps |
| CPU time | 487.53 seconds |
| Started | Aug 21 04:31:02 PM UTC 24 |
| Finished | Aug 21 04:39:16 PM UTC 24 |
| Peak memory | 269200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3459900590 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping _timeout.3459900590 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.4193937358 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 318895969 ps |
| CPU time | 37.85 seconds |
| Started | Aug 21 04:30:22 PM UTC 24 |
| Finished | Aug 21 04:31:01 PM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4193937358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.4193937358 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.3183129044 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 2413440369 ps |
| CPU time | 55.27 seconds |
| Started | Aug 21 04:30:36 PM UTC 24 |
| Finished | Aug 21 04:31:33 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3183129044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3183129044 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/49.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.1483133152 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 4386628104 ps |
| CPU time | 87.76 seconds |
| Started | Aug 21 04:30:49 PM UTC 24 |
| Finished | Aug 21 04:32:19 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1483133152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1483133152 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.1534692381 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 926059810 ps |
| CPU time | 23.16 seconds |
| Started | Aug 21 04:30:14 PM UTC 24 |
| Finished | Aug 21 04:30:38 PM UTC 24 |
| Peak memory | 269268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1534692381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1534692381 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/49.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all_with_rand_reset.3143036114 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 7933143045 ps |
| CPU time | 346.32 seconds |
| Started | Aug 21 04:32:20 PM UTC 24 |
| Finished | Aug 21 04:38:11 PM UTC 24 |
| Peak memory | 279828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=3143036114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3143036114 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.1932063138 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 12839207 ps |
| CPU time | 3.53 seconds |
| Started | Aug 21 03:08:26 PM UTC 24 |
| Finished | Aug 21 03:08:30 PM UTC 24 |
| Peak memory | 263192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1932063138 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_satu ration.1932063138 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.277618555 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 7797520627 ps |
| CPU time | 884.97 seconds |
| Started | Aug 21 03:08:18 PM UTC 24 |
| Finished | Aug 21 03:23:14 PM UTC 24 |
| Peak memory | 285588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=277618555 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.277618555 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.1954015273 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2274974942 ps |
| CPU time | 25.21 seconds |
| Started | Aug 21 03:08:23 PM UTC 24 |
| Finished | Aug 21 03:08:49 PM UTC 24 |
| Peak memory | 263068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1954015273 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1954015273 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.976322468 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 8818090127 ps |
| CPU time | 258.93 seconds |
| Started | Aug 21 03:08:18 PM UTC 24 |
| Finished | Aug 21 03:12:41 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=976322468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.976322468 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.3413754897 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 450656831 ps |
| CPU time | 11.21 seconds |
| Started | Aug 21 03:08:17 PM UTC 24 |
| Finished | Aug 21 03:08:29 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3413754897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3413754897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.623271595 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 14473833650 ps |
| CPU time | 1119.85 seconds |
| Started | Aug 21 03:08:21 PM UTC 24 |
| Finished | Aug 21 03:27:14 PM UTC 24 |
| Peak memory | 285588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=623271595 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.623271595 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.2448826814 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 32366094039 ps |
| CPU time | 2128.02 seconds |
| Started | Aug 21 03:08:23 PM UTC 24 |
| Finished | Aug 21 03:44:15 PM UTC 24 |
| Peak memory | 302648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2448826814 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_s tub_clk.2448826814 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.963558713 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 401413687 ps |
| CPU time | 16.22 seconds |
| Started | Aug 21 03:08:16 PM UTC 24 |
| Finished | Aug 21 03:08:33 PM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=963558713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.963558713 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.1417097484 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 229459138 ps |
| CPU time | 6.6 seconds |
| Started | Aug 21 03:08:18 PM UTC 24 |
| Finished | Aug 21 03:08:26 PM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1417097484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1417097484 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.2166151796 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1633871434 ps |
| CPU time | 21.39 seconds |
| Started | Aug 21 03:08:14 PM UTC 24 |
| Finished | Aug 21 03:08:36 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2166151796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2166151796 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.3245691762 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 75776070 ps |
| CPU time | 3.36 seconds |
| Started | Aug 21 03:08:37 PM UTC 24 |
| Finished | Aug 21 03:08:42 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3245691762 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_satu ration.3245691762 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.2721632048 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 58897189864 ps |
| CPU time | 1166.64 seconds |
| Started | Aug 21 03:08:32 PM UTC 24 |
| Finished | Aug 21 03:28:13 PM UTC 24 |
| Peak memory | 285512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2721632048 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2721632048 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.1062236631 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1020301873 ps |
| CPU time | 33.62 seconds |
| Started | Aug 21 03:08:35 PM UTC 24 |
| Finished | Aug 21 03:09:10 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1062236631 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1062236631 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.546185246 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 12061987706 ps |
| CPU time | 165.74 seconds |
| Started | Aug 21 03:08:31 PM UTC 24 |
| Finished | Aug 21 03:11:20 PM UTC 24 |
| Peak memory | 265368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=546185246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.546185246 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.3580061225 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2138419561 ps |
| CPU time | 52.4 seconds |
| Started | Aug 21 03:08:30 PM UTC 24 |
| Finished | Aug 21 03:09:25 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3580061225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3580061225 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.391889197 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 42915093585 ps |
| CPU time | 2995.46 seconds |
| Started | Aug 21 03:08:35 PM UTC 24 |
| Finished | Aug 21 03:59:05 PM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=391889197 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_st ub_clk.391889197 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.4149550208 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5890700212 ps |
| CPU time | 73.66 seconds |
| Started | Aug 21 03:08:34 PM UTC 24 |
| Finished | Aug 21 03:09:49 PM UTC 24 |
| Peak memory | 263064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4149550208 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_ timeout.4149550208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.3255831495 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1111433002 ps |
| CPU time | 28.9 seconds |
| Started | Aug 21 03:08:29 PM UTC 24 |
| Finished | Aug 21 03:08:59 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3255831495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3255831495 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.4117545264 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 476439172 ps |
| CPU time | 20.54 seconds |
| Started | Aug 21 03:08:30 PM UTC 24 |
| Finished | Aug 21 03:08:52 PM UTC 24 |
| Peak memory | 269396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4117545264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.4117545264 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.1043365669 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 957562633 ps |
| CPU time | 44.84 seconds |
| Started | Aug 21 03:08:29 PM UTC 24 |
| Finished | Aug 21 03:09:15 PM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1043365669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1043365669 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all_with_rand_reset.3383578758 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 17275076470 ps |
| CPU time | 311.08 seconds |
| Started | Aug 21 03:08:38 PM UTC 24 |
| Finished | Aug 21 03:13:54 PM UTC 24 |
| Peak memory | 279828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=3383578758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3383578758 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.3130415396 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 12992924 ps |
| CPU time | 3.26 seconds |
| Started | Aug 21 03:09:08 PM UTC 24 |
| Finished | Aug 21 03:09:12 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3130415396 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_satu ration.3130415396 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.3824148763 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 463561934 ps |
| CPU time | 17.49 seconds |
| Started | Aug 21 03:09:00 PM UTC 24 |
| Finished | Aug 21 03:09:19 PM UTC 24 |
| Peak memory | 263324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3824148763 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3824148763 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.3323632203 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2663227217 ps |
| CPU time | 145.3 seconds |
| Started | Aug 21 03:08:43 PM UTC 24 |
| Finished | Aug 21 03:11:11 PM UTC 24 |
| Peak memory | 265040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3323632203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3323632203 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.1733796444 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1044494288 ps |
| CPU time | 26.35 seconds |
| Started | Aug 21 03:08:42 PM UTC 24 |
| Finished | Aug 21 03:09:10 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1733796444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1733796444 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.1401468098 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 65391146295 ps |
| CPU time | 1479.28 seconds |
| Started | Aug 21 03:08:52 PM UTC 24 |
| Finished | Aug 21 03:33:49 PM UTC 24 |
| Peak memory | 301900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1401468098 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1401468098 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.3489173849 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 16272590554 ps |
| CPU time | 1368.38 seconds |
| Started | Aug 21 03:08:53 PM UTC 24 |
| Finished | Aug 21 03:31:57 PM UTC 24 |
| Peak memory | 301912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3489173849 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_s tub_clk.3489173849 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.1843257569 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2122405174 ps |
| CPU time | 59.6 seconds |
| Started | Aug 21 03:08:40 PM UTC 24 |
| Finished | Aug 21 03:09:42 PM UTC 24 |
| Peak memory | 269392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1843257569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1843257569 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.61774191 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1174854123 ps |
| CPU time | 43.43 seconds |
| Started | Aug 21 03:08:40 PM UTC 24 |
| Finished | Aug 21 03:09:25 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=61774191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.61774191 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.1580371881 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 697110635 ps |
| CPU time | 36.33 seconds |
| Started | Aug 21 03:08:44 PM UTC 24 |
| Finished | Aug 21 03:09:22 PM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1580371881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1580371881 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.1549547464 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 3531064659 ps |
| CPU time | 49.96 seconds |
| Started | Aug 21 03:08:39 PM UTC 24 |
| Finished | Aug 21 03:09:31 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1549547464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1549547464 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all_with_rand_reset.661774106 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 6520330627 ps |
| CPU time | 634.24 seconds |
| Started | Aug 21 03:09:11 PM UTC 24 |
| Finished | Aug 21 03:19:53 PM UTC 24 |
| Peak memory | 295880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/ hw/dv/tools/sim.tcl +ntb_random_seed=661774106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.661774106 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.2726116030 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 124224009 ps |
| CPU time | 4.29 seconds |
| Started | Aug 21 03:09:42 PM UTC 24 |
| Finished | Aug 21 03:09:48 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2726116030 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_satu ration.2726116030 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.2999812462 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 265546165091 ps |
| CPU time | 3037.51 seconds |
| Started | Aug 21 03:09:25 PM UTC 24 |
| Finished | Aug 21 04:00:34 PM UTC 24 |
| Peak memory | 304944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2999812462 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2999812462 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.3620868916 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 505916968 ps |
| CPU time | 31.39 seconds |
| Started | Aug 21 03:09:32 PM UTC 24 |
| Finished | Aug 21 03:10:05 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3620868916 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3620868916 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.3074773241 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1438406319 ps |
| CPU time | 78.76 seconds |
| Started | Aug 21 03:09:22 PM UTC 24 |
| Finished | Aug 21 03:10:43 PM UTC 24 |
| Peak memory | 269144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3074773241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3074773241 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.299940167 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 450826269 ps |
| CPU time | 39.28 seconds |
| Started | Aug 21 03:09:20 PM UTC 24 |
| Finished | Aug 21 03:10:01 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=299940167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.299940167 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.1983984675 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 36066095941 ps |
| CPU time | 1677.84 seconds |
| Started | Aug 21 03:09:27 PM UTC 24 |
| Finished | Aug 21 03:37:45 PM UTC 24 |
| Peak memory | 297804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1983984675 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1983984675 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.308442749 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 56764900365 ps |
| CPU time | 1777.76 seconds |
| Started | Aug 21 03:09:28 PM UTC 24 |
| Finished | Aug 21 03:39:26 PM UTC 24 |
| Peak memory | 285588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=308442749 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_st ub_clk.308442749 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.2659255803 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3283951551 ps |
| CPU time | 168.12 seconds |
| Started | Aug 21 03:09:26 PM UTC 24 |
| Finished | Aug 21 03:12:17 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2659255803 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_ timeout.2659255803 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.3463941211 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 506217635 ps |
| CPU time | 8.33 seconds |
| Started | Aug 21 03:09:13 PM UTC 24 |
| Finished | Aug 21 03:09:22 PM UTC 24 |
| Peak memory | 262992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3463941211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3463941211 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.3943585214 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 138363323 ps |
| CPU time | 6.51 seconds |
| Started | Aug 21 03:09:16 PM UTC 24 |
| Finished | Aug 21 03:09:24 PM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3943585214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3943585214 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.2204603554 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 241421554 ps |
| CPU time | 8.05 seconds |
| Started | Aug 21 03:09:23 PM UTC 24 |
| Finished | Aug 21 03:09:33 PM UTC 24 |
| Peak memory | 253016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2204603554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2204603554 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.1377932428 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1975444055 ps |
| CPU time | 67.68 seconds |
| Started | Aug 21 03:09:11 PM UTC 24 |
| Finished | Aug 21 03:10:20 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1377932428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1377932428 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.505256001 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 60390204155 ps |
| CPU time | 1536.33 seconds |
| Started | Aug 21 03:09:33 PM UTC 24 |
| Finished | Aug 21 03:35:27 PM UTC 24 |
| Peak memory | 302292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=50525 6001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 8.alert_handler_stress_all.505256001 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/8.alert_handler_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.1696121914 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 90933331 ps |
| CPU time | 5.78 seconds |
| Started | Aug 21 03:10:44 PM UTC 24 |
| Finished | Aug 21 03:10:51 PM UTC 24 |
| Peak memory | 263516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1696121914 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_satu ration.1696121914 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.596751637 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 309568351572 ps |
| CPU time | 2319.25 seconds |
| Started | Aug 21 03:10:18 PM UTC 24 |
| Finished | Aug 21 03:49:23 PM UTC 24 |
| Peak memory | 305012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=596751637 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.596751637 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_entropy/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.493157104 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 5728342474 ps |
| CPU time | 84.96 seconds |
| Started | Aug 21 03:10:29 PM UTC 24 |
| Finished | Aug 21 03:11:56 PM UTC 24 |
| Peak memory | 262988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=493157104 -assert nopostproc +UVM_TESTNAME=alert_handler _base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.493157104 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.1579965929 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 5185161687 ps |
| CPU time | 136.63 seconds |
| Started | Aug 21 03:10:13 PM UTC 24 |
| Finished | Aug 21 03:12:32 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1579965929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1579965929 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.3276417730 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 231901730 ps |
| CPU time | 18.25 seconds |
| Started | Aug 21 03:10:10 PM UTC 24 |
| Finished | Aug 21 03:10:30 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3276417730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3276417730 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.2952515751 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 29752330983 ps |
| CPU time | 1597.58 seconds |
| Started | Aug 21 03:10:22 PM UTC 24 |
| Finished | Aug 21 03:37:18 PM UTC 24 |
| Peak memory | 285592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2952515751 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2952515751 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_lpg/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.3337452801 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 28853301482 ps |
| CPU time | 702.81 seconds |
| Started | Aug 21 03:10:27 PM UTC 24 |
| Finished | Aug 21 03:22:18 PM UTC 24 |
| Peak memory | 285592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3337452801 -assert nopostproc +UVM_ TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_s tub_clk.3337452801 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.2060850855 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 114947351 ps |
| CPU time | 6.84 seconds |
| Started | Aug 21 03:10:02 PM UTC 24 |
| Finished | Aug 21 03:10:09 PM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2060850855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2060850855 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.2817997104 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3571868523 ps |
| CPU time | 40.57 seconds |
| Started | Aug 21 03:10:06 PM UTC 24 |
| Finished | Aug 21 03:10:48 PM UTC 24 |
| Peak memory | 263060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2817997104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2817997104 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_random_classes/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.3222570379 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 455764524 ps |
| CPU time | 11.07 seconds |
| Started | Aug 21 03:10:13 PM UTC 24 |
| Finished | Aug 21 03:10:25 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3222570379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3222570379 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.2637678213 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1639854148 ps |
| CPU time | 35.98 seconds |
| Started | Aug 21 03:09:50 PM UTC 24 |
| Finished | Aug 21 03:10:28 PM UTC 24 |
| Peak memory | 269396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2637678213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2637678213 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.3920564582 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 56974478066 ps |
| CPU time | 1504.29 seconds |
| Started | Aug 21 03:10:31 PM UTC 24 |
| Finished | Aug 21 03:35:51 PM UTC 24 |
| Peak memory | 297796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_n s=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39205 64582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 9.alert_handler_stress_all.3920564582 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |