Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	62454	1			T10	2		T16	6		T41	3
class_i[0x1]	30688	1			T10	49		T18	5		T112	2
class_i[0x2]	74011	1			T27	28		T41	645		T46	79
class_i[0x3]	41607	1			T10	3		T16	16		T46	4

---

Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	53252	1			T10	21		T16	12		T27	21
alert[0x1]	53355	1			T10	7		T16	1		T27	7
alert[0x2]	52382	1			T10	15		T16	1		T41	1
alert[0x3]	49771	1			T10	11		T16	8		T41	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

208454

1

T10

54

T16

22

T27

28

esc_ping_fail

306

1

T18

5

T19

3

T20

3

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	53160	1			T10	21		T16	12		T27	21
esc_integrity_fail	alert[0x1]	53277	1			T10	7		T16	1		T27	7
esc_integrity_fail	alert[0x2]	52311	1			T10	15		T16	1		T41	1
esc_integrity_fail	alert[0x3]	49706	1			T10	11		T16	8		T41	1
esc_ping_fail	alert[0x0]	92	1			T18	1		T19	1		T20	2
esc_ping_fail	alert[0x1]	78	1			T18	2		T201	1		T131	3
esc_ping_fail	alert[0x2]	71	1			T18	1		T201	2		T131	2
esc_ping_fail	alert[0x3]	65	1			T18	1		T19	2		T20	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	62371	1			T10	2		T16	6		T41	3
esc_integrity_fail	class_i[0x1]	30600	1			T10	49		T80	19		T48	174
esc_integrity_fail	class_i[0x2]	73953	1			T27	28		T41	645		T46	79
esc_integrity_fail	class_i[0x3]	41530	1			T10	3		T16	16		T46	4
esc_ping_fail	class_i[0x0]	83	1			T131	1		T246	1		T106	1
esc_ping_fail	class_i[0x1]	88	1			T18	5		T112	2		T201	7
esc_ping_fail	class_i[0x2]	58	1			T112	1		T201	1		T131	6
esc_ping_fail	class_i[0x3]	77	1			T19	3		T20	3		T131	1