Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	557183493	0	0	622
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	557183493	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	557183493	557025290	0	0
tb.dut.CheckAccuCntDw	0	0	622	622	0	0
tb.dut.CheckEscCntDw	0	0	622	622	0	0
tb.dut.CheckNAlerts	0	0	622	622	0	0
tb.dut.CheckNClasses	0	0	622	622	0	0
tb.dut.CheckNEscSev	0	0	622	622	0	0
tb.dut.CrashdumpKnownO_A	0	0	557183493	557025290	0	0
tb.dut.EdnKnownO_A	0	0	557183493	557025290	0	0
tb.dut.EscPKnownO_A	0	0	557183493	557025290	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	557183493	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	557183493	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	557183493	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	557183493	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	557183493	70	0	0
tb.dut.IrqAKnownO_A	0	0	557183493	557025290	0	0
tb.dut.IrqBKnownO_A	0	0	557183493	557025290	0	0
tb.dut.IrqCKnownO_A	0	0	557183493	557025290	0	0
tb.dut.IrqDKnownO_A	0	0	557183493	557025290	0	0
tb.dut.TlAReadyKnownO_A	0	0	557183493	557025290	0	0
tb.dut.TlDValidKnownO_A	0	0	557183493	557025290	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	582597001	204274	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	582597001	13384	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	582597001	13857	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	582597001	13543	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	582597001	12615	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	582597001	13658	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	582597001	12861	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	582597001	12359	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	582597001	13876	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	582597001	12330	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	582597001	13805	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	582597001	12693	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	582597001	13838	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	582597001	14627	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	582597001	13566	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	582597001	14092	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	582597001	12518	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	582597001	13573	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	582597001	13706	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	582597001	13555	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	582597001	15022	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	582597001	12319	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	582597001	13829	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	582597001	12989	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	582597001	12336	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	582597001	13592	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	582597001	13889	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	582597001	13632	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	582597001	13571	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	582597001	13688	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	582597001	12493	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	582597001	12384	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	582597001	12289	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	582597001	12639	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	582597001	12659	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	582597001	13699	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	582597001	13457	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	582597001	13903	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	582597001	12719	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	582597001	12459	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	582597001	12482	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	582597001	12405	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	582597001	12316	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	582597001	14999	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	582597001	12492	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	582597001	12318	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	582597001	13479	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	582597001	13507	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	582597001	12539	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	582597001	13846	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	582597001	13708	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	582597001	12474	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	582597001	12524	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	582597001	13471	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	582597001	14599	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	582597001	12936	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	582597001	13772	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	582597001	12368	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	582597001	13709	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	582597001	13736	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	582597001	12463	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	582597001	12600	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	582597001	13670	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	582597001	12823	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	582597001	13684	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	582597001	12634	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	582597001	12839	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	582597001	15121	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	582597001	13724	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	582597001	13768	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	582597001	21796	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	582597001	13619	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	582597001	13664	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	582597001	12470	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	582597001	13635	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	582597001	13781	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	582597001	12373	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	582597001	12509	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	582597001	13398	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	557183493	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	557183493	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	557183493	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	557183493	1747	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	557183493	150963	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	557183493	302752195	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	557183493	174	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	557183493	786	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	557183493	38	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	557183493	391	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	557042185	224541545	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	557183493	856	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	557183493	835	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	557183493	824	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	557183493	800	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	557183493	1109	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	557183493	104864	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	557183493	1006	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	557183493	59	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	557183493	1118	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	557183493	908	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	557041145	556972099	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	557183493	557025290	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	557183493	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	557183493	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	557183493	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	557183493	3151	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	557183493	123764	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	557183493	342788293	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	557183493	227	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	557183493	454	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	557183493	21	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	557183493	215	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	557042185	263655584	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	557183493	513	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	557183493	500	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	557183493	491	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	557183493	487	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	557183493	930	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	557183493	95714	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	557183493	855	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	557183493	52	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	557183493	1103	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	557183493	893	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	557041145	556972099	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	557183493	557025290	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	557183493	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	557183493	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	557183493	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	557183493	2681	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	557183493	181775	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	557183493	315148740	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	557183493	190	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	557183493	494	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	557183493	26	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	557183493	238	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	557042185	249527955	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	557183493	538	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	557183493	527	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	557183493	516	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	557183493	507	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	557183493	786	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	557183493	74908	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	557183493	717	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	557183493	40	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	557183493	1110	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	557183493	900	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	557041145	556972099	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	557183493	557025290	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	557183493	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	557183493	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	557183493	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	557183493	4133	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	557183493	140189	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	557183493	319071027	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	557183493	211	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	557183493	436	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	557183493	18	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	557183493	187	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	557042185	244160728	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	557183493	491	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	557183493	479	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	557183493	477	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	557183493	464	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	557183493	489	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	557183493	54329	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	557183493	418	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	557183493	48	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	557183493	1087	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	557183493	877	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	557041145	556972099	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	557183493	557025290	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	582597001	79854445	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	582597001	581952614	0	0
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