Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	160	1			T44	1		T78	1		T39	2
index[0x1]	166	1			T16	1		T31	1		T41	1
index[0x2]	165	1			T11	1		T29	1		T38	3
index[0x3]	167	1			T16	1		T13	1		T29	2

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	215	1			T11	1		T16	2		T13	1
lens_less_than_1000[1]	110	1			T29	2		T39	2		T35	1
lens_less_than_1000[2]	125	1			T31	1		T38	2		T23	1
lens_less_than_1000[3]	58	1			T29	1		T32	1		T284	1
lens_less_than_1000[4]	56	1			T44	1		T65	1		T23	1
lens_less_than_1000[5]	29	1			T81	2		T48	1		T124	1
lens_less_than_1000[6]	21	1			T35	1		T48	1		T108	2
lens_less_than_1000[7]	22	1			T41	1		T124	2		T115	1
lens_less_than_1000[8]	11	1			T35	1		T285	1		T286	1
lens_less_than_1000[9]	3	1			T287	2		T288	1		-	-
len_2	8	1			T37	1		T58	1		T289	2

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[8]]	0	1	1
[index[0x2]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	52	1			T78	1		T34	1		T35	1
index[0x0]	lens_less_than_1000[1]	26	1			T39	2		T49	1		T124	2
index[0x0]	lens_less_than_1000[2]	28	1			T108	1		T290	1		T57	2
index[0x0]	lens_less_than_1000[3]	12	1			T37	1		T51	1		T52	1
index[0x0]	lens_less_than_1000[4]	22	1			T44	1		T23	1		T52	1
index[0x0]	lens_less_than_1000[5]	7	1			T291	1		T55	1		T292	1
index[0x0]	lens_less_than_1000[6]	8	1			T48	1		T108	2		T70	1
index[0x0]	lens_less_than_1000[7]	2	1			T59	1		T293	1		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T287	1		-	-		-	-
index[0x0]	len_2	2	1			T58	1		T289	1		-	-
index[0x1]	lens_less_than_1000[0]	51	1			T16	1		T109	1		T79	2
index[0x1]	lens_less_than_1000[1]	28	1			T48	1		T51	1		T198	1
index[0x1]	lens_less_than_1000[2]	39	1			T31	1		T38	2		T220	1
index[0x1]	lens_less_than_1000[3]	14	1			T294	1		T287	1		T295	1
index[0x1]	lens_less_than_1000[4]	8	1			T65	1		T296	1		T297	1
index[0x1]	lens_less_than_1000[5]	8	1			T48	1		T298	1		T111	1
index[0x1]	lens_less_than_1000[6]	3	1			T257	1		T299	1		T300	1
index[0x1]	lens_less_than_1000[7]	7	1			T41	1		T124	2		T301	1
index[0x1]	lens_less_than_1000[8]	3	1			T35	1		T302	1		T117	1
index[0x1]	lens_less_than_1000[9]	1	1			T287	1		-	-		-	-
index[0x1]	len_2	4	1			T37	1		T104	1		T303	2
index[0x2]	lens_less_than_1000[0]	54	1			T11	1		T38	3		T45	1
index[0x2]	lens_less_than_1000[1]	36	1			T35	1		T48	1		T36	1
index[0x2]	lens_less_than_1000[2]	22	1			T23	1		T58	1		T304	1
index[0x2]	lens_less_than_1000[3]	14	1			T29	1		T48	1		T305	1
index[0x2]	lens_less_than_1000[4]	21	1			T240	1		T98	1		T120	10
index[0x2]	lens_less_than_1000[5]	6	1			T81	1		T124	1		T306	1
index[0x2]	lens_less_than_1000[6]	6	1			T35	1		T306	1		T263	1
index[0x2]	lens_less_than_1000[7]	2	1			T307	1		T308	1		-	-
index[0x2]	lens_less_than_1000[8]	3	1			T286	1		T309	1		T310	1
index[0x2]	len_2	1	1			T311	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	58	1			T16	1		T13	1		T80	1
index[0x3]	lens_less_than_1000[1]	20	1			T29	2		T251	1		T101	3
index[0x3]	lens_less_than_1000[2]	36	1			T99	1		T312	1		T36	1
index[0x3]	lens_less_than_1000[3]	18	1			T32	1		T284	1		T294	1
index[0x3]	lens_less_than_1000[4]	5	1			T313	1		T55	1		T314	1
index[0x3]	lens_less_than_1000[5]	8	1			T81	1		T98	1		T57	1
index[0x3]	lens_less_than_1000[6]	4	1			T315	1		T123	1		T267	1
index[0x3]	lens_less_than_1000[7]	11	1			T115	1		T59	1		T307	1
index[0x3]	lens_less_than_1000[8]	5	1			T285	1		T316	1		T116	1
index[0x3]	lens_less_than_1000[9]	1	1			T288	1		-	-		-	-
index[0x3]	len_2	1	1			T289	1		-	-		-	-