Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	59	1			T32	1		T46	1		T65	2
class_index[0x1]	52	1			T29	2		T46	1		T79	2
class_index[0x2]	40	1			T31	1		T65	2		T51	1
class_index[0x3]	48	1			T65	1		T79	1		T76	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	102	1			T32	1		T65	4		T79	1
intr_timeout_cnt[1]	37	1			T29	2		T46	1		T79	2
intr_timeout_cnt[2]	16	1			T46	1		T89	2		T90	1
intr_timeout_cnt[3]	10	1			T51	1		T90	2		T262	1
intr_timeout_cnt[4]	7	1			T65	1		T81	1		T129	1
intr_timeout_cnt[5]	4	1			T90	1		T129	1		T263	1
intr_timeout_cnt[6]	5	1			T31	1		T264	1		T265	3
intr_timeout_cnt[7]	5	1			T116	1		T62	1		T266	1
intr_timeout_cnt[8]	4	1			T116	1		T266	1		T267	1
intr_timeout_cnt[9]	9	1			T123	1		T268	2		T269	5

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[6]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	29	1			T32	1		T65	2		T87	1
class_index[0x0]	intr_timeout_cnt[1]	14	1			T46	1		T89	1		T91	2
class_index[0x0]	intr_timeout_cnt[2]	5	1			T90	1		T270	1		T269	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T262	1		T269	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	1	1			T271	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[5]	1	1			T263	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	4	1			T264	1		T265	3		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T272	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T273	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T123	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	23	1			T48	1		T36	1		T37	1
class_index[0x1]	intr_timeout_cnt[1]	13	1			T29	2		T79	2		T76	1
class_index[0x1]	intr_timeout_cnt[2]	2	1			T46	1		T123	1		-	-
class_index[0x1]	intr_timeout_cnt[3]	2	1			T51	1		T267	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T81	1		T129	1		T274	1
class_index[0x1]	intr_timeout_cnt[5]	1	1			T90	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T266	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T267	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	6	1			T269	5		T275	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	24	1			T65	2		T53	3		T113	1
class_index[0x2]	intr_timeout_cnt[1]	6	1			T51	1		T59	1		T63	1
class_index[0x2]	intr_timeout_cnt[2]	2	1			T91	1		T268	1		-	-
class_index[0x2]	intr_timeout_cnt[3]	3	1			T276	1		T277	1		T278	1
class_index[0x2]	intr_timeout_cnt[4]	1	1			T265	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T274	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T31	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T62	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T116	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	26	1			T79	1		T76	1		T119	2
class_index[0x3]	intr_timeout_cnt[1]	4	1			T119	1		T279	1		T280	1
class_index[0x3]	intr_timeout_cnt[2]	7	1			T89	2		T102	1		T281	1
class_index[0x3]	intr_timeout_cnt[3]	3	1			T90	2		T60	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	2	1			T65	1		T282	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	1	1			T129	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T116	1		T283	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T266	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T268	2		-	-		-	-