Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	286660	1			T1	5		T2	9		T3	11
all_values[1]	286660	1			T1	5		T2	9		T3	11
all_values[2]	286660	1			T1	5		T2	9		T3	11
all_values[3]	286660	1			T1	5		T2	9		T3	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

570431

1

T1

13

T2

32

T3

26

auto[1]

576209

1

T1

7

T2

4

T3

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

682983

1

T1

13

T2

32

T3

40

auto[1]

463657

1

T1

7

T2

4

T3

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	83476	1			T2	5		T3	4		T10	8
all_values[0]	auto[0]	auto[1]	59304	1			T2	4		T3	3		T10	7
all_values[0]	auto[1]	auto[0]	84280	1			T1	3		T3	3		T10	3
all_values[0]	auto[1]	auto[1]	59600	1			T1	2		T3	1		T10	3
all_values[1]	auto[0]	auto[0]	84566	1			T1	3		T2	7		T3	5
all_values[1]	auto[0]	auto[1]	58179	1			T1	2		T10	7		T17	1
all_values[1]	auto[1]	auto[0]	85768	1			T2	2		T3	6		T10	3
all_values[1]	auto[1]	auto[1]	58147	1			T10	3		T17	1		T16	2
all_values[2]	auto[0]	auto[0]	84058	1			T1	3		T2	9		T3	7
all_values[2]	auto[0]	auto[1]	58218	1			T1	2		T10	5		T17	1
all_values[2]	auto[1]	auto[0]	85967	1			T3	4		T10	5		T17	1
all_values[2]	auto[1]	auto[1]	58417	1			T10	3		T17	1		T16	1
all_values[3]	auto[0]	auto[0]	86636	1			T1	3		T2	7		T3	7
all_values[3]	auto[0]	auto[1]	55994	1			T10	3		T17	2		T16	3
all_values[3]	auto[1]	auto[0]	88232	1			T1	1		T2	2		T3	4
all_values[3]	auto[1]	auto[1]	55798	1			T1	1		T10	2		T16	3