Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	286660	1			T1	5		T2	9		T3	11
all_pins[1]	286660	1			T1	5		T2	9		T3	11
all_pins[2]	286660	1			T1	5		T2	9		T3	11
all_pins[3]	286660	1			T1	5		T2	9		T3	11

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	914678	1			T1	17		T2	36		T3	43
values[0x1]	231962	1			T1	3		T3	1		T10	11
transitions[0x0=>0x1]	153933	1			T1	2		T10	9		T17	2
transitions[0x1=>0x0]	154188	1			T1	3		T3	1		T10	9

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	227060	1			T1	3		T2	9		T3	10
all_pins[0]	values[0x1]	59600	1			T1	2		T3	1		T10	3
all_pins[0]	transitions[0x0=>0x1]	59088	1			T1	1		T10	3		T17	1
all_pins[0]	transitions[0x1=>0x0]	55541	1			T1	1		T10	2		T16	3
all_pins[1]	values[0x0]	228513	1			T1	5		T2	9		T3	11
all_pins[1]	values[0x1]	58147	1			T10	3		T17	1		T16	2
all_pins[1]	transitions[0x0=>0x1]	32209	1			T10	2		T16	1		T13	2
all_pins[1]	transitions[0x1=>0x0]	33662	1			T1	2		T3	1		T10	2
all_pins[2]	values[0x0]	228243	1			T1	5		T2	9		T3	11
all_pins[2]	values[0x1]	58417	1			T10	3		T17	1		T16	1
all_pins[2]	transitions[0x0=>0x1]	32130	1			T10	2		T17	1		T16	1
all_pins[2]	transitions[0x1=>0x0]	31860	1			T10	2		T17	1		T16	2
all_pins[3]	values[0x0]	230862	1			T1	4		T2	9		T3	11
all_pins[3]	values[0x1]	55798	1			T1	1		T10	2		T16	3
all_pins[3]	transitions[0x0=>0x1]	30506	1			T1	1		T10	2		T16	2
all_pins[3]	transitions[0x1=>0x0]	33125	1			T10	3		T17	1		T13	3