Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	245	1			T176	7		T178	4		T260	7
all_values[1]	245	1			T176	7		T178	4		T260	7
all_values[2]	245	1			T176	7		T178	4		T260	7
all_values[3]	245	1			T176	7		T178	4		T260	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

533

1

T176

14

T178

7

T260

18

auto[1]

447

1

T176

14

T178

9

T260

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

405

1

T176

10

T178

7

T260

11

auto[1]

575

1

T176

18

T178

9

T260

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

596

1

T176

17

T178

11

T260

15

auto[1]

384

1

T176

11

T178

5

T260

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

48

1

T176

1

T178

1

T260

2

all_values[0]

auto[0]

auto[0]

auto[1]

21

1

T176

1

T178

1

T261

1

all_values[0]

auto[0]

auto[1]

auto[0]

44

1

T178

1

T260

2

T376

1

all_values[0]

auto[0]

auto[1]

auto[1]

33

1

T176

3

T377

3

T376

1

all_values[0]

auto[1]

auto[0]

auto[1]

56

1

T176

2

T260

2

T378

1

all_values[0]

auto[1]

auto[1]

auto[1]

43

1

T178

1

T260

1

T261

2

all_values[1]

auto[0]

auto[0]

auto[0]

57

1

T176

2

T178

1

T376

2

all_values[1]

auto[0]

auto[0]

auto[1]

26

1

T260

1

T261

1

T379

1

all_values[1]

auto[0]

auto[1]

auto[0]

46

1

T176

3

T178

2

T260

3

all_values[1]

auto[0]

auto[1]

auto[1]

24

1

T378

2

T261

1

T377

2

all_values[1]

auto[1]

auto[0]

auto[1]

56

1

T176

2

T260

3

T378

1

all_values[1]

auto[1]

auto[1]

auto[1]

36

1

T178

1

T379

1

T380

3

all_values[2]

auto[0]

auto[0]

auto[0]

63

1

T176

2

T178

1

T260

1

all_values[2]

auto[0]

auto[0]

auto[1]

15

1

T260

2

T380

1

T381

1

all_values[2]

auto[0]

auto[1]

auto[0]

48

1

T176

1

T377

1

T376

1

all_values[2]

auto[0]

auto[1]

auto[1]

25

1

T176

1

T178

1

T378

3

all_values[2]

auto[1]

auto[0]

auto[1]

51

1

T176

1

T178

1

T260

2

all_values[2]

auto[1]

auto[1]

auto[1]

43

1

T176

2

T178

1

T260

2

all_values[3]

auto[0]

auto[0]

auto[0]

62

1

T176

1

T178

1

T260

2

all_values[3]

auto[0]

auto[0]

auto[1]

20

1

T260

1

T380

1

T382

2

all_values[3]

auto[0]

auto[1]

auto[0]

37

1

T260

1

T261

2

T376

1

all_values[3]

auto[0]

auto[1]

auto[1]

27

1

T176

2

T178

2

T378

2

all_values[3]

auto[1]

auto[0]

auto[1]

58

1

T176

2

T178

1

T260

2

all_values[3]

auto[1]

auto[1]

auto[1]

41

1

T176

2

T260

1

T378

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal