Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	71023	1			T240	813		T241	294		T108	251
accum_cnt_1000	163669	1			T44	5		T324	119		T48	3
accum_cnt_100	17957	1			T31	4		T44	28		T38	2
accum_cnt_50	51705	1			T14	3		T31	72		T44	73
accum_cnt_10	168112	1			T1	7		T2	3		T3	1
accum_cnt_0	341745	1			T1	9		T2	21		T3	27

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	212186	1			T1	4		T2	6		T3	7
class_index[0x1]	212186	1			T1	4		T2	6		T3	7
class_index[0x2]	212186	1			T1	4		T2	6		T3	7
class_index[0x3]	212186	1			T1	4		T2	6		T3	7

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	20477	1			T240	335		T241	294		T242	366
class_index[0x0]	accum_cnt_1000	43494	1			T324	63		T36	4		T239	612
class_index[0x0]	accum_cnt_100	4955	1			T38	2		T92	2		T324	14
class_index[0x0]	accum_cnt_50	15007	1			T31	20		T44	22		T38	14
class_index[0x0]	accum_cnt_10	42442	1			T1	2		T2	3		T3	1
class_index[0x0]	accum_cnt_0	77375	1			T1	2		T2	3		T3	6
class_index[0x1]	accum_cnt_2000	15794	1			T53	459		T98	537		T291	231
class_index[0x1]	accum_cnt_1000	38415	1			T48	3		T239	663		T325	2
class_index[0x1]	accum_cnt_100	4218	1			T45	15		T48	23		T36	19
class_index[0x1]	accum_cnt_50	9142	1			T31	14		T44	24		T45	17
class_index[0x1]	accum_cnt_10	47355	1			T1	1		T13	20		T14	8
class_index[0x1]	accum_cnt_0	91700	1			T1	3		T2	6		T3	7
class_index[0x2]	accum_cnt_2000	19519	1			T240	478		T108	251		T50	137
class_index[0x2]	accum_cnt_1000	43030	1			T324	56		T220	2		T239	658
class_index[0x2]	accum_cnt_100	4323	1			T44	13		T45	15		T83	4
class_index[0x2]	accum_cnt_50	12763	1			T31	18		T44	16		T45	17
class_index[0x2]	accum_cnt_10	37699	1			T10	5		T16	3		T13	10
class_index[0x2]	accum_cnt_0	82765	1			T1	4		T2	6		T3	7
class_index[0x3]	accum_cnt_2000	15233	1			T52	265		T326	41		T327	408
class_index[0x3]	accum_cnt_1000	38730	1			T44	5		T239	632		T296	13
class_index[0x3]	accum_cnt_100	4461	1			T31	4		T44	15		T45	13
class_index[0x3]	accum_cnt_50	14793	1			T14	3		T31	20		T44	11
class_index[0x3]	accum_cnt_10	40616	1			T1	4		T10	11		T17	3
class_index[0x3]	accum_cnt_0	89905	1			T2	6		T3	7		T10	2