Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	8317	1			T35	1		T246	1		T106	2
alert[0x1]	5429	1			T31	2		T36	26		T51	40
alert[0x2]	3851	1			T105	22		T131	1		T48	2
alert[0x3]	6674	1			T31	3		T36	8		T72	1
alert[0x4]	2477	1			T19	1		T80	2		T36	3
alert[0x5]	1313	1			T20	1		T131	1		T36	2
alert[0x6]	2279	1			T31	4		T36	1		T318	1
alert[0x7]	3727	1			T35	37		T201	1		T106	1
alert[0x8]	2534	1			T18	1		T35	6		T20	1
alert[0x9]	8336	1			T18	1		T131	1		T36	1
alert[0xa]	9388	1			T16	1		T35	48		T112	1
alert[0xb]	2262	1			T35	2		T131	1		T48	1
alert[0xc]	3193	1			T10	3		T35	11		T48	1
alert[0xd]	4369	1			T18	1		T105	2		T112	1
alert[0xe]	6599	1			T31	1		T105	2		T35	2
alert[0xf]	7151	1			T35	4		T294	1		T49	1
alert[0x10]	1516	1			T18	1		T48	1		T106	2
alert[0x11]	1975	1			T19	1		T35	24		T48	8
alert[0x12]	8521	1			T31	24		T35	2		T201	2
alert[0x13]	7639	1			T19	1		T319	1		T328	1
alert[0x14]	4332	1			T131	2		T36	5		T106	1
alert[0x15]	2870	1			T241	11		T317	1		T329	1
alert[0x16]	3422	1			T31	2		T19	1		T131	1
alert[0x17]	7355	1			T35	2		T36	123		T50	432
alert[0x18]	4739	1			T19	1		T105	3		T237	1
alert[0x19]	3634	1			T105	1		T35	36		T241	117
alert[0x1a]	2334	1			T105	1		T81	4		T48	1
alert[0x1b]	4660	1			T49	3		T53	630		T55	34
alert[0x1c]	4895	1			T16	2		T31	1		T41	1
alert[0x1d]	3990	1			T201	1		T50	829		T72	1
alert[0x1e]	4024	1			T19	1		T131	1		T36	1
alert[0x1f]	5838	1			T19	1		T105	35		T131	1
alert[0x20]	6490	1			T31	3		T35	2		T53	575
alert[0x21]	3315	1			T19	1		T35	11		T201	1
alert[0x22]	4160	1			T35	8		T20	1		T36	2
alert[0x23]	5519	1			T20	1		T112	1		T201	1
alert[0x24]	5580	1			T201	1		T72	1		T51	10
alert[0x25]	4238	1			T201	1		T50	64		T72	1
alert[0x26]	2344	1			T31	1		T105	15		T246	1
alert[0x27]	10546	1			T16	2		T105	4		T201	1
alert[0x28]	8397	1			T31	2		T109	2		T201	1
alert[0x29]	4189	1			T109	1		T48	2		T51	292
alert[0x2a]	5854	1			T10	1		T36	1		T330	3
alert[0x2b]	11023	1			T35	6		T20	1		T50	64
alert[0x2c]	4926	1			T19	1		T112	1		T131	1
alert[0x2d]	4264	1			T16	1		T46	6		T18	1
alert[0x2e]	2201	1			T246	1		T36	2		T294	1
alert[0x2f]	3620	1			T294	1		T50	29		T329	1
alert[0x30]	6725	1			T35	27		T112	1		T237	2
alert[0x31]	3004	1			T16	1		T50	317		T72	1
alert[0x32]	3138	1			T35	1		T106	1		T241	10
alert[0x33]	4279	1			T36	47		T241	208		T50	26
alert[0x34]	7458	1			T131	1		T51	120		T331	1216
alert[0x35]	4367	1			T10	9		T18	1		T105	16
alert[0x36]	3287	1			T16	1		T31	3		T35	3
alert[0x37]	3984	1			T49	1		T330	4		T51	117
alert[0x38]	13480	1			T48	33		T241	4		T49	7
alert[0x39]	5632	1			T35	14		T20	1		T36	3
alert[0x3a]	3679	1			T20	1		T131	1		T246	1
alert[0x3b]	6185	1			T20	1		T112	1		T131	1
alert[0x3c]	2207	1			T46	1		T35	7		T131	1
alert[0x3d]	3387	1			T35	19		T112	1		T201	1
alert[0x3e]	3674	1			T18	1		T20	1		T36	21
alert[0x3f]	4911	1			T36	8		T241	29		T49	9
alert[0x40]	2238	1			T109	6		T35	7		T241	214

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	63030	1			T18	7		T19	1		T105	101
class_i[0x1]	68639	1			T10	3		T46	7		T19	1
class_i[0x2]	70250	1			T10	10		T19	1		T35	244
class_i[0x3]	116025	1			T16	8		T31	46		T41	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

317213

1

T10

13

T16

8

T31

46

alert_ping_fail

731

1

T18

7

T19

10

T20

10

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	8312	1			T35	1		T50	15		T51	39
alert_integrity_fail	alert[0x1]	5419	1			T31	2		T36	26		T51	40
alert_integrity_fail	alert[0x2]	3832	1			T105	22		T48	2		T36	3
alert_integrity_fail	alert[0x3]	6667	1			T31	3		T36	8		T331	36
alert_integrity_fail	alert[0x4]	2471	1			T80	2		T36	3		T242	2
alert_integrity_fail	alert[0x5]	1299	1			T36	2		T124	2		T53	7
alert_integrity_fail	alert[0x6]	2270	1			T31	4		T36	1		T291	171
alert_integrity_fail	alert[0x7]	3720	1			T35	37		T49	31		T51	63
alert_integrity_fail	alert[0x8]	2520	1			T35	6		T48	2		T36	21
alert_integrity_fail	alert[0x9]	8327	1			T36	1		T241	5		T51	32
alert_integrity_fail	alert[0xa]	9371	1			T16	1		T35	48		T36	15
alert_integrity_fail	alert[0xb]	2250	1			T35	2		T48	1		T49	2
alert_integrity_fail	alert[0xc]	3186	1			T10	3		T35	11		T48	1
alert_integrity_fail	alert[0xd]	4349	1			T105	2		T36	19		T53	563
alert_integrity_fail	alert[0xe]	6586	1			T31	1		T105	2		T35	2
alert_integrity_fail	alert[0xf]	7143	1			T35	4		T49	1		T330	7
alert_integrity_fail	alert[0x10]	1507	1			T48	1		T241	8		T51	13
alert_integrity_fail	alert[0x11]	1964	1			T35	24		T48	8		T49	2
alert_integrity_fail	alert[0x12]	8507	1			T31	24		T35	2		T241	657
alert_integrity_fail	alert[0x13]	7628	1			T57	3		T217	45		T295	755
alert_integrity_fail	alert[0x14]	4318	1			T36	5		T241	12		T50	23
alert_integrity_fail	alert[0x15]	2853	1			T241	11		T291	18		T55	164
alert_integrity_fail	alert[0x16]	3413	1			T31	2		T48	4		T36	27
alert_integrity_fail	alert[0x17]	7346	1			T35	2		T36	123		T50	432
alert_integrity_fail	alert[0x18]	4727	1			T105	3		T237	1		T49	5
alert_integrity_fail	alert[0x19]	3624	1			T105	1		T35	36		T241	117
alert_integrity_fail	alert[0x1a]	2321	1			T105	1		T81	4		T48	1
alert_integrity_fail	alert[0x1b]	4650	1			T49	3		T53	630		T55	34
alert_integrity_fail	alert[0x1c]	4884	1			T16	2		T31	1		T41	1
alert_integrity_fail	alert[0x1d]	3973	1			T50	829		T331	37		T119	3
alert_integrity_fail	alert[0x1e]	4012	1			T36	1		T50	176		T51	74
alert_integrity_fail	alert[0x1f]	5824	1			T105	35		T48	4		T36	3
alert_integrity_fail	alert[0x20]	6480	1			T31	3		T35	2		T53	575
alert_integrity_fail	alert[0x21]	3304	1			T35	11		T48	2		T119	4
alert_integrity_fail	alert[0x22]	4152	1			T35	8		T36	2		T241	127
alert_integrity_fail	alert[0x23]	5505	1			T49	8		T119	1		T55	427
alert_integrity_fail	alert[0x24]	5571	1			T51	10		T53	45		T291	355
alert_integrity_fail	alert[0x25]	4227	1			T50	64		T51	5		T53	44
alert_integrity_fail	alert[0x26]	2338	1			T31	1		T105	15		T49	2
alert_integrity_fail	alert[0x27]	10538	1			T16	2		T105	4		T51	13
alert_integrity_fail	alert[0x28]	8386	1			T31	2		T109	2		T36	23
alert_integrity_fail	alert[0x29]	4178	1			T109	1		T48	2		T51	292
alert_integrity_fail	alert[0x2a]	5846	1			T10	1		T36	1		T330	3
alert_integrity_fail	alert[0x2b]	11011	1			T35	6		T50	64		T51	432
alert_integrity_fail	alert[0x2c]	4904	1			T237	1		T49	6		T331	3
alert_integrity_fail	alert[0x2d]	4247	1			T16	1		T46	6		T50	181
alert_integrity_fail	alert[0x2e]	2185	1			T36	2		T50	8		T256	8
alert_integrity_fail	alert[0x2f]	3610	1			T50	29		T291	25		T91	1
alert_integrity_fail	alert[0x30]	6714	1			T35	27		T237	2		T50	23
alert_integrity_fail	alert[0x31]	2995	1			T16	1		T50	317		T331	14
alert_integrity_fail	alert[0x32]	3124	1			T35	1		T241	10		T330	1
alert_integrity_fail	alert[0x33]	4270	1			T36	47		T241	208		T50	26
alert_integrity_fail	alert[0x34]	7449	1			T51	120		T331	1216		T53	14
alert_integrity_fail	alert[0x35]	4355	1			T10	9		T105	16		T48	7
alert_integrity_fail	alert[0x36]	3276	1			T16	1		T31	3		T35	3
alert_integrity_fail	alert[0x37]	3974	1			T49	1		T330	4		T51	117
alert_integrity_fail	alert[0x38]	13473	1			T48	33		T241	4		T49	7
alert_integrity_fail	alert[0x39]	5623	1			T35	14		T36	3		T50	54
alert_integrity_fail	alert[0x3a]	3667	1			T331	45		T53	419		T291	2158
alert_integrity_fail	alert[0x3b]	6166	1			T49	1		T124	53		T89	1
alert_integrity_fail	alert[0x3c]	2193	1			T46	1		T35	7		T48	2
alert_integrity_fail	alert[0x3d]	3377	1			T35	19		T50	43		T55	217
alert_integrity_fail	alert[0x3e]	3657	1			T36	21		T330	1		T51	75
alert_integrity_fail	alert[0x3f]	4910	1			T36	8		T241	29		T49	9
alert_integrity_fail	alert[0x40]	2235	1			T109	6		T35	7		T241	214
alert_ping_fail	alert[0x0]	5	1			T246	1		T106	2		T332	1
alert_ping_fail	alert[0x1]	10	1			T298	2		T314	2		T333	1
alert_ping_fail	alert[0x2]	19	1			T131	1		T246	1		T334	1
alert_ping_fail	alert[0x3]	7	1			T72	1		T335	2		T336	1
alert_ping_fail	alert[0x4]	6	1			T19	1		T106	1		T328	1
alert_ping_fail	alert[0x5]	14	1			T20	1		T131	1		T337	1
alert_ping_fail	alert[0x6]	9	1			T318	1		T332	1		T323	1
alert_ping_fail	alert[0x7]	7	1			T201	1		T106	1		T314	1
alert_ping_fail	alert[0x8]	14	1			T18	1		T20	1		T201	1
alert_ping_fail	alert[0x9]	9	1			T18	1		T131	1		T107	1
alert_ping_fail	alert[0xa]	17	1			T112	1		T246	1		T294	1
alert_ping_fail	alert[0xb]	12	1			T131	1		T106	1		T334	1
alert_ping_fail	alert[0xc]	7	1			T328	1		T107	1		T338	1
alert_ping_fail	alert[0xd]	20	1			T18	1		T112	1		T246	1
alert_ping_fail	alert[0xe]	13	1			T294	1		T339	1		T316	1
alert_ping_fail	alert[0xf]	8	1			T294	1		T334	1		T337	1
alert_ping_fail	alert[0x10]	9	1			T18	1		T106	2		T334	2
alert_ping_fail	alert[0x11]	11	1			T19	1		T334	1		T298	1
alert_ping_fail	alert[0x12]	14	1			T201	2		T246	1		T294	1
alert_ping_fail	alert[0x13]	11	1			T19	1		T319	1		T328	1
alert_ping_fail	alert[0x14]	14	1			T131	2		T106	1		T294	1
alert_ping_fail	alert[0x15]	17	1			T317	1		T329	1		T298	1
alert_ping_fail	alert[0x16]	9	1			T19	1		T131	1		T328	1
alert_ping_fail	alert[0x17]	9	1			T337	1		T120	1		T304	1
alert_ping_fail	alert[0x18]	12	1			T19	1		T332	1		T107	1
alert_ping_fail	alert[0x19]	10	1			T72	2		T334	1		T328	2
alert_ping_fail	alert[0x1a]	13	1			T106	1		T316	1		T314	1
alert_ping_fail	alert[0x1b]	10	1			T340	1		T339	1		T338	1
alert_ping_fail	alert[0x1c]	11	1			T20	1		T332	2		T298	1
alert_ping_fail	alert[0x1d]	17	1			T201	1		T72	1		T329	1
alert_ping_fail	alert[0x1e]	12	1			T19	1		T131	1		T328	2
alert_ping_fail	alert[0x1f]	14	1			T19	1		T131	1		T305	1
alert_ping_fail	alert[0x20]	10	1			T332	1		T298	1		T340	1
alert_ping_fail	alert[0x21]	11	1			T19	1		T201	1		T72	1
alert_ping_fail	alert[0x22]	8	1			T20	1		T106	1		T298	1
alert_ping_fail	alert[0x23]	14	1			T20	1		T112	1		T201	1
alert_ping_fail	alert[0x24]	9	1			T201	1		T72	1		T334	1
alert_ping_fail	alert[0x25]	11	1			T201	1		T72	1		T337	1
alert_ping_fail	alert[0x26]	6	1			T246	1		T339	2		T341	1
alert_ping_fail	alert[0x27]	8	1			T201	1		T131	1		T332	1
alert_ping_fail	alert[0x28]	11	1			T201	1		T106	1		T317	1
alert_ping_fail	alert[0x29]	11	1			T107	1		T340	1		T333	2
alert_ping_fail	alert[0x2a]	8	1			T333	2		T342	2		T343	1
alert_ping_fail	alert[0x2b]	12	1			T20	1		T72	1		T332	1
alert_ping_fail	alert[0x2c]	22	1			T19	1		T112	1		T131	1
alert_ping_fail	alert[0x2d]	17	1			T18	1		T19	1		T329	1
alert_ping_fail	alert[0x2e]	16	1			T246	1		T294	1		T334	1
alert_ping_fail	alert[0x2f]	10	1			T294	1		T329	1		T339	1
alert_ping_fail	alert[0x30]	11	1			T112	1		T332	1		T107	1
alert_ping_fail	alert[0x31]	9	1			T72	1		T340	1		T344	1
alert_ping_fail	alert[0x32]	14	1			T106	1		T332	1		T316	1
alert_ping_fail	alert[0x33]	9	1			T332	1		T298	1		T339	1
alert_ping_fail	alert[0x34]	9	1			T131	1		T334	1		T332	1
alert_ping_fail	alert[0x35]	12	1			T18	1		T131	1		T337	2
alert_ping_fail	alert[0x36]	11	1			T106	1		T314	2		T120	1
alert_ping_fail	alert[0x37]	10	1			T334	2		T337	1		T344	1
alert_ping_fail	alert[0x38]	7	1			T337	1		T333	1		T345	1
alert_ping_fail	alert[0x39]	9	1			T20	1		T314	2		T120	1
alert_ping_fail	alert[0x3a]	12	1			T20	1		T131	1		T246	1
alert_ping_fail	alert[0x3b]	19	1			T20	1		T112	1		T131	1
alert_ping_fail	alert[0x3c]	14	1			T131	1		T72	2		T334	1
alert_ping_fail	alert[0x3d]	10	1			T112	1		T201	1		T346	1
alert_ping_fail	alert[0x3e]	17	1			T18	1		T20	1		T72	1
alert_ping_fail	alert[0x3f]	1	1			T347	1		-	-		-	-
alert_ping_fail	alert[0x40]	3	1			T72	1		T339	1		T120	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	62788	1			T105	101		T109	9		T35	28
alert_integrity_fail	class_i[0x1]	68447	1			T10	3		T46	7		T35	8
alert_integrity_fail	class_i[0x2]	70132	1			T10	10		T35	244		T48	32
alert_integrity_fail	class_i[0x3]	115846	1			T16	8		T31	46		T41	1
alert_ping_fail	class_i[0x0]	242	1			T18	7		T19	1		T112	6
alert_ping_fail	class_i[0x1]	192	1			T19	1		T201	11		T131	2
alert_ping_fail	class_i[0x2]	118	1			T19	1		T20	1		T112	1
alert_ping_fail	class_i[0x3]	179	1			T19	7		T20	9		T246	7