Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.23 99.99 98.63 97.06 100.00 100.00 99.38 99.52


Total test records in report: 827
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T779 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.1015773163 Aug 24 01:56:01 AM UTC 24 Aug 24 01:56:03 AM UTC 24 20252569 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.158455843 Aug 24 01:55:56 AM UTC 24 Aug 24 01:56:04 AM UTC 24 243706343 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.74183034 Aug 24 01:56:04 AM UTC 24 Aug 24 01:56:12 AM UTC 24 242262148 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.137408727 Aug 24 01:56:13 AM UTC 24 Aug 24 01:56:19 AM UTC 24 263122579 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.4074239725 Aug 24 01:56:05 AM UTC 24 Aug 24 01:56:20 AM UTC 24 270620096 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.356706265 Aug 24 01:56:01 AM UTC 24 Aug 24 01:56:30 AM UTC 24 1834638898 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.2975253055 Aug 24 01:56:30 AM UTC 24 Aug 24 01:56:40 AM UTC 24 144988957 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.1318145290 Aug 24 01:56:41 AM UTC 24 Aug 24 01:56:43 AM UTC 24 8793257 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.729832189 Aug 24 01:56:44 AM UTC 24 Aug 24 01:56:53 AM UTC 24 775628450 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3432302760 Aug 24 01:50:43 AM UTC 24 Aug 24 01:57:10 AM UTC 24 16047199516 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1110096867 Aug 24 01:54:42 AM UTC 24 Aug 24 01:57:13 AM UTC 24 3179245516 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1262353474 Aug 24 01:56:39 AM UTC 24 Aug 24 01:57:13 AM UTC 24 618112004 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1161483956 Aug 24 01:56:54 AM UTC 24 Aug 24 01:57:15 AM UTC 24 170604437 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.911309109 Aug 24 01:57:11 AM UTC 24 Aug 24 01:57:19 AM UTC 24 396899516 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.1163331894 Aug 24 01:57:15 AM UTC 24 Aug 24 01:57:22 AM UTC 24 175714601 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.207757831 Aug 24 01:57:23 AM UTC 24 Aug 24 01:57:25 AM UTC 24 7421088 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.3322855341 Aug 24 01:57:26 AM UTC 24 Aug 24 01:57:29 AM UTC 24 185069328 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.211514942 Aug 24 01:57:20 AM UTC 24 Aug 24 01:57:39 AM UTC 24 181506421 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1942301975 Aug 24 01:54:05 AM UTC 24 Aug 24 01:57:48 AM UTC 24 18342922891 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1982587884 Aug 24 01:57:40 AM UTC 24 Aug 24 01:57:48 AM UTC 24 60364133 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2003964944 Aug 24 01:57:30 AM UTC 24 Aug 24 01:57:50 AM UTC 24 635838866 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2369713015 Aug 24 01:57:52 AM UTC 24 Aug 24 01:57:56 AM UTC 24 118231411 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.1337422682 Aug 24 01:57:57 AM UTC 24 Aug 24 01:57:59 AM UTC 24 7953817 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.918978074 Aug 24 01:58:00 AM UTC 24 Aug 24 01:58:05 AM UTC 24 51173708 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.51836753 Aug 24 01:57:51 AM UTC 24 Aug 24 01:58:08 AM UTC 24 480998504 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.361821541 Aug 24 01:52:16 AM UTC 24 Aug 24 01:58:15 AM UTC 24 12271869248 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3653041346 Aug 24 01:58:09 AM UTC 24 Aug 24 01:58:17 AM UTC 24 254441470 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.322995961 Aug 24 01:58:17 AM UTC 24 Aug 24 01:58:19 AM UTC 24 8976593 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.848344854 Aug 24 01:58:18 AM UTC 24 Aug 24 01:58:20 AM UTC 24 16447766 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.2046437837 Aug 24 01:58:20 AM UTC 24 Aug 24 01:58:22 AM UTC 24 12544706 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.1051472910 Aug 24 01:58:21 AM UTC 24 Aug 24 01:58:23 AM UTC 24 7591542 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1744883133 Aug 24 01:58:06 AM UTC 24 Aug 24 01:58:24 AM UTC 24 631473932 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1656705430 Aug 24 01:54:03 AM UTC 24 Aug 24 01:58:25 AM UTC 24 4596423519 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.828202064 Aug 24 01:58:23 AM UTC 24 Aug 24 01:58:25 AM UTC 24 8065001 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.3955069884 Aug 24 01:58:24 AM UTC 24 Aug 24 01:58:26 AM UTC 24 14423244 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.1619258599 Aug 24 01:58:24 AM UTC 24 Aug 24 01:58:26 AM UTC 24 24092725 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.3866177351 Aug 24 01:58:27 AM UTC 24 Aug 24 01:58:29 AM UTC 24 18770076 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2179220326 Aug 24 01:58:27 AM UTC 24 Aug 24 01:58:29 AM UTC 24 15543471 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.3468926832 Aug 24 01:58:28 AM UTC 24 Aug 24 01:58:30 AM UTC 24 19100184 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.750249860 Aug 24 01:58:28 AM UTC 24 Aug 24 01:58:31 AM UTC 24 53263317 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.695824007 Aug 24 01:56:20 AM UTC 24 Aug 24 01:58:31 AM UTC 24 4781155788 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.707052204 Aug 24 01:58:30 AM UTC 24 Aug 24 01:58:32 AM UTC 24 17549360 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.2300493280 Aug 24 01:58:30 AM UTC 24 Aug 24 01:58:32 AM UTC 24 8244110 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.1087704923 Aug 24 01:58:31 AM UTC 24 Aug 24 01:58:33 AM UTC 24 15475952 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.95767386 Aug 24 01:58:32 AM UTC 24 Aug 24 01:58:34 AM UTC 24 15823222 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.2495108426 Aug 24 01:58:32 AM UTC 24 Aug 24 01:58:35 AM UTC 24 9510283 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.1079174749 Aug 24 01:58:33 AM UTC 24 Aug 24 01:58:35 AM UTC 24 57152687 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.92976974 Aug 24 01:58:33 AM UTC 24 Aug 24 01:58:36 AM UTC 24 8158347 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.1730536956 Aug 24 01:58:34 AM UTC 24 Aug 24 01:58:37 AM UTC 24 7359242 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.152258239 Aug 24 01:58:35 AM UTC 24 Aug 24 01:58:38 AM UTC 24 11859641 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.1223819178 Aug 24 01:58:35 AM UTC 24 Aug 24 01:58:38 AM UTC 24 9633825 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.3828564095 Aug 24 01:58:37 AM UTC 24 Aug 24 01:58:39 AM UTC 24 11228477 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.3039504192 Aug 24 01:58:38 AM UTC 24 Aug 24 01:58:40 AM UTC 24 19382489 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.3754626788 Aug 24 01:58:37 AM UTC 24 Aug 24 01:58:40 AM UTC 24 43927493 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.1056819461 Aug 24 01:58:39 AM UTC 24 Aug 24 01:58:41 AM UTC 24 7720050 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.743447023 Aug 24 01:58:39 AM UTC 24 Aug 24 01:58:41 AM UTC 24 8557847 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.3884342371 Aug 24 01:58:40 AM UTC 24 Aug 24 01:58:42 AM UTC 24 17396517 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.4247460926 Aug 24 01:58:41 AM UTC 24 Aug 24 01:58:43 AM UTC 24 13367941 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.448254154 Aug 24 01:58:41 AM UTC 24 Aug 24 01:58:43 AM UTC 24 9251818 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.1084010103 Aug 24 01:58:42 AM UTC 24 Aug 24 01:58:44 AM UTC 24 8083656 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4149967224 Aug 24 01:55:23 AM UTC 24 Aug 24 01:58:54 AM UTC 24 3921515822 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3991607666 Aug 24 01:54:38 AM UTC 24 Aug 24 01:58:57 AM UTC 24 2372956876 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3499015187 Aug 24 01:55:01 AM UTC 24 Aug 24 01:59:09 AM UTC 24 4846932747 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1898045196 Aug 24 01:55:53 AM UTC 24 Aug 24 01:59:35 AM UTC 24 15178720322 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.39810306 Aug 24 01:53:39 AM UTC 24 Aug 24 01:59:48 AM UTC 24 19361608456 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3744681387 Aug 24 01:55:37 AM UTC 24 Aug 24 01:59:57 AM UTC 24 41264317318 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2741872046 Aug 24 01:46:00 AM UTC 24 Aug 24 02:00:49 AM UTC 24 109090032634 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.4246930447 Aug 24 01:54:59 AM UTC 24 Aug 24 02:01:29 AM UTC 24 6110172408 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.22965239 Aug 24 01:57:49 AM UTC 24 Aug 24 02:01:41 AM UTC 24 16406932552 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1362065371 Aug 24 01:57:13 AM UTC 24 Aug 24 02:02:05 AM UTC 24 14702262964 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1244198072 Aug 24 01:55:49 AM UTC 24 Aug 24 02:02:58 AM UTC 24 8661727358 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3162417980 Aug 24 01:57:13 AM UTC 24 Aug 24 02:03:51 AM UTC 24 24551015762 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3936853023 Aug 24 01:52:55 AM UTC 24 Aug 24 02:05:47 AM UTC 24 50581895140 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3115297251 Aug 24 01:55:37 AM UTC 24 Aug 24 02:07:05 AM UTC 24 48745814254 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.547212380 Aug 24 01:55:20 AM UTC 24 Aug 24 02:07:33 AM UTC 24 27054503743 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2278712763 Aug 24 01:57:49 AM UTC 24 Aug 24 02:08:35 AM UTC 24 134074495335 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1047538101 Aug 24 01:56:19 AM UTC 24 Aug 24 02:10:38 AM UTC 24 54127851465 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.1889321927
Short name T10
Test name
Test status
Simulation time 172922748 ps
CPU time 11.92 seconds
Started Aug 23 11:30:15 PM UTC 24
Finished Aug 23 11:30:29 PM UTC 24
Peak memory 268564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889321927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1889321927
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.2541745208
Short name T31
Test name
Test status
Simulation time 881055778 ps
CPU time 36.19 seconds
Started Aug 23 11:30:52 PM UTC 24
Finished Aug 23 11:31:30 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541745208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2541745208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.1803688399
Short name T8
Test name
Test status
Simulation time 534909685 ps
CPU time 8.41 seconds
Started Aug 23 11:30:45 PM UTC 24
Finished Aug 23 11:30:54 PM UTC 24
Peak memory 297408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803688399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1803688399
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all_with_rand_reset.633491737
Short name T35
Test name
Test status
Simulation time 1870530688 ps
CPU time 168.48 seconds
Started Aug 23 11:31:45 PM UTC 24
Finished Aug 23 11:34:36 PM UTC 24
Peak memory 279416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=633491737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.ale
rt_handler_stress_all_with_rand_reset.633491737
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.1892719330
Short name T5
Test name
Test status
Simulation time 151813702 ps
CPU time 7.08 seconds
Started Aug 23 11:30:40 PM UTC 24
Finished Aug 23 11:30:48 PM UTC 24
Peak memory 262940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892719330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1892719330
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.3699017856
Short name T193
Test name
Test status
Simulation time 467702120 ps
CPU time 7.9 seconds
Started Aug 24 01:42:41 AM UTC 24
Finished Aug 24 01:42:50 AM UTC 24
Peak memory 252444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699017856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3699017856
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.3546599574
Short name T29
Test name
Test status
Simulation time 3831015566 ps
CPU time 41.78 seconds
Started Aug 23 11:30:30 PM UTC 24
Finished Aug 23 11:31:14 PM UTC 24
Peak memory 262844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546599574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3546599574
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all_with_rand_reset.871464909
Short name T49
Test name
Test status
Simulation time 2615036584 ps
CPU time 235.63 seconds
Started Aug 23 11:42:01 PM UTC 24
Finished Aug 23 11:46:00 PM UTC 24
Peak memory 286020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=871464909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.ale
rt_handler_stress_all_with_rand_reset.871464909
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3835872093
Short name T152
Test name
Test status
Simulation time 5291367775 ps
CPU time 265.43 seconds
Started Aug 24 01:49:10 AM UTC 24
Finished Aug 24 01:53:38 AM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835872093 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.3835872093
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1129762951
Short name T174
Test name
Test status
Simulation time 1718141975 ps
CPU time 30.27 seconds
Started Aug 24 01:44:39 AM UTC 24
Finished Aug 24 01:45:10 AM UTC 24
Peak memory 252444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129762951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1129762951
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.1532620540
Short name T53
Test name
Test status
Simulation time 104373639118 ps
CPU time 1332.59 seconds
Started Aug 23 11:32:43 PM UTC 24
Finished Aug 23 11:55:10 PM UTC 24
Peak memory 301888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532620540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1532620540
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.2390383474
Short name T297
Test name
Test status
Simulation time 14690802838 ps
CPU time 1039.02 seconds
Started Aug 23 11:30:19 PM UTC 24
Finished Aug 23 11:47:48 PM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390383474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2390383474
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all_with_rand_reset.2728218085
Short name T122
Test name
Test status
Simulation time 5444371570 ps
CPU time 49.86 seconds
Started Aug 24 12:11:59 AM UTC 24
Finished Aug 24 12:12:50 AM UTC 24
Peak memory 279480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2728218085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.a
lert_handler_stress_all_with_rand_reset.2728218085
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.2261915869
Short name T45
Test name
Test status
Simulation time 1843825754 ps
CPU time 83.82 seconds
Started Aug 23 11:30:21 PM UTC 24
Finished Aug 23 11:31:46 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261915869 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.2261915869
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4283495033
Short name T161
Test name
Test status
Simulation time 4037705340 ps
CPU time 229.52 seconds
Started Aug 24 01:51:43 AM UTC 24
Finished Aug 24 01:55:35 AM UTC 24
Peak memory 279592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283495033 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.4283495033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.2909044385
Short name T120
Test name
Test status
Simulation time 51334158244 ps
CPU time 348.96 seconds
Started Aug 24 12:32:14 AM UTC 24
Finished Aug 24 12:38:07 AM UTC 24
Peak memory 262132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909044385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2909044385
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.1799733487
Short name T103
Test name
Test status
Simulation time 78604169895 ps
CPU time 1715.15 seconds
Started Aug 24 12:34:08 AM UTC 24
Finished Aug 24 01:03:00 AM UTC 24
Peak memory 304680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799733487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1799733487
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/26.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.547212380
Short name T144
Test name
Test status
Simulation time 27054503743 ps
CPU time 724.39 seconds
Started Aug 24 01:55:20 AM UTC 24
Finished Aug 24 02:07:33 AM UTC 24
Peak memory 282100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547212380 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shado
w_reg_errors_with_csr_rw.547212380
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.3775581800
Short name T291
Test name
Test status
Simulation time 148760931990 ps
CPU time 1635.77 seconds
Started Aug 23 11:33:57 PM UTC 24
Finished Aug 24 12:01:29 AM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775581800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3775581800
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4149967224
Short name T148
Test name
Test status
Simulation time 3921515822 ps
CPU time 207.96 seconds
Started Aug 24 01:55:23 AM UTC 24
Finished Aug 24 01:58:54 AM UTC 24
Peak memory 285596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149967224 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.4149967224
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.1296823364
Short name T321
Test name
Test status
Simulation time 40657867680 ps
CPU time 1795.44 seconds
Started Aug 23 11:40:54 PM UTC 24
Finished Aug 24 12:11:07 AM UTC 24
Peak memory 301960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296823364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1296823364
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.416441596
Short name T131
Test name
Test status
Simulation time 45305266300 ps
CPU time 351.69 seconds
Started Aug 23 11:30:54 PM UTC 24
Finished Aug 23 11:36:50 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416441596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.416441596
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.3033211516
Short name T13
Test name
Test status
Simulation time 1940218117 ps
CPU time 38.18 seconds
Started Aug 23 11:30:12 PM UTC 24
Finished Aug 23 11:30:52 PM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033211516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3033211516
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.2344746806
Short name T176
Test name
Test status
Simulation time 8015051 ps
CPU time 1.14 seconds
Started Aug 24 01:42:38 AM UTC 24
Finished Aug 24 01:42:40 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344746806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2344746806
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3474959927
Short name T195
Test name
Test status
Simulation time 1705982200 ps
CPU time 95.99 seconds
Started Aug 24 01:42:49 AM UTC 24
Finished Aug 24 01:44:27 AM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474959927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3474959927
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2278712763
Short name T171
Test name
Test status
Simulation time 134074495335 ps
CPU time 639.43 seconds
Started Aug 24 01:57:49 AM UTC 24
Finished Aug 24 02:08:35 AM UTC 24
Peak memory 279596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278712763 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shad
ow_reg_errors_with_csr_rw.2278712763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.4196490503
Short name T72
Test name
Test status
Simulation time 70851264675 ps
CPU time 310 seconds
Started Aug 23 11:45:55 PM UTC 24
Finished Aug 23 11:51:08 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196490503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.4196490503
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all_with_rand_reset.4104511427
Short name T48
Test name
Test status
Simulation time 8556795693 ps
CPU time 374.63 seconds
Started Aug 23 11:31:08 PM UTC 24
Finished Aug 23 11:37:27 PM UTC 24
Peak memory 285620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4104511427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.al
ert_handler_stress_all_with_rand_reset.4104511427
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1110096867
Short name T151
Test name
Test status
Simulation time 3179245516 ps
CPU time 147.94 seconds
Started Aug 24 01:54:42 AM UTC 24
Finished Aug 24 01:57:13 AM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110096867 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.1110096867
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.2054143233
Short name T90
Test name
Test status
Simulation time 628871399 ps
CPU time 30.79 seconds
Started Aug 24 12:04:51 AM UTC 24
Finished Aug 24 12:05:23 AM UTC 24
Peak memory 269080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054143233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2054143233
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.2055661396
Short name T318
Test name
Test status
Simulation time 175104572825 ps
CPU time 1461.11 seconds
Started Aug 23 11:34:31 PM UTC 24
Finished Aug 23 11:59:06 PM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055661396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2055661396
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3936853023
Short name T169
Test name
Test status
Simulation time 50581895140 ps
CPU time 763.72 seconds
Started Aug 24 01:52:55 AM UTC 24
Finished Aug 24 02:05:47 AM UTC 24
Peak memory 282240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936853023 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shado
w_reg_errors_with_csr_rw.3936853023
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.2580053010
Short name T62
Test name
Test status
Simulation time 38662297926 ps
CPU time 1707.97 seconds
Started Aug 24 12:13:16 AM UTC 24
Finished Aug 24 12:42:01 AM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580053010 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.2580053010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.3959380249
Short name T333
Test name
Test status
Simulation time 38281718097 ps
CPU time 296.5 seconds
Started Aug 24 12:28:05 AM UTC 24
Finished Aug 24 12:33:05 AM UTC 24
Peak memory 269188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959380249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3959380249
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.238645201
Short name T370
Test name
Test status
Simulation time 10545291008 ps
CPU time 716.12 seconds
Started Aug 24 12:41:18 AM UTC 24
Finished Aug 24 12:53:23 AM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238645201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.238645201
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/29.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3499015187
Short name T160
Test name
Test status
Simulation time 4846932747 ps
CPU time 245.19 seconds
Started Aug 24 01:55:01 AM UTC 24
Finished Aug 24 01:59:09 AM UTC 24
Peak memory 285596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499015187 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.3499015187
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.2018444702
Short name T267
Test name
Test status
Simulation time 135447551540 ps
CPU time 2639.49 seconds
Started Aug 24 12:06:44 AM UTC 24
Finished Aug 24 12:51:08 AM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018444702 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.2018444702
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.127955499
Short name T621
Test name
Test status
Simulation time 40891278510 ps
CPU time 1657.27 seconds
Started Aug 24 12:55:43 AM UTC 24
Finished Aug 24 01:23:37 AM UTC 24
Peak memory 288296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127955499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.127955499
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/34.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.4150440224
Short name T382
Test name
Test status
Simulation time 18730279 ps
CPU time 1.15 seconds
Started Aug 24 01:53:49 AM UTC 24
Finished Aug 24 01:53:51 AM UTC 24
Peak memory 248780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150440224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4150440224
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.2259503693
Short name T338
Test name
Test status
Simulation time 18636860762 ps
CPU time 437.93 seconds
Started Aug 24 12:21:00 AM UTC 24
Finished Aug 24 12:28:23 AM UTC 24
Peak memory 263056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259503693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2259503693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.2639105087
Short name T52
Test name
Test status
Simulation time 105570733638 ps
CPU time 1363.45 seconds
Started Aug 23 11:31:27 PM UTC 24
Finished Aug 23 11:54:24 PM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639105087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2639105087
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3991607666
Short name T156
Test name
Test status
Simulation time 2372956876 ps
CPU time 255.04 seconds
Started Aug 24 01:54:38 AM UTC 24
Finished Aug 24 01:58:57 AM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991607666 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shad
ow_reg_errors_with_csr_rw.3991607666
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.1668542434
Short name T332
Test name
Test status
Simulation time 68606737600 ps
CPU time 516.38 seconds
Started Aug 23 11:54:32 PM UTC 24
Finished Aug 24 12:03:13 AM UTC 24
Peak memory 263376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668542434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1668542434
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.4030105024
Short name T37
Test name
Test status
Simulation time 1469734553 ps
CPU time 30.26 seconds
Started Aug 23 11:39:31 PM UTC 24
Finished Aug 23 11:40:03 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030105024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.4030105024
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.3085863507
Short name T65
Test name
Test status
Simulation time 1271897863 ps
CPU time 12.6 seconds
Started Aug 23 11:31:55 PM UTC 24
Finished Aug 23 11:32:09 PM UTC 24
Peak memory 263236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085863507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3085863507
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all_with_rand_reset.2327675456
Short name T59
Test name
Test status
Simulation time 40014095559 ps
CPU time 226.13 seconds
Started Aug 24 12:26:01 AM UTC 24
Finished Aug 24 12:29:51 AM UTC 24
Peak memory 283648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2327675456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.a
lert_handler_stress_all_with_rand_reset.2327675456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.631544288
Short name T353
Test name
Test status
Simulation time 40851067730 ps
CPU time 1933.38 seconds
Started Aug 24 12:38:56 AM UTC 24
Finished Aug 24 01:11:28 AM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631544288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.631544288
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/28.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1047538101
Short name T170
Test name
Test status
Simulation time 54127851465 ps
CPU time 849.72 seconds
Started Aug 24 01:56:19 AM UTC 24
Finished Aug 24 02:10:38 AM UTC 24
Peak memory 288244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047538101 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shad
ow_reg_errors_with_csr_rw.1047538101
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3979733370
Short name T180
Test name
Test status
Simulation time 1505570935 ps
CPU time 51.02 seconds
Started Aug 24 01:53:24 AM UTC 24
Finished Aug 24 01:54:16 AM UTC 24
Peak memory 252516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979733370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3979733370
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3155285482
Short name T244
Test name
Test status
Simulation time 132757076 ps
CPU time 7.34 seconds
Started Aug 24 01:49:00 AM UTC 24
Finished Aug 24 01:49:09 AM UTC 24
Peak memory 252640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155285482 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_
rw_with_rand_reset.3155285482
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all_with_rand_reset.3698612812
Short name T119
Test name
Test status
Simulation time 1749267320 ps
CPU time 152.23 seconds
Started Aug 23 11:55:52 PM UTC 24
Finished Aug 23 11:58:27 PM UTC 24
Peak memory 279676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3698612812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.a
lert_handler_stress_all_with_rand_reset.3698612812
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.2599616623
Short name T287
Test name
Test status
Simulation time 3044683370 ps
CPU time 40.03 seconds
Started Aug 24 12:11:04 AM UTC 24
Finished Aug 24 12:11:45 AM UTC 24
Peak memory 269216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599616623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2599616623
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all_with_rand_reset.1370821610
Short name T123
Test name
Test status
Simulation time 12500289019 ps
CPU time 283.44 seconds
Started Aug 24 12:14:09 AM UTC 24
Finished Aug 24 12:18:56 AM UTC 24
Peak memory 279472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1370821610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.a
lert_handler_stress_all_with_rand_reset.1370821610
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.10934078
Short name T363
Test name
Test status
Simulation time 190370014456 ps
CPU time 1640.72 seconds
Started Aug 24 01:26:59 AM UTC 24
Finished Aug 24 01:54:36 AM UTC 24
Peak memory 304672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10934078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.10934078
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/44.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.3956558658
Short name T114
Test name
Test status
Simulation time 45534060963 ps
CPU time 2226.72 seconds
Started Aug 23 11:37:34 PM UTC 24
Finished Aug 24 12:15:02 AM UTC 24
Peak memory 321056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956558658 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.3956558658
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.3885533395
Short name T266
Test name
Test status
Simulation time 309916380671 ps
CPU time 1407.82 seconds
Started Aug 24 12:25:54 AM UTC 24
Finished Aug 24 12:49:36 AM UTC 24
Peak memory 320992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885533395 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.3885533395
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/23.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1253975630
Short name T154
Test name
Test status
Simulation time 76771566492 ps
CPU time 395.01 seconds
Started Aug 24 01:48:14 AM UTC 24
Finished Aug 24 01:54:54 AM UTC 24
Peak memory 279528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253975630 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shado
w_reg_errors_with_csr_rw.1253975630
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.1467283326
Short name T9
Test name
Test status
Simulation time 525627190 ps
CPU time 18.89 seconds
Started Aug 23 11:31:12 PM UTC 24
Finished Aug 23 11:31:32 PM UTC 24
Peak memory 297472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467283326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1467283326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.3404830468
Short name T12
Test name
Test status
Simulation time 160122001 ps
CPU time 2.75 seconds
Started Aug 23 11:30:41 PM UTC 24
Finished Aug 23 11:30:45 PM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404830468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3404830468
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.1693960868
Short name T28
Test name
Test status
Simulation time 49819063 ps
CPU time 3 seconds
Started Aug 23 11:31:07 PM UTC 24
Finished Aug 23 11:31:11 PM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693960868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1693960868
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.1901995959
Short name T15
Test name
Test status
Simulation time 83267681 ps
CPU time 2.73 seconds
Started Aug 23 11:30:24 PM UTC 24
Finished Aug 23 11:30:28 PM UTC 24
Peak memory 263568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901995959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1901995959
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.1243484714
Short name T227
Test name
Test status
Simulation time 57308067 ps
CPU time 2.03 seconds
Started Aug 23 11:52:49 PM UTC 24
Finished Aug 23 11:52:52 PM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243484714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1243484714
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.1318145290
Short name T381
Test name
Test status
Simulation time 8793257 ps
CPU time 1.24 seconds
Started Aug 24 01:56:41 AM UTC 24
Finished Aug 24 01:56:43 AM UTC 24
Peak memory 248716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318145290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1318145290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.407576543
Short name T358
Test name
Test status
Simulation time 64365719497 ps
CPU time 1104.75 seconds
Started Aug 23 11:51:35 PM UTC 24
Finished Aug 24 12:10:11 AM UTC 24
Peak memory 302148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407576543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.407576543
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.3986614074
Short name T124
Test name
Test status
Simulation time 309772190 ps
CPU time 30.33 seconds
Started Aug 23 11:51:23 PM UTC 24
Finished Aug 23 11:51:55 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986614074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3986614074
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.3825896883
Short name T289
Test name
Test status
Simulation time 35694556641 ps
CPU time 1222.41 seconds
Started Aug 24 12:03:35 AM UTC 24
Finished Aug 24 12:24:10 AM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825896883 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.3825896883
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.2855176146
Short name T339
Test name
Test status
Simulation time 37514768643 ps
CPU time 315.31 seconds
Started Aug 24 12:11:09 AM UTC 24
Finished Aug 24 12:16:28 AM UTC 24
Peak memory 263056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855176146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2855176146
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.1513879203
Short name T129
Test name
Test status
Simulation time 2929229863 ps
CPU time 38.05 seconds
Started Aug 24 12:20:38 AM UTC 24
Finished Aug 24 12:21:18 AM UTC 24
Peak memory 262964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513879203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1513879203
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all_with_rand_reset.2465738316
Short name T116
Test name
Test status
Simulation time 2619798300 ps
CPU time 150.87 seconds
Started Aug 24 12:23:20 AM UTC 24
Finished Aug 24 12:25:54 AM UTC 24
Peak memory 279476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2465738316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.a
lert_handler_stress_all_with_rand_reset.2465738316
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.3749854818
Short name T314
Test name
Test status
Simulation time 48275894535 ps
CPU time 382.84 seconds
Started Aug 24 12:25:00 AM UTC 24
Finished Aug 24 12:31:27 AM UTC 24
Peak memory 263056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749854818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3749854818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.1901834660
Short name T268
Test name
Test status
Simulation time 2054464217 ps
CPU time 22.82 seconds
Started Aug 24 12:33:43 AM UTC 24
Finished Aug 24 12:34:07 AM UTC 24
Peak memory 269080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901834660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1901834660
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.1357586952
Short name T269
Test name
Test status
Simulation time 4427309983 ps
CPU time 47.05 seconds
Started Aug 24 12:41:13 AM UTC 24
Finished Aug 24 12:42:01 AM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357586952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1357586952
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.754959241
Short name T265
Test name
Test status
Simulation time 214700246 ps
CPU time 21.7 seconds
Started Aug 24 01:06:17 AM UTC 24
Finished Aug 24 01:06:40 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754959241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.754959241
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.478135223
Short name T175
Test name
Test status
Simulation time 204294254 ps
CPU time 3.1 seconds
Started Aug 24 01:47:02 AM UTC 24
Finished Aug 24 01:47:06 AM UTC 24
Peak memory 250392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478135223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.478135223
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3744681387
Short name T162
Test name
Test status
Simulation time 41264317318 ps
CPU time 257.38 seconds
Started Aug 24 01:55:37 AM UTC 24
Finished Aug 24 01:59:57 AM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744681387 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.3744681387
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.2903647018
Short name T44
Test name
Test status
Simulation time 2888480634 ps
CPU time 43.39 seconds
Started Aug 23 11:30:50 PM UTC 24
Finished Aug 23 11:31:35 PM UTC 24
Peak memory 269140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903647018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2903647018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.923555125
Short name T240
Test name
Test status
Simulation time 26348530769 ps
CPU time 617.52 seconds
Started Aug 23 11:30:37 PM UTC 24
Finished Aug 23 11:41:02 PM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923555125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.923555125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1362065371
Short name T153
Test name
Test status
Simulation time 14702262964 ps
CPU time 287.44 seconds
Started Aug 24 01:57:13 AM UTC 24
Finished Aug 24 02:02:05 AM UTC 24
Peak memory 285596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362065371 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.1362065371
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.4246930447
Short name T384
Test name
Test status
Simulation time 6110172408 ps
CPU time 385.61 seconds
Started Aug 24 01:54:59 AM UTC 24
Finished Aug 24 02:01:29 AM UTC 24
Peak memory 279528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246930447 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shad
ow_reg_errors_with_csr_rw.4246930447
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.2543382076
Short name T257
Test name
Test status
Simulation time 91894937397 ps
CPU time 1087.66 seconds
Started Aug 23 11:51:34 PM UTC 24
Finished Aug 24 12:09:53 AM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543382076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2543382076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.4110912866
Short name T89
Test name
Test status
Simulation time 471567765 ps
CPU time 21.02 seconds
Started Aug 23 11:57:42 PM UTC 24
Finished Aug 23 11:58:04 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110912866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.4110912866
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.315646001
Short name T286
Test name
Test status
Simulation time 2484032008 ps
CPU time 27.3 seconds
Started Aug 24 12:12:16 AM UTC 24
Finished Aug 24 12:12:45 AM UTC 24
Peak memory 269432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315646001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.315646001
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.1365907518
Short name T288
Test name
Test status
Simulation time 12140884720 ps
CPU time 784.73 seconds
Started Aug 24 12:19:00 AM UTC 24
Finished Aug 24 12:32:13 AM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365907518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1365907518
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/21.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.192313531
Short name T359
Test name
Test status
Simulation time 58256665297 ps
CPU time 1313.61 seconds
Started Aug 24 12:25:07 AM UTC 24
Finished Aug 24 12:47:13 AM UTC 24
Peak memory 299584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192313531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.192313531
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/23.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.212700176
Short name T311
Test name
Test status
Simulation time 837191479 ps
CPU time 20.79 seconds
Started Aug 24 12:31:51 AM UTC 24
Finished Aug 24 12:32:13 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212700176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.212700176
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.1492502865
Short name T263
Test name
Test status
Simulation time 339180498 ps
CPU time 16.66 seconds
Started Aug 24 12:38:37 AM UTC 24
Finished Aug 24 12:38:55 AM UTC 24
Peak memory 269472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492502865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1492502865
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.960653669
Short name T307
Test name
Test status
Simulation time 33061855420 ps
CPU time 1280.47 seconds
Started Aug 24 12:47:15 AM UTC 24
Finished Aug 24 01:08:48 AM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960653669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.960653669
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.4122145936
Short name T375
Test name
Test status
Simulation time 10675394407 ps
CPU time 482.27 seconds
Started Aug 24 12:49:38 AM UTC 24
Finished Aug 24 12:57:46 AM UTC 24
Peak memory 279432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122145936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4122145936
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/32.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.276154479
Short name T271
Test name
Test status
Simulation time 1393744816 ps
CPU time 40.09 seconds
Started Aug 24 12:49:04 AM UTC 24
Finished Aug 24 12:49:45 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276154479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.276154479
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.1185549927
Short name T276
Test name
Test status
Simulation time 3169696160 ps
CPU time 40.06 seconds
Started Aug 24 01:03:38 AM UTC 24
Finished Aug 24 01:04:20 AM UTC 24
Peak memory 263296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185549927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1185549927
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.3994620892
Short name T274
Test name
Test status
Simulation time 1375345061 ps
CPU time 28.78 seconds
Started Aug 24 01:12:17 AM UTC 24
Finished Aug 24 01:12:47 AM UTC 24
Peak memory 269472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994620892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3994620892
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.2140358935
Short name T272
Test name
Test status
Simulation time 215145207 ps
CPU time 10.47 seconds
Started Aug 24 01:14:47 AM UTC 24
Finished Aug 24 01:14:59 AM UTC 24
Peak memory 269472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140358935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2140358935
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.1072184053
Short name T347
Test name
Test status
Simulation time 6353285927 ps
CPU time 183.89 seconds
Started Aug 24 01:24:39 AM UTC 24
Finished Aug 24 01:27:46 AM UTC 24
Peak memory 263312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072184053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1072184053
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.3615673869
Short name T273
Test name
Test status
Simulation time 1518236635 ps
CPU time 46.18 seconds
Started Aug 24 01:31:34 AM UTC 24
Finished Aug 24 01:32:22 AM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615673869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3615673869
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.1778893444
Short name T117
Test name
Test status
Simulation time 1505865984 ps
CPU time 37.03 seconds
Started Aug 24 12:33:39 AM UTC 24
Finished Aug 24 12:34:17 AM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778893444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1778893444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/26.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2014906577
Short name T134
Test name
Test status
Simulation time 7606831117 ps
CPU time 114.4 seconds
Started Aug 24 01:42:25 AM UTC 24
Finished Aug 24 01:44:22 AM UTC 24
Peak memory 281640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014906577 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.2014906577
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2369713015
Short name T183
Test name
Test status
Simulation time 118231411 ps
CPU time 2.41 seconds
Started Aug 24 01:57:52 AM UTC 24
Finished Aug 24 01:57:56 AM UTC 24
Peak memory 250388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369713015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2369713015
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.270791925
Short name T181
Test name
Test status
Simulation time 2935062672 ps
CPU time 16.93 seconds
Started Aug 24 01:49:27 AM UTC 24
Finished Aug 24 01:49:45 AM UTC 24
Peak memory 252768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270791925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.270791925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1942301975
Short name T164
Test name
Test status
Simulation time 18342922891 ps
CPU time 219.63 seconds
Started Aug 24 01:54:05 AM UTC 24
Finished Aug 24 01:57:48 AM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942301975 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.1942301975
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.41382104
Short name T186
Test name
Test status
Simulation time 7390207228 ps
CPU time 64.13 seconds
Started Aug 24 01:54:17 AM UTC 24
Finished Aug 24 01:55:22 AM UTC 24
Peak memory 252568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41382104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.41382104
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1329825092
Short name T185
Test name
Test status
Simulation time 23146616 ps
CPU time 1.89 seconds
Started Aug 24 01:55:09 AM UTC 24
Finished Aug 24 01:55:12 AM UTC 24
Peak memory 248840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329825092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1329825092
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2880501916
Short name T182
Test name
Test status
Simulation time 90359437 ps
CPU time 2.87 seconds
Started Aug 24 01:52:03 AM UTC 24
Finished Aug 24 01:52:07 AM UTC 24
Peak memory 250392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880501916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2880501916
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3404556515
Short name T189
Test name
Test status
Simulation time 106674454 ps
CPU time 4.39 seconds
Started Aug 24 01:52:49 AM UTC 24
Finished Aug 24 01:52:54 AM UTC 24
Peak memory 250532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404556515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3404556515
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.925770435
Short name T155
Test name
Test status
Simulation time 44036277524 ps
CPU time 137.78 seconds
Started Aug 24 01:53:04 AM UTC 24
Finished Aug 24 01:55:25 AM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925770435 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.925770435
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3657107912
Short name T173
Test name
Test status
Simulation time 63987871 ps
CPU time 2.32 seconds
Started Aug 24 01:42:33 AM UTC 24
Finished Aug 24 01:42:37 AM UTC 24
Peak memory 250532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657107912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3657107912
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3570149161
Short name T190
Test name
Test status
Simulation time 55757226 ps
CPU time 3.35 seconds
Started Aug 24 01:53:49 AM UTC 24
Finished Aug 24 01:53:53 AM UTC 24
Peak memory 250528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570149161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3570149161
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2851763988
Short name T191
Test name
Test status
Simulation time 55668869 ps
CPU time 1.81 seconds
Started Aug 24 01:54:54 AM UTC 24
Finished Aug 24 01:54:57 AM UTC 24
Peak memory 248840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851763988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2851763988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.951436678
Short name T192
Test name
Test status
Simulation time 2621042671 ps
CPU time 32.82 seconds
Started Aug 24 01:55:25 AM UTC 24
Finished Aug 24 01:56:00 AM UTC 24
Peak memory 252768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951436678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.951436678
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.356706265
Short name T179
Test name
Test status
Simulation time 1834638898 ps
CPU time 27.69 seconds
Started Aug 24 01:56:01 AM UTC 24
Finished Aug 24 01:56:30 AM UTC 24
Peak memory 252512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356706265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.356706265
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3739571026
Short name T196
Test name
Test status
Simulation time 1626997985 ps
CPU time 17.2 seconds
Started Aug 24 01:48:28 AM UTC 24
Finished Aug 24 01:48:46 AM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739571026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3739571026
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.166426160
Short name T187
Test name
Test status
Simulation time 87319775 ps
CPU time 1.8 seconds
Started Aug 24 01:51:19 AM UTC 24
Finished Aug 24 01:51:22 AM UTC 24
Peak memory 248840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166426160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.166426160
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.2377781607
Short name T16
Test name
Test status
Simulation time 234523561 ps
CPU time 12.2 seconds
Started Aug 23 11:30:34 PM UTC 24
Finished Aug 23 11:30:48 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377781607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2377781607
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1466760454
Short name T209
Test name
Test status
Simulation time 3452568481 ps
CPU time 185.9 seconds
Started Aug 24 01:42:51 AM UTC 24
Finished Aug 24 01:45:59 AM UTC 24
Peak memory 252576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466760454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1466760454
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.4110087422
Short name T177
Test name
Test status
Simulation time 852661715 ps
CPU time 7.36 seconds
Started Aug 24 01:42:40 AM UTC 24
Finished Aug 24 01:42:48 AM UTC 24
Peak memory 252376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110087422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.4110087422
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.469593785
Short name T216
Test name
Test status
Simulation time 35593638 ps
CPU time 4.43 seconds
Started Aug 24 01:44:22 AM UTC 24
Finished Aug 24 01:44:28 AM UTC 24
Peak memory 262816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469593785 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_r
w_with_rand_reset.469593785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1274924120
Short name T194
Test name
Test status
Simulation time 316948969 ps
CPU time 11.84 seconds
Started Aug 24 01:44:12 AM UTC 24
Finished Aug 24 01:44:25 AM UTC 24
Peak memory 260704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274924120 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.1274924120
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2702564615
Short name T135
Test name
Test status
Simulation time 6342142639 ps
CPU time 373.67 seconds
Started Aug 24 01:42:03 AM UTC 24
Finished Aug 24 01:48:21 AM UTC 24
Peak memory 279460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702564615 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shado
w_reg_errors_with_csr_rw.2702564615
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.3616831323
Short name T720
Test name
Test status
Simulation time 52646288 ps
CPU time 6.26 seconds
Started Aug 24 01:42:25 AM UTC 24
Finished Aug 24 01:42:33 AM UTC 24
Peak memory 268960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616831323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3616831323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3252301785
Short name T210
Test name
Test status
Simulation time 3695661714 ps
CPU time 192.53 seconds
Started Aug 24 01:45:12 AM UTC 24
Finished Aug 24 01:48:27 AM UTC 24
Peak memory 252584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252301785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3252301785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.350973380
Short name T207
Test name
Test status
Simulation time 16874460418 ps
CPU time 171.29 seconds
Started Aug 24 01:45:11 AM UTC 24
Finished Aug 24 01:48:05 AM UTC 24
Peak memory 252504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350973380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.350973380
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2758901043
Short name T203
Test name
Test status
Simulation time 379388670 ps
CPU time 7.17 seconds
Started Aug 24 01:44:57 AM UTC 24
Finished Aug 24 01:45:05 AM UTC 24
Peak memory 262616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758901043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2758901043
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4055943463
Short name T247
Test name
Test status
Simulation time 184747562 ps
CPU time 5.93 seconds
Started Aug 24 01:45:54 AM UTC 24
Finished Aug 24 01:46:01 AM UTC 24
Peak memory 252576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055943463 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_
rw_with_rand_reset.4055943463
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.2049097889
Short name T213
Test name
Test status
Simulation time 403579482 ps
CPU time 3.84 seconds
Started Aug 24 01:45:06 AM UTC 24
Finished Aug 24 01:45:11 AM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049097889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2049097889
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.1214262934
Short name T178
Test name
Test status
Simulation time 5997819 ps
CPU time 1.19 seconds
Started Aug 24 01:44:54 AM UTC 24
Finished Aug 24 01:44:56 AM UTC 24
Peak memory 248716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214262934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1214262934
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3188564214
Short name T204
Test name
Test status
Simulation time 336853053 ps
CPU time 18.77 seconds
Started Aug 24 01:45:33 AM UTC 24
Finished Aug 24 01:45:53 AM UTC 24
Peak memory 260768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188564214 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.3188564214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3448898127
Short name T136
Test name
Test status
Simulation time 5287551181 ps
CPU time 242.32 seconds
Started Aug 24 01:44:27 AM UTC 24
Finished Aug 24 01:48:33 AM UTC 24
Peak memory 279592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448898127 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.3448898127
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.500797639
Short name T139
Test name
Test status
Simulation time 8992621172 ps
CPU time 287.12 seconds
Started Aug 24 01:44:26 AM UTC 24
Finished Aug 24 01:49:17 AM UTC 24
Peak memory 283556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500797639 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow
_reg_errors_with_csr_rw.500797639
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.1545515087
Short name T721
Test name
Test status
Simulation time 479448619 ps
CPU time 7.94 seconds
Started Aug 24 01:44:28 AM UTC 24
Finished Aug 24 01:44:38 AM UTC 24
Peak memory 262816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545515087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1545515087
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2007240808
Short name T751
Test name
Test status
Simulation time 194213332 ps
CPU time 6.4 seconds
Started Aug 24 01:53:57 AM UTC 24
Finished Aug 24 01:54:05 AM UTC 24
Peak memory 252496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007240808 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem
_rw_with_rand_reset.2007240808
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.1504967929
Short name T749
Test name
Test status
Simulation time 51753153 ps
CPU time 3.66 seconds
Started Aug 24 01:53:52 AM UTC 24
Finished Aug 24 01:53:57 AM UTC 24
Peak memory 250400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504967929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1504967929
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1199738359
Short name T752
Test name
Test status
Simulation time 351329737 ps
CPU time 16.19 seconds
Started Aug 24 01:53:54 AM UTC 24
Finished Aug 24 01:54:11 AM UTC 24
Peak memory 260828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199738359 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.1199738359
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.320302546
Short name T141
Test name
Test status
Simulation time 1665051147 ps
CPU time 90.67 seconds
Started Aug 24 01:53:39 AM UTC 24
Finished Aug 24 01:55:11 AM UTC 24
Peak memory 269084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320302546 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.320302546
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.39810306
Short name T165
Test name
Test status
Simulation time 19361608456 ps
CPU time 364.98 seconds
Started Aug 24 01:53:39 AM UTC 24
Finished Aug 24 01:59:48 AM UTC 24
Peak memory 279600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39810306 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow
_reg_errors_with_csr_rw.39810306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.1759549843
Short name T748
Test name
Test status
Simulation time 437608937 ps
CPU time 6.82 seconds
Started Aug 24 01:53:40 AM UTC 24
Finished Aug 24 01:53:48 AM UTC 24
Peak memory 262888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759549843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1759549843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3205972274
Short name T757
Test name
Test status
Simulation time 67724687 ps
CPU time 4.87 seconds
Started Aug 24 01:54:36 AM UTC 24
Finished Aug 24 01:54:42 AM UTC 24
Peak memory 256592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205972274 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem
_rw_with_rand_reset.3205972274
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.127486600
Short name T755
Test name
Test status
Simulation time 35353633 ps
CPU time 3.82 seconds
Started Aug 24 01:54:30 AM UTC 24
Finished Aug 24 01:54:35 AM UTC 24
Peak memory 250528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127486600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.127486600
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.1779594102
Short name T754
Test name
Test status
Simulation time 14478506 ps
CPU time 1.37 seconds
Started Aug 24 01:54:27 AM UTC 24
Finished Aug 24 01:54:29 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779594102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1779594102
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.560294169
Short name T756
Test name
Test status
Simulation time 176588601 ps
CPU time 10.14 seconds
Started Aug 24 01:54:30 AM UTC 24
Finished Aug 24 01:54:41 AM UTC 24
Peak memory 262676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560294169 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.560294169
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1656705430
Short name T150
Test name
Test status
Simulation time 4596423519 ps
CPU time 258.35 seconds
Started Aug 24 01:54:03 AM UTC 24
Finished Aug 24 01:58:25 AM UTC 24
Peak memory 279464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656705430 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shad
ow_reg_errors_with_csr_rw.1656705430
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.1489695762
Short name T753
Test name
Test status
Simulation time 1069776797 ps
CPU time 15.21 seconds
Started Aug 24 01:54:13 AM UTC 24
Finished Aug 24 01:54:29 AM UTC 24
Peak memory 269032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489695762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1489695762
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2233111044
Short name T761
Test name
Test status
Simulation time 473352584 ps
CPU time 8.24 seconds
Started Aug 24 01:54:58 AM UTC 24
Finished Aug 24 01:55:07 AM UTC 24
Peak memory 252496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233111044 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem
_rw_with_rand_reset.2233111044
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.1006245187
Short name T760
Test name
Test status
Simulation time 25469711 ps
CPU time 2.97 seconds
Started Aug 24 01:54:55 AM UTC 24
Finished Aug 24 01:55:00 AM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006245187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1006245187
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.1705414906
Short name T759
Test name
Test status
Simulation time 7516663 ps
CPU time 1.08 seconds
Started Aug 24 01:54:55 AM UTC 24
Finished Aug 24 01:54:58 AM UTC 24
Peak memory 246732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705414906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1705414906
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1517811263
Short name T767
Test name
Test status
Simulation time 2699156891 ps
CPU time 34.88 seconds
Started Aug 24 01:54:55 AM UTC 24
Finished Aug 24 01:55:32 AM UTC 24
Peak memory 262736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517811263 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.1517811263
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.1312412337
Short name T758
Test name
Test status
Simulation time 887952773 ps
CPU time 9.94 seconds
Started Aug 24 01:54:43 AM UTC 24
Finished Aug 24 01:54:55 AM UTC 24
Peak memory 266848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312412337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1312412337
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3416728780
Short name T765
Test name
Test status
Simulation time 345261244 ps
CPU time 5.46 seconds
Started Aug 24 01:55:17 AM UTC 24
Finished Aug 24 01:55:23 AM UTC 24
Peak memory 252500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416728780 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem
_rw_with_rand_reset.3416728780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.2999959274
Short name T763
Test name
Test status
Simulation time 66717917 ps
CPU time 2.53 seconds
Started Aug 24 01:55:13 AM UTC 24
Finished Aug 24 01:55:16 AM UTC 24
Peak memory 252512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999959274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2999959274
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.67427824
Short name T762
Test name
Test status
Simulation time 38026575 ps
CPU time 1.2 seconds
Started Aug 24 01:55:12 AM UTC 24
Finished Aug 24 01:55:14 AM UTC 24
Peak memory 248848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67427824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.67427824
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3791623304
Short name T766
Test name
Test status
Simulation time 459215231 ps
CPU time 14.49 seconds
Started Aug 24 01:55:15 AM UTC 24
Finished Aug 24 01:55:30 AM UTC 24
Peak memory 260700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791623304 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.3791623304
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.1539054826
Short name T764
Test name
Test status
Simulation time 345320400 ps
CPU time 10.79 seconds
Started Aug 24 01:55:08 AM UTC 24
Finished Aug 24 01:55:20 AM UTC 24
Peak memory 262888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539054826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1539054826
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.685810107
Short name T771
Test name
Test status
Simulation time 1397705805 ps
CPU time 7.5 seconds
Started Aug 24 01:55:37 AM UTC 24
Finished Aug 24 01:55:45 AM UTC 24
Peak memory 252516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685810107 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem_
rw_with_rand_reset.685810107
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.1215926486
Short name T769
Test name
Test status
Simulation time 35390188 ps
CPU time 2.79 seconds
Started Aug 24 01:55:32 AM UTC 24
Finished Aug 24 01:55:36 AM UTC 24
Peak memory 250464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215926486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1215926486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.4166924095
Short name T768
Test name
Test status
Simulation time 11490733 ps
CPU time 1.29 seconds
Started Aug 24 01:55:31 AM UTC 24
Finished Aug 24 01:55:34 AM UTC 24
Peak memory 246732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166924095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4166924095
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1098359679
Short name T772
Test name
Test status
Simulation time 1087954203 ps
CPU time 9.73 seconds
Started Aug 24 01:55:35 AM UTC 24
Finished Aug 24 01:55:45 AM UTC 24
Peak memory 262676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098359679 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.1098359679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.2295530416
Short name T770
Test name
Test status
Simulation time 213809926 ps
CPU time 13.17 seconds
Started Aug 24 01:55:24 AM UTC 24
Finished Aug 24 01:55:38 AM UTC 24
Peak memory 269032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295530416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2295530416
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2878019121
Short name T777
Test name
Test status
Simulation time 841690865 ps
CPU time 3.94 seconds
Started Aug 24 01:55:49 AM UTC 24
Finished Aug 24 01:55:54 AM UTC 24
Peak memory 252500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878019121 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem
_rw_with_rand_reset.2878019121
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.3863149285
Short name T776
Test name
Test status
Simulation time 65899744 ps
CPU time 4.39 seconds
Started Aug 24 01:55:47 AM UTC 24
Finished Aug 24 01:55:53 AM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863149285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3863149285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.3117633519
Short name T773
Test name
Test status
Simulation time 10475505 ps
CPU time 1.35 seconds
Started Aug 24 01:55:46 AM UTC 24
Finished Aug 24 01:55:48 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117633519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3117633519
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.765841748
Short name T778
Test name
Test status
Simulation time 163964556 ps
CPU time 9.71 seconds
Started Aug 24 01:55:49 AM UTC 24
Finished Aug 24 01:56:00 AM UTC 24
Peak memory 262748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765841748 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.765841748
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3115297251
Short name T168
Test name
Test status
Simulation time 48745814254 ps
CPU time 681.27 seconds
Started Aug 24 01:55:37 AM UTC 24
Finished Aug 24 02:07:05 AM UTC 24
Peak memory 281960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115297251 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shad
ow_reg_errors_with_csr_rw.3115297251
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.1898118052
Short name T774
Test name
Test status
Simulation time 167109552 ps
CPU time 8.53 seconds
Started Aug 24 01:55:39 AM UTC 24
Finished Aug 24 01:55:48 AM UTC 24
Peak memory 262756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898118052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1898118052
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1138995457
Short name T775
Test name
Test status
Simulation time 59984901 ps
CPU time 1.81 seconds
Started Aug 24 01:55:46 AM UTC 24
Finished Aug 24 01:55:49 AM UTC 24
Peak memory 248840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138995457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1138995457
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.137408727
Short name T782
Test name
Test status
Simulation time 263122579 ps
CPU time 4.46 seconds
Started Aug 24 01:56:13 AM UTC 24
Finished Aug 24 01:56:19 AM UTC 24
Peak memory 252504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137408727 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem_
rw_with_rand_reset.137408727
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.74183034
Short name T781
Test name
Test status
Simulation time 242262148 ps
CPU time 7.33 seconds
Started Aug 24 01:56:04 AM UTC 24
Finished Aug 24 01:56:12 AM UTC 24
Peak memory 252448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74183034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_han
dler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.74183034
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.1015773163
Short name T779
Test name
Test status
Simulation time 20252569 ps
CPU time 1.2 seconds
Started Aug 24 01:56:01 AM UTC 24
Finished Aug 24 01:56:03 AM UTC 24
Peak memory 248780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015773163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1015773163
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.4074239725
Short name T783
Test name
Test status
Simulation time 270620096 ps
CPU time 13.62 seconds
Started Aug 24 01:56:05 AM UTC 24
Finished Aug 24 01:56:20 AM UTC 24
Peak memory 260624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074239725 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.4074239725
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1898045196
Short name T157
Test name
Test status
Simulation time 15178720322 ps
CPU time 218.92 seconds
Started Aug 24 01:55:53 AM UTC 24
Finished Aug 24 01:59:35 AM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898045196 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.1898045196
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1244198072
Short name T167
Test name
Test status
Simulation time 8661727358 ps
CPU time 423.3 seconds
Started Aug 24 01:55:49 AM UTC 24
Finished Aug 24 02:02:58 AM UTC 24
Peak memory 283552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244198072 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shad
ow_reg_errors_with_csr_rw.1244198072
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.158455843
Short name T780
Test name
Test status
Simulation time 243706343 ps
CPU time 7.13 seconds
Started Aug 24 01:55:56 AM UTC 24
Finished Aug 24 01:56:04 AM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158455843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.158455843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.911309109
Short name T787
Test name
Test status
Simulation time 396899516 ps
CPU time 6.17 seconds
Started Aug 24 01:57:11 AM UTC 24
Finished Aug 24 01:57:19 AM UTC 24
Peak memory 250528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911309109 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem_
rw_with_rand_reset.911309109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.729832189
Short name T785
Test name
Test status
Simulation time 775628450 ps
CPU time 7.88 seconds
Started Aug 24 01:56:44 AM UTC 24
Finished Aug 24 01:56:53 AM UTC 24
Peak memory 252376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729832189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.729832189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1161483956
Short name T786
Test name
Test status
Simulation time 170604437 ps
CPU time 19.63 seconds
Started Aug 24 01:56:54 AM UTC 24
Finished Aug 24 01:57:15 AM UTC 24
Peak memory 260624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161483956 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.1161483956
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.695824007
Short name T166
Test name
Test status
Simulation time 4781155788 ps
CPU time 128.57 seconds
Started Aug 24 01:56:20 AM UTC 24
Finished Aug 24 01:58:31 AM UTC 24
Peak memory 281504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695824007 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.695824007
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.2975253055
Short name T784
Test name
Test status
Simulation time 144988957 ps
CPU time 8.81 seconds
Started Aug 24 01:56:30 AM UTC 24
Finished Aug 24 01:56:40 AM UTC 24
Peak memory 268896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975253055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2975253055
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1262353474
Short name T188
Test name
Test status
Simulation time 618112004 ps
CPU time 32.49 seconds
Started Aug 24 01:56:39 AM UTC 24
Finished Aug 24 01:57:13 AM UTC 24
Peak memory 252512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262353474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1262353474
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1982587884
Short name T791
Test name
Test status
Simulation time 60364133 ps
CPU time 7.23 seconds
Started Aug 24 01:57:40 AM UTC 24
Finished Aug 24 01:57:48 AM UTC 24
Peak memory 262940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982587884 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem
_rw_with_rand_reset.1982587884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.3322855341
Short name T790
Test name
Test status
Simulation time 185069328 ps
CPU time 2.66 seconds
Started Aug 24 01:57:26 AM UTC 24
Finished Aug 24 01:57:29 AM UTC 24
Peak memory 250464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322855341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3322855341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.207757831
Short name T789
Test name
Test status
Simulation time 7421088 ps
CPU time 1.2 seconds
Started Aug 24 01:57:23 AM UTC 24
Finished Aug 24 01:57:25 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207757831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.207757831
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2003964944
Short name T792
Test name
Test status
Simulation time 635838866 ps
CPU time 17.97 seconds
Started Aug 24 01:57:30 AM UTC 24
Finished Aug 24 01:57:50 AM UTC 24
Peak memory 260628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003964944 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.2003964944
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3162417980
Short name T172
Test name
Test status
Simulation time 24551015762 ps
CPU time 392.76 seconds
Started Aug 24 01:57:13 AM UTC 24
Finished Aug 24 02:03:51 AM UTC 24
Peak memory 279592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162417980 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shad
ow_reg_errors_with_csr_rw.3162417980
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.1163331894
Short name T788
Test name
Test status
Simulation time 175714601 ps
CPU time 5.73 seconds
Started Aug 24 01:57:15 AM UTC 24
Finished Aug 24 01:57:22 AM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163331894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1163331894
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.211514942
Short name T184
Test name
Test status
Simulation time 181506421 ps
CPU time 18.56 seconds
Started Aug 24 01:57:20 AM UTC 24
Finished Aug 24 01:57:39 AM UTC 24
Peak memory 252440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211514942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.211514942
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3653041346
Short name T796
Test name
Test status
Simulation time 254441470 ps
CPU time 7.52 seconds
Started Aug 24 01:58:09 AM UTC 24
Finished Aug 24 01:58:17 AM UTC 24
Peak memory 252500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653041346 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem
_rw_with_rand_reset.3653041346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.918978074
Short name T794
Test name
Test status
Simulation time 51173708 ps
CPU time 3.88 seconds
Started Aug 24 01:58:00 AM UTC 24
Finished Aug 24 01:58:05 AM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918978074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.918978074
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.1337422682
Short name T793
Test name
Test status
Simulation time 7953817 ps
CPU time 1.08 seconds
Started Aug 24 01:57:57 AM UTC 24
Finished Aug 24 01:57:59 AM UTC 24
Peak memory 248644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337422682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1337422682
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1744883133
Short name T801
Test name
Test status
Simulation time 631473932 ps
CPU time 16.28 seconds
Started Aug 24 01:58:06 AM UTC 24
Finished Aug 24 01:58:24 AM UTC 24
Peak memory 260700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744883133 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.1744883133
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.22965239
Short name T158
Test name
Test status
Simulation time 16406932552 ps
CPU time 229.12 seconds
Started Aug 24 01:57:49 AM UTC 24
Finished Aug 24 02:01:41 AM UTC 24
Peak memory 279592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22965239 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.22965239
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.51836753
Short name T795
Test name
Test status
Simulation time 480998504 ps
CPU time 15.47 seconds
Started Aug 24 01:57:51 AM UTC 24
Finished Aug 24 01:58:08 AM UTC 24
Peak memory 268896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51836753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.51836753
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.775193175
Short name T212
Test name
Test status
Simulation time 4083490110 ps
CPU time 94.46 seconds
Started Aug 24 01:47:26 AM UTC 24
Finished Aug 24 01:49:03 AM UTC 24
Peak memory 250456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775193175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.775193175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.859401171
Short name T739
Test name
Test status
Simulation time 33650079530 ps
CPU time 320.64 seconds
Started Aug 24 01:47:23 AM UTC 24
Finished Aug 24 01:52:48 AM UTC 24
Peak memory 250456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859401171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.859401171
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3517107395
Short name T205
Test name
Test status
Simulation time 65948580 ps
CPU time 3.27 seconds
Started Aug 24 01:47:10 AM UTC 24
Finished Aug 24 01:47:14 AM UTC 24
Peak memory 262616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517107395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3517107395
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.186461907
Short name T383
Test name
Test status
Simulation time 138766221 ps
CPU time 7.49 seconds
Started Aug 24 01:48:05 AM UTC 24
Finished Aug 24 01:48:14 AM UTC 24
Peak memory 268888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186461907 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_r
w_with_rand_reset.186461907
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.1120408208
Short name T206
Test name
Test status
Simulation time 95878843 ps
CPU time 6.69 seconds
Started Aug 24 01:47:15 AM UTC 24
Finished Aug 24 01:47:23 AM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120408208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1120408208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.2983260836
Short name T260
Test name
Test status
Simulation time 26022736 ps
CPU time 1.25 seconds
Started Aug 24 01:47:07 AM UTC 24
Finished Aug 24 01:47:09 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983260836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2983260836
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2935983064
Short name T208
Test name
Test status
Simulation time 799679025 ps
CPU time 17.12 seconds
Started Aug 24 01:47:59 AM UTC 24
Finished Aug 24 01:48:18 AM UTC 24
Peak memory 262816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935983064 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.2935983064
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3488049433
Short name T137
Test name
Test status
Simulation time 2040049382 ps
CPU time 114.17 seconds
Started Aug 24 01:46:02 AM UTC 24
Finished Aug 24 01:47:58 AM UTC 24
Peak memory 279464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488049433 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.3488049433
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2741872046
Short name T142
Test name
Test status
Simulation time 109090032634 ps
CPU time 879.39 seconds
Started Aug 24 01:46:00 AM UTC 24
Finished Aug 24 02:00:49 AM UTC 24
Peak memory 285672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741872046 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shado
w_reg_errors_with_csr_rw.2741872046
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.2156023361
Short name T722
Test name
Test status
Simulation time 668127012 ps
CPU time 18.68 seconds
Started Aug 24 01:46:41 AM UTC 24
Finished Aug 24 01:47:01 AM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156023361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2156023361
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.322995961
Short name T797
Test name
Test status
Simulation time 8976593 ps
CPU time 1.29 seconds
Started Aug 24 01:58:17 AM UTC 24
Finished Aug 24 01:58:19 AM UTC 24
Peak memory 248780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322995961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.322995961
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/20.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.848344854
Short name T798
Test name
Test status
Simulation time 16447766 ps
CPU time 1.18 seconds
Started Aug 24 01:58:18 AM UTC 24
Finished Aug 24 01:58:20 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848344854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.848344854
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/21.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.2046437837
Short name T799
Test name
Test status
Simulation time 12544706 ps
CPU time 1.12 seconds
Started Aug 24 01:58:20 AM UTC 24
Finished Aug 24 01:58:22 AM UTC 24
Peak memory 248716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046437837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2046437837
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/22.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.1051472910
Short name T800
Test name
Test status
Simulation time 7591542 ps
CPU time 1.14 seconds
Started Aug 24 01:58:21 AM UTC 24
Finished Aug 24 01:58:23 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051472910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1051472910
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/23.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.828202064
Short name T802
Test name
Test status
Simulation time 8065001 ps
CPU time 1.11 seconds
Started Aug 24 01:58:23 AM UTC 24
Finished Aug 24 01:58:25 AM UTC 24
Peak memory 246732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828202064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.828202064
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/24.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.3955069884
Short name T803
Test name
Test status
Simulation time 14423244 ps
CPU time 1.12 seconds
Started Aug 24 01:58:24 AM UTC 24
Finished Aug 24 01:58:26 AM UTC 24
Peak memory 248716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955069884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3955069884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/25.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.1619258599
Short name T804
Test name
Test status
Simulation time 24092725 ps
CPU time 1.1 seconds
Started Aug 24 01:58:24 AM UTC 24
Finished Aug 24 01:58:26 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619258599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1619258599
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/26.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.3866177351
Short name T805
Test name
Test status
Simulation time 18770076 ps
CPU time 1.06 seconds
Started Aug 24 01:58:27 AM UTC 24
Finished Aug 24 01:58:29 AM UTC 24
Peak memory 246732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866177351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3866177351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/27.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2179220326
Short name T806
Test name
Test status
Simulation time 15543471 ps
CPU time 1.12 seconds
Started Aug 24 01:58:27 AM UTC 24
Finished Aug 24 01:58:29 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179220326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2179220326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/28.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.3468926832
Short name T807
Test name
Test status
Simulation time 19100184 ps
CPU time 1.18 seconds
Started Aug 24 01:58:28 AM UTC 24
Finished Aug 24 01:58:30 AM UTC 24
Peak memory 248716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468926832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3468926832
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/29.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.4094562976
Short name T727
Test name
Test status
Simulation time 687534337 ps
CPU time 63.68 seconds
Started Aug 24 01:48:44 AM UTC 24
Finished Aug 24 01:49:50 AM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094562976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.4094562976
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4237388033
Short name T385
Test name
Test status
Simulation time 1706284360 ps
CPU time 86.84 seconds
Started Aug 24 01:48:41 AM UTC 24
Finished Aug 24 01:50:10 AM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237388033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.4237388033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3949753320
Short name T724
Test name
Test status
Simulation time 74967744 ps
CPU time 5.36 seconds
Started Aug 24 01:48:34 AM UTC 24
Finished Aug 24 01:48:41 AM UTC 24
Peak memory 262616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949753320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3949753320
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.1469288018
Short name T243
Test name
Test status
Simulation time 223598043 ps
CPU time 6.72 seconds
Started Aug 24 01:48:36 AM UTC 24
Finished Aug 24 01:48:44 AM UTC 24
Peak memory 252372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469288018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1469288018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.175322222
Short name T378
Test name
Test status
Simulation time 8032120 ps
CPU time 1.17 seconds
Started Aug 24 01:48:33 AM UTC 24
Finished Aug 24 01:48:35 AM UTC 24
Peak memory 248840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175322222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.175322222
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.564432900
Short name T211
Test name
Test status
Simulation time 107515382 ps
CPU time 11.08 seconds
Started Aug 24 01:48:47 AM UTC 24
Finished Aug 24 01:48:59 AM UTC 24
Peak memory 260628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564432900 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.564432900
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1765755774
Short name T147
Test name
Test status
Simulation time 17339033912 ps
CPU time 232.33 seconds
Started Aug 24 01:48:19 AM UTC 24
Finished Aug 24 01:52:14 AM UTC 24
Peak memory 279592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765755774 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.1765755774
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.3467475178
Short name T723
Test name
Test status
Simulation time 400203144 ps
CPU time 9.36 seconds
Started Aug 24 01:48:22 AM UTC 24
Finished Aug 24 01:48:32 AM UTC 24
Peak memory 268896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467475178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3467475178
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.750249860
Short name T808
Test name
Test status
Simulation time 53263317 ps
CPU time 1.82 seconds
Started Aug 24 01:58:28 AM UTC 24
Finished Aug 24 01:58:31 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750249860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.750249860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/30.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.707052204
Short name T809
Test name
Test status
Simulation time 17549360 ps
CPU time 1.1 seconds
Started Aug 24 01:58:30 AM UTC 24
Finished Aug 24 01:58:32 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707052204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.707052204
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/31.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.2300493280
Short name T810
Test name
Test status
Simulation time 8244110 ps
CPU time 1.2 seconds
Started Aug 24 01:58:30 AM UTC 24
Finished Aug 24 01:58:32 AM UTC 24
Peak memory 246732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300493280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2300493280
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/32.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.1087704923
Short name T811
Test name
Test status
Simulation time 15475952 ps
CPU time 1.08 seconds
Started Aug 24 01:58:31 AM UTC 24
Finished Aug 24 01:58:33 AM UTC 24
Peak memory 246732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087704923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1087704923
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/33.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.95767386
Short name T812
Test name
Test status
Simulation time 15823222 ps
CPU time 1.04 seconds
Started Aug 24 01:58:32 AM UTC 24
Finished Aug 24 01:58:34 AM UTC 24
Peak memory 248848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95767386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.95767386
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/34.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.2495108426
Short name T813
Test name
Test status
Simulation time 9510283 ps
CPU time 1.29 seconds
Started Aug 24 01:58:32 AM UTC 24
Finished Aug 24 01:58:35 AM UTC 24
Peak memory 248716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495108426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2495108426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/35.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.1079174749
Short name T814
Test name
Test status
Simulation time 57152687 ps
CPU time 1.08 seconds
Started Aug 24 01:58:33 AM UTC 24
Finished Aug 24 01:58:35 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079174749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1079174749
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/36.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.92976974
Short name T815
Test name
Test status
Simulation time 8158347 ps
CPU time 1.22 seconds
Started Aug 24 01:58:33 AM UTC 24
Finished Aug 24 01:58:36 AM UTC 24
Peak memory 248848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92976974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.92976974
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/37.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.1730536956
Short name T816
Test name
Test status
Simulation time 7359242 ps
CPU time 1.06 seconds
Started Aug 24 01:58:34 AM UTC 24
Finished Aug 24 01:58:37 AM UTC 24
Peak memory 248772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730536956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1730536956
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/38.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.1223819178
Short name T818
Test name
Test status
Simulation time 9633825 ps
CPU time 1.16 seconds
Started Aug 24 01:58:35 AM UTC 24
Finished Aug 24 01:58:38 AM UTC 24
Peak memory 248836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223819178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1223819178
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/39.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1454572677
Short name T258
Test name
Test status
Simulation time 2418134882 ps
CPU time 113.8 seconds
Started Aug 24 01:49:46 AM UTC 24
Finished Aug 24 01:51:42 AM UTC 24
Peak memory 250592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454572677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1454572677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3834341886
Short name T735
Test name
Test status
Simulation time 3334278158 ps
CPU time 145.37 seconds
Started Aug 24 01:49:41 AM UTC 24
Finished Aug 24 01:52:09 AM UTC 24
Peak memory 250456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834341886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3834341886
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3788431161
Short name T726
Test name
Test status
Simulation time 97105647 ps
CPU time 2.97 seconds
Started Aug 24 01:49:30 AM UTC 24
Finished Aug 24 01:49:34 AM UTC 24
Peak memory 252512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788431161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3788431161
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2785495234
Short name T387
Test name
Test status
Simulation time 93929371 ps
CPU time 5.99 seconds
Started Aug 24 01:49:55 AM UTC 24
Finished Aug 24 01:50:02 AM UTC 24
Peak memory 250456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785495234 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_
rw_with_rand_reset.2785495234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.856883042
Short name T386
Test name
Test status
Simulation time 62193021 ps
CPU time 4.42 seconds
Started Aug 24 01:49:35 AM UTC 24
Finished Aug 24 01:49:40 AM UTC 24
Peak memory 250396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856883042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.856883042
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.2832431988
Short name T261
Test name
Test status
Simulation time 17883321 ps
CPU time 1.09 seconds
Started Aug 24 01:49:27 AM UTC 24
Finished Aug 24 01:49:29 AM UTC 24
Peak memory 246732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832431988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2832431988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.409973173
Short name T728
Test name
Test status
Simulation time 2487728490 ps
CPU time 30.36 seconds
Started Aug 24 01:49:50 AM UTC 24
Finished Aug 24 01:50:22 AM UTC 24
Peak memory 260892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409973173 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.409973173
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.725071520
Short name T140
Test name
Test status
Simulation time 4286575599 ps
CPU time 245.84 seconds
Started Aug 24 01:49:03 AM UTC 24
Finished Aug 24 01:53:13 AM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725071520 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow
_reg_errors_with_csr_rw.725071520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.1765847917
Short name T725
Test name
Test status
Simulation time 196642394 ps
CPU time 5.81 seconds
Started Aug 24 01:49:18 AM UTC 24
Finished Aug 24 01:49:25 AM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765847917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1765847917
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.152258239
Short name T817
Test name
Test status
Simulation time 11859641 ps
CPU time 1.09 seconds
Started Aug 24 01:58:35 AM UTC 24
Finished Aug 24 01:58:38 AM UTC 24
Peak memory 248772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152258239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.152258239
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/40.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.3828564095
Short name T819
Test name
Test status
Simulation time 11228477 ps
CPU time 1.12 seconds
Started Aug 24 01:58:37 AM UTC 24
Finished Aug 24 01:58:39 AM UTC 24
Peak memory 248772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828564095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3828564095
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/41.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.3754626788
Short name T821
Test name
Test status
Simulation time 43927493 ps
CPU time 2.22 seconds
Started Aug 24 01:58:37 AM UTC 24
Finished Aug 24 01:58:40 AM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754626788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3754626788
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/42.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.3039504192
Short name T820
Test name
Test status
Simulation time 19382489 ps
CPU time 1.16 seconds
Started Aug 24 01:58:38 AM UTC 24
Finished Aug 24 01:58:40 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039504192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3039504192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/43.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.743447023
Short name T823
Test name
Test status
Simulation time 8557847 ps
CPU time 1.24 seconds
Started Aug 24 01:58:39 AM UTC 24
Finished Aug 24 01:58:41 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743447023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.743447023
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/44.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.1056819461
Short name T822
Test name
Test status
Simulation time 7720050 ps
CPU time 1.08 seconds
Started Aug 24 01:58:39 AM UTC 24
Finished Aug 24 01:58:41 AM UTC 24
Peak memory 246660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056819461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1056819461
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/45.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.3884342371
Short name T824
Test name
Test status
Simulation time 17396517 ps
CPU time 1.48 seconds
Started Aug 24 01:58:40 AM UTC 24
Finished Aug 24 01:58:42 AM UTC 24
Peak memory 248780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884342371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3884342371
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/46.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.448254154
Short name T826
Test name
Test status
Simulation time 9251818 ps
CPU time 1.28 seconds
Started Aug 24 01:58:41 AM UTC 24
Finished Aug 24 01:58:43 AM UTC 24
Peak memory 246732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448254154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.448254154
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/47.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.4247460926
Short name T825
Test name
Test status
Simulation time 13367941 ps
CPU time 1.09 seconds
Started Aug 24 01:58:41 AM UTC 24
Finished Aug 24 01:58:43 AM UTC 24
Peak memory 246732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247460926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.4247460926
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/48.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.1084010103
Short name T827
Test name
Test status
Simulation time 8083656 ps
CPU time 1.14 seconds
Started Aug 24 01:58:42 AM UTC 24
Finished Aug 24 01:58:44 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084010103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1084010103
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/49.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2625214035
Short name T245
Test name
Test status
Simulation time 76952447 ps
CPU time 4.6 seconds
Started Aug 24 01:50:37 AM UTC 24
Finished Aug 24 01:50:43 AM UTC 24
Peak memory 252576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625214035 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_
rw_with_rand_reset.2625214035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.1287879602
Short name T730
Test name
Test status
Simulation time 93847596 ps
CPU time 3.88 seconds
Started Aug 24 01:50:31 AM UTC 24
Finished Aug 24 01:50:36 AM UTC 24
Peak memory 252508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287879602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1287879602
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.3044007109
Short name T379
Test name
Test status
Simulation time 17053518 ps
CPU time 1.09 seconds
Started Aug 24 01:50:28 AM UTC 24
Finished Aug 24 01:50:30 AM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044007109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3044007109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.415180514
Short name T248
Test name
Test status
Simulation time 1581295387 ps
CPU time 19.71 seconds
Started Aug 24 01:50:31 AM UTC 24
Finished Aug 24 01:50:52 AM UTC 24
Peak memory 260624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415180514 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.415180514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1041033242
Short name T138
Test name
Test status
Simulation time 14670228639 ps
CPU time 80.8 seconds
Started Aug 24 01:50:11 AM UTC 24
Finished Aug 24 01:51:33 AM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041033242 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.1041033242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2429428971
Short name T149
Test name
Test status
Simulation time 4493713553 ps
CPU time 222.5 seconds
Started Aug 24 01:50:03 AM UTC 24
Finished Aug 24 01:53:48 AM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429428971 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shado
w_reg_errors_with_csr_rw.2429428971
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.1921831160
Short name T729
Test name
Test status
Simulation time 254627783 ps
CPU time 6.75 seconds
Started Aug 24 01:50:23 AM UTC 24
Finished Aug 24 01:50:30 AM UTC 24
Peak memory 268896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921831160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1921831160
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1480318692
Short name T214
Test name
Test status
Simulation time 53292785 ps
CPU time 3.16 seconds
Started Aug 24 01:50:23 AM UTC 24
Finished Aug 24 01:50:27 AM UTC 24
Peak memory 250396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480318692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1480318692
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2557552830
Short name T733
Test name
Test status
Simulation time 79513688 ps
CPU time 5.23 seconds
Started Aug 24 01:51:34 AM UTC 24
Finished Aug 24 01:51:41 AM UTC 24
Peak memory 252504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557552830 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_
rw_with_rand_reset.2557552830
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.3826136786
Short name T732
Test name
Test status
Simulation time 108347368 ps
CPU time 4.18 seconds
Started Aug 24 01:51:27 AM UTC 24
Finished Aug 24 01:51:32 AM UTC 24
Peak memory 252508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826136786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3826136786
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.1889394746
Short name T377
Test name
Test status
Simulation time 9694497 ps
CPU time 1.25 seconds
Started Aug 24 01:51:23 AM UTC 24
Finished Aug 24 01:51:26 AM UTC 24
Peak memory 246732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889394746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1889394746
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.291030925
Short name T259
Test name
Test status
Simulation time 329366028 ps
CPU time 18.42 seconds
Started Aug 24 01:51:33 AM UTC 24
Finished Aug 24 01:51:53 AM UTC 24
Peak memory 260764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291030925 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.291030925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.12758461
Short name T145
Test name
Test status
Simulation time 8681267269 ps
CPU time 114.86 seconds
Started Aug 24 01:50:52 AM UTC 24
Finished Aug 24 01:52:49 AM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12758461 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.12758461
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3432302760
Short name T143
Test name
Test status
Simulation time 16047199516 ps
CPU time 382.31 seconds
Started Aug 24 01:50:43 AM UTC 24
Finished Aug 24 01:57:10 AM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432302760 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shado
w_reg_errors_with_csr_rw.3432302760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.3207478338
Short name T731
Test name
Test status
Simulation time 184142859 ps
CPU time 11.14 seconds
Started Aug 24 01:51:06 AM UTC 24
Finished Aug 24 01:51:18 AM UTC 24
Peak memory 266848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207478338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3207478338
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2046552451
Short name T737
Test name
Test status
Simulation time 59960631 ps
CPU time 3.65 seconds
Started Aug 24 01:52:14 AM UTC 24
Finished Aug 24 01:52:19 AM UTC 24
Peak memory 252504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046552451 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_
rw_with_rand_reset.2046552451
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.2831411901
Short name T736
Test name
Test status
Simulation time 35057923 ps
CPU time 4.28 seconds
Started Aug 24 01:52:10 AM UTC 24
Finished Aug 24 01:52:16 AM UTC 24
Peak memory 250396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831411901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2831411901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.3495543624
Short name T376
Test name
Test status
Simulation time 12091367 ps
CPU time 1.08 seconds
Started Aug 24 01:52:08 AM UTC 24
Finished Aug 24 01:52:10 AM UTC 24
Peak memory 246732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495543624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3495543624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.115920680
Short name T738
Test name
Test status
Simulation time 247332652 ps
CPU time 13.85 seconds
Started Aug 24 01:52:11 AM UTC 24
Finished Aug 24 01:52:26 AM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115920680 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.115920680
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1768963228
Short name T163
Test name
Test status
Simulation time 9773112646 ps
CPU time 240.88 seconds
Started Aug 24 01:51:42 AM UTC 24
Finished Aug 24 01:55:46 AM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768963228 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shado
w_reg_errors_with_csr_rw.1768963228
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.1400145899
Short name T734
Test name
Test status
Simulation time 594015592 ps
CPU time 7.56 seconds
Started Aug 24 01:51:54 AM UTC 24
Finished Aug 24 01:52:03 AM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400145899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1400145899
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2295253858
Short name T742
Test name
Test status
Simulation time 62794030 ps
CPU time 8.16 seconds
Started Aug 24 01:52:54 AM UTC 24
Finished Aug 24 01:53:04 AM UTC 24
Peak memory 268960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295253858 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_
rw_with_rand_reset.2295253858
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.305327832
Short name T741
Test name
Test status
Simulation time 20396990 ps
CPU time 2.49 seconds
Started Aug 24 01:52:50 AM UTC 24
Finished Aug 24 01:52:54 AM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305327832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.305327832
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.1283957257
Short name T380
Test name
Test status
Simulation time 10642232 ps
CPU time 1.28 seconds
Started Aug 24 01:52:49 AM UTC 24
Finished Aug 24 01:52:51 AM UTC 24
Peak memory 248780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283957257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1283957257
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2134158576
Short name T745
Test name
Test status
Simulation time 722474235 ps
CPU time 38.35 seconds
Started Aug 24 01:52:52 AM UTC 24
Finished Aug 24 01:53:32 AM UTC 24
Peak memory 260768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134158576 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.2134158576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3688428728
Short name T146
Test name
Test status
Simulation time 8223702741 ps
CPU time 151.06 seconds
Started Aug 24 01:52:20 AM UTC 24
Finished Aug 24 01:54:53 AM UTC 24
Peak memory 279528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688428728 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.3688428728
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.361821541
Short name T159
Test name
Test status
Simulation time 12271869248 ps
CPU time 354.57 seconds
Started Aug 24 01:52:16 AM UTC 24
Finished Aug 24 01:58:15 AM UTC 24
Peak memory 281512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361821541 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow
_reg_errors_with_csr_rw.361821541
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.4000581597
Short name T740
Test name
Test status
Simulation time 2559994028 ps
CPU time 20.47 seconds
Started Aug 24 01:52:27 AM UTC 24
Finished Aug 24 01:52:48 AM UTC 24
Peak memory 262880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000581597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.4000581597
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1073024191
Short name T746
Test name
Test status
Simulation time 31746084 ps
CPU time 3.94 seconds
Started Aug 24 01:53:33 AM UTC 24
Finished Aug 24 01:53:38 AM UTC 24
Peak memory 252504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073024191 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_
rw_with_rand_reset.1073024191
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.654369880
Short name T747
Test name
Test status
Simulation time 184986082 ps
CPU time 6.11 seconds
Started Aug 24 01:53:30 AM UTC 24
Finished Aug 24 01:53:38 AM UTC 24
Peak memory 250332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654369880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.654369880
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.517655331
Short name T744
Test name
Test status
Simulation time 10677799 ps
CPU time 1.32 seconds
Started Aug 24 01:53:29 AM UTC 24
Finished Aug 24 01:53:31 AM UTC 24
Peak memory 246788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517655331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.517655331
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2985343569
Short name T750
Test name
Test status
Simulation time 539838846 ps
CPU time 29.63 seconds
Started Aug 24 01:53:31 AM UTC 24
Finished Aug 24 01:54:02 AM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985343569 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.2985343569
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.2532946241
Short name T743
Test name
Test status
Simulation time 386984998 ps
CPU time 13.23 seconds
Started Aug 24 01:53:14 AM UTC 24
Finished Aug 24 01:53:28 AM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532946241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2532946241
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.4060525175
Short name T241
Test name
Test status
Simulation time 19379066452 ps
CPU time 910.54 seconds
Started Aug 23 11:30:18 PM UTC 24
Finished Aug 23 11:45:38 PM UTC 24
Peak memory 279360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060525175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.4060525175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.2067503226
Short name T6
Test name
Test status
Simulation time 18970382222 ps
CPU time 33.59 seconds
Started Aug 23 11:30:19 PM UTC 24
Finished Aug 23 11:30:54 PM UTC 24
Peak memory 262948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067503226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2067503226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.374337901
Short name T66
Test name
Test status
Simulation time 7227571474 ps
CPU time 111.84 seconds
Started Aug 23 11:30:15 PM UTC 24
Finished Aug 23 11:32:09 PM UTC 24
Peak memory 268956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374337901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.374337901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.3986417230
Short name T1
Test name
Test status
Simulation time 94644088 ps
CPU time 3.7 seconds
Started Aug 23 11:30:13 PM UTC 24
Finished Aug 23 11:30:18 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986417230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3986417230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg_stub_clk.2480231611
Short name T108
Test name
Test status
Simulation time 43916577627 ps
CPU time 1038.62 seconds
Started Aug 23 11:30:19 PM UTC 24
Finished Aug 23 11:47:48 PM UTC 24
Peak memory 285476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480231611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2480231611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.880927978
Short name T19
Test name
Test status
Simulation time 19451143367 ps
CPU time 150.41 seconds
Started Aug 23 11:30:18 PM UTC 24
Finished Aug 23 11:32:51 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880927978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.880927978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.218562996
Short name T2
Test name
Test status
Simulation time 185466481 ps
CPU time 7.03 seconds
Started Aug 23 11:30:12 PM UTC 24
Finished Aug 23 11:30:20 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218562996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.218562996
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.4109037571
Short name T4
Test name
Test status
Simulation time 332081675 ps
CPU time 7.81 seconds
Started Aug 23 11:30:28 PM UTC 24
Finished Aug 23 11:30:37 PM UTC 24
Peak memory 297320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109037571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.4109037571
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.3378633963
Short name T3
Test name
Test status
Simulation time 210921085 ps
CPU time 10.24 seconds
Started Aug 23 11:30:11 PM UTC 24
Finished Aug 23 11:30:23 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378633963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3378633963
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.280163535
Short name T98
Test name
Test status
Simulation time 394746000473 ps
CPU time 1792.46 seconds
Started Aug 23 11:30:36 PM UTC 24
Finished Aug 24 12:00:46 AM UTC 24
Peak memory 302280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280163535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.280163535
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.2631814177
Short name T215
Test name
Test status
Simulation time 3192313638 ps
CPU time 140.37 seconds
Started Aug 23 11:30:30 PM UTC 24
Finished Aug 23 11:32:53 PM UTC 24
Peak memory 264984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631814177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2631814177
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.4169364979
Short name T17
Test name
Test status
Simulation time 80202467 ps
CPU time 5.08 seconds
Started Aug 23 11:30:30 PM UTC 24
Finished Aug 23 11:30:36 PM UTC 24
Peak memory 262652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169364979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.4169364979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg.1400048450
Short name T322
Test name
Test status
Simulation time 180961364356 ps
CPU time 1724.99 seconds
Started Aug 23 11:30:37 PM UTC 24
Finished Aug 23 11:59:39 PM UTC 24
Peak memory 302280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400048450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1400048450
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.211886325
Short name T18
Test name
Test status
Simulation time 13808410029 ps
CPU time 118.81 seconds
Started Aug 23 11:30:36 PM UTC 24
Finished Aug 23 11:32:37 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211886325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.211886325
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.3088833978
Short name T11
Test name
Test status
Simulation time 217043263 ps
CPU time 5.54 seconds
Started Aug 23 11:30:29 PM UTC 24
Finished Aug 23 11:30:36 PM UTC 24
Peak memory 264948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088833978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3088833978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.568486777
Short name T30
Test name
Test status
Simulation time 1013017112 ps
CPU time 13.04 seconds
Started Aug 23 11:30:29 PM UTC 24
Finished Aug 23 11:30:43 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568486777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.568486777
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.3746675080
Short name T27
Test name
Test status
Simulation time 522203798 ps
CPU time 15.85 seconds
Started Aug 23 11:30:40 PM UTC 24
Finished Aug 23 11:30:57 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746675080 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.3746675080
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.447674856
Short name T71
Test name
Test status
Simulation time 12922819 ps
CPU time 1.92 seconds
Started Aug 23 11:51:05 PM UTC 24
Finished Aug 23 11:51:08 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447674856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.447674856
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.3317333135
Short name T428
Test name
Test status
Simulation time 213017688631 ps
CPU time 1265.06 seconds
Started Aug 23 11:48:56 PM UTC 24
Finished Aug 24 12:10:14 AM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317333135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3317333135
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.1933013295
Short name T399
Test name
Test status
Simulation time 283694226 ps
CPU time 10.28 seconds
Started Aug 23 11:49:49 PM UTC 24
Finished Aug 23 11:50:00 PM UTC 24
Peak memory 263240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933013295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1933013295
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.542821639
Short name T398
Test name
Test status
Simulation time 897992092 ps
CPU time 52.53 seconds
Started Aug 23 11:48:54 PM UTC 24
Finished Aug 23 11:49:48 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542821639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.542821639
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.3837089470
Short name T396
Test name
Test status
Simulation time 410592216 ps
CPU time 6.41 seconds
Started Aug 23 11:48:45 PM UTC 24
Finished Aug 23 11:48:53 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837089470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3837089470
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.3876696189
Short name T319
Test name
Test status
Simulation time 38728783968 ps
CPU time 566.28 seconds
Started Aug 23 11:49:05 PM UTC 24
Finished Aug 23 11:58:37 PM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876696189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3876696189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.1715756996
Short name T326
Test name
Test status
Simulation time 36055611158 ps
CPU time 556.92 seconds
Started Aug 23 11:49:27 PM UTC 24
Finished Aug 23 11:58:50 PM UTC 24
Peak memory 279364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715756996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1715756996
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.3269878302
Short name T334
Test name
Test status
Simulation time 45828055581 ps
CPU time 348.27 seconds
Started Aug 23 11:49:02 PM UTC 24
Finished Aug 23 11:54:54 PM UTC 24
Peak memory 263312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269878302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3269878302
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.2523791477
Short name T397
Test name
Test status
Simulation time 6180177407 ps
CPU time 37.3 seconds
Started Aug 23 11:48:15 PM UTC 24
Finished Aug 23 11:48:54 PM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523791477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2523791477
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.1738959389
Short name T395
Test name
Test status
Simulation time 820409568 ps
CPU time 11.83 seconds
Started Aug 23 11:48:30 PM UTC 24
Finished Aug 23 11:48:44 PM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738959389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1738959389
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.3972498354
Short name T330
Test name
Test status
Simulation time 145763723 ps
CPU time 7.69 seconds
Started Aug 23 11:48:55 PM UTC 24
Finished Aug 23 11:49:04 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972498354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3972498354
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.2690303281
Short name T313
Test name
Test status
Simulation time 4614599080 ps
CPU time 46.26 seconds
Started Aug 23 11:48:08 PM UTC 24
Finished Aug 23 11:48:55 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690303281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2690303281
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.3043694489
Short name T371
Test name
Test status
Simulation time 162248495844 ps
CPU time 750.98 seconds
Started Aug 23 11:50:01 PM UTC 24
Finished Aug 24 12:02:40 AM UTC 24
Peak memory 285824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043694489 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.3043694489
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/10.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.67678736
Short name T400
Test name
Test status
Simulation time 691070280 ps
CPU time 11.1 seconds
Started Aug 23 11:52:25 PM UTC 24
Finished Aug 23 11:52:37 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67678736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h
andler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.67678736
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.256987840
Short name T222
Test name
Test status
Simulation time 4350668449 ps
CPU time 183 seconds
Started Aug 23 11:51:19 PM UTC 24
Finished Aug 23 11:54:25 PM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256987840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.256987840
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.1572464991
Short name T77
Test name
Test status
Simulation time 172294221 ps
CPU time 14.74 seconds
Started Aug 23 11:51:17 PM UTC 24
Finished Aug 23 11:51:33 PM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572464991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1572464991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.4017883715
Short name T436
Test name
Test status
Simulation time 114475363970 ps
CPU time 1207 seconds
Started Aug 23 11:51:56 PM UTC 24
Finished Aug 24 12:12:15 AM UTC 24
Peak memory 285520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017883715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.4017883715
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.1321890553
Short name T329
Test name
Test status
Simulation time 4229144790 ps
CPU time 73.06 seconds
Started Aug 23 11:51:34 PM UTC 24
Finished Aug 23 11:52:48 PM UTC 24
Peak memory 263056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321890553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1321890553
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.1658754042
Short name T74
Test name
Test status
Simulation time 749317843 ps
CPU time 9.42 seconds
Started Aug 23 11:51:08 PM UTC 24
Finished Aug 23 11:51:19 PM UTC 24
Peak memory 267392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658754042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1658754042
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.2803671420
Short name T75
Test name
Test status
Simulation time 286550055 ps
CPU time 21.9 seconds
Started Aug 23 11:51:09 PM UTC 24
Finished Aug 23 11:51:33 PM UTC 24
Peak memory 269076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803671420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2803671420
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.1880585254
Short name T73
Test name
Test status
Simulation time 204277880 ps
CPU time 8.63 seconds
Started Aug 23 11:51:07 PM UTC 24
Finished Aug 23 11:51:17 PM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880585254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1880585254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.3433710965
Short name T285
Test name
Test status
Simulation time 498459446997 ps
CPU time 1169.44 seconds
Started Aug 23 11:52:38 PM UTC 24
Finished Aug 24 12:12:19 AM UTC 24
Peak memory 285568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433710965 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.3433710965
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/11.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.3995468076
Short name T228
Test name
Test status
Simulation time 113601242 ps
CPU time 2.59 seconds
Started Aug 23 11:55:47 PM UTC 24
Finished Aug 23 11:55:51 PM UTC 24
Peak memory 263500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995468076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3995468076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.85888132
Short name T121
Test name
Test status
Simulation time 15764877228 ps
CPU time 726.04 seconds
Started Aug 23 11:54:27 PM UTC 24
Finished Aug 24 12:06:40 AM UTC 24
Peak memory 279436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85888132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/a
lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.85888132
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.3040420018
Short name T404
Test name
Test status
Simulation time 139494495 ps
CPU time 6.33 seconds
Started Aug 23 11:55:12 PM UTC 24
Finished Aug 23 11:55:19 PM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040420018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3040420018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.3218785599
Short name T406
Test name
Test status
Simulation time 17920211150 ps
CPU time 184.32 seconds
Started Aug 23 11:54:11 PM UTC 24
Finished Aug 23 11:57:18 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218785599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3218785599
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.4054351230
Short name T403
Test name
Test status
Simulation time 5257429723 ps
CPU time 19.76 seconds
Started Aug 23 11:54:10 PM UTC 24
Finished Aug 23 11:54:31 PM UTC 24
Peak memory 263328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054351230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4054351230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.1176698418
Short name T368
Test name
Test status
Simulation time 38729762612 ps
CPU time 1830.48 seconds
Started Aug 23 11:54:46 PM UTC 24
Finished Aug 24 12:25:34 AM UTC 24
Peak memory 304936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176698418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1176698418
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.2501520623
Short name T425
Test name
Test status
Simulation time 16262684031 ps
CPU time 675.93 seconds
Started Aug 23 11:54:55 PM UTC 24
Finished Aug 24 12:06:18 AM UTC 24
Peak memory 295824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501520623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2501520623
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.3747322414
Short name T401
Test name
Test status
Simulation time 312968596 ps
CPU time 8.03 seconds
Started Aug 23 11:53:34 PM UTC 24
Finished Aug 23 11:53:43 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747322414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3747322414
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.4185703199
Short name T88
Test name
Test status
Simulation time 1334563591 ps
CPU time 24.97 seconds
Started Aug 23 11:53:44 PM UTC 24
Finished Aug 23 11:54:10 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185703199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.4185703199
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.1137391111
Short name T76
Test name
Test status
Simulation time 815851412 ps
CPU time 18.76 seconds
Started Aug 23 11:54:25 PM UTC 24
Finished Aug 23 11:54:45 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137391111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1137391111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.800139150
Short name T402
Test name
Test status
Simulation time 7531084978 ps
CPU time 42.69 seconds
Started Aug 23 11:53:25 PM UTC 24
Finished Aug 23 11:54:09 PM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800139150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.800139150
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all.677224491
Short name T270
Test name
Test status
Simulation time 130334189168 ps
CPU time 1457.32 seconds
Started Aug 23 11:55:20 PM UTC 24
Finished Aug 24 12:19:51 AM UTC 24
Peak memory 300832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677224491 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all.677224491
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/12.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.2735176050
Short name T229
Test name
Test status
Simulation time 32748113 ps
CPU time 2.87 seconds
Started Aug 23 11:59:41 PM UTC 24
Finished Aug 23 11:59:44 PM UTC 24
Peak memory 263500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735176050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2735176050
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.82684429
Short name T446
Test name
Test status
Simulation time 70541425023 ps
CPU time 1102.16 seconds
Started Aug 23 11:58:05 PM UTC 24
Finished Aug 24 12:16:38 AM UTC 24
Peak memory 285512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82684429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/a
lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.82684429
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.3574576911
Short name T409
Test name
Test status
Simulation time 386849847 ps
CPU time 5.47 seconds
Started Aug 23 11:59:08 PM UTC 24
Finished Aug 23 11:59:14 PM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574576911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3574576911
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.169180942
Short name T315
Test name
Test status
Simulation time 13491826211 ps
CPU time 155.11 seconds
Started Aug 23 11:57:38 PM UTC 24
Finished Aug 24 12:00:15 AM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169180942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.169180942
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.65626882
Short name T408
Test name
Test status
Simulation time 62714403 ps
CPU time 3.86 seconds
Started Aug 23 11:57:32 PM UTC 24
Finished Aug 23 11:57:37 PM UTC 24
Peak memory 252992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65626882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc
_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.65626882
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.1694212777
Short name T352
Test name
Test status
Simulation time 115718187156 ps
CPU time 1264.9 seconds
Started Aug 23 11:58:39 PM UTC 24
Finished Aug 24 12:19:56 AM UTC 24
Peak memory 288556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694212777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1694212777
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.377419770
Short name T448
Test name
Test status
Simulation time 59323310639 ps
CPU time 1127.67 seconds
Started Aug 23 11:58:51 PM UTC 24
Finished Aug 24 12:17:50 AM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377419770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.377419770
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.2812511434
Short name T328
Test name
Test status
Simulation time 3604443775 ps
CPU time 109.62 seconds
Started Aug 23 11:58:28 PM UTC 24
Finished Aug 24 12:00:20 AM UTC 24
Peak memory 269128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812511434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2812511434
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.1874822258
Short name T54
Test name
Test status
Simulation time 528211506 ps
CPU time 28.82 seconds
Started Aug 23 11:57:10 PM UTC 24
Finished Aug 23 11:57:40 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874822258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1874822258
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.2849811288
Short name T407
Test name
Test status
Simulation time 133578613 ps
CPU time 11.23 seconds
Started Aug 23 11:57:19 PM UTC 24
Finished Aug 23 11:57:31 PM UTC 24
Peak memory 263004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849811288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2849811288
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.4031514777
Short name T405
Test name
Test status
Simulation time 978648073 ps
CPU time 13.23 seconds
Started Aug 23 11:56:55 PM UTC 24
Finished Aug 23 11:57:10 PM UTC 24
Peak memory 269060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031514777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.4031514777
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.3833018336
Short name T58
Test name
Test status
Simulation time 130047038198 ps
CPU time 822.11 seconds
Started Aug 23 11:59:15 PM UTC 24
Finished Aug 24 12:13:06 AM UTC 24
Peak memory 301880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833018336 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.3833018336
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all_with_rand_reset.1216117325
Short name T197
Test name
Test status
Simulation time 1753067228 ps
CPU time 154.88 seconds
Started Aug 23 11:59:46 PM UTC 24
Finished Aug 24 12:02:23 AM UTC 24
Peak memory 285884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1216117325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.a
lert_handler_stress_all_with_rand_reset.1216117325
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.3272842601
Short name T230
Test name
Test status
Simulation time 15261284 ps
CPU time 2.32 seconds
Started Aug 24 12:01:44 AM UTC 24
Finished Aug 24 12:01:47 AM UTC 24
Peak memory 263248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272842601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3272842601
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.3746213645
Short name T299
Test name
Test status
Simulation time 162926147619 ps
CPU time 2095.02 seconds
Started Aug 24 12:00:53 AM UTC 24
Finished Aug 24 12:36:09 AM UTC 24
Peak memory 304684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746213645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3746213645
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.3915985066
Short name T415
Test name
Test status
Simulation time 1860657628 ps
CPU time 30.93 seconds
Started Aug 24 12:01:11 AM UTC 24
Finished Aug 24 12:01:43 AM UTC 24
Peak memory 263240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915985066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3915985066
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.3117450156
Short name T413
Test name
Test status
Simulation time 57521112 ps
CPU time 4.97 seconds
Started Aug 24 12:00:48 AM UTC 24
Finished Aug 24 12:00:54 AM UTC 24
Peak memory 267068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117450156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3117450156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.2231739966
Short name T127
Test name
Test status
Simulation time 2424196725 ps
CPU time 21.08 seconds
Started Aug 24 12:00:45 AM UTC 24
Finished Aug 24 12:01:08 AM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231739966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2231739966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.178132912
Short name T361
Test name
Test status
Simulation time 14934707048 ps
CPU time 807.71 seconds
Started Aug 24 12:00:56 AM UTC 24
Finished Aug 24 12:14:32 AM UTC 24
Peak memory 295740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178132912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.178132912
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.1073200642
Short name T430
Test name
Test status
Simulation time 6138931650 ps
CPU time 554.37 seconds
Started Aug 24 12:01:09 AM UTC 24
Finished Aug 24 12:10:30 AM UTC 24
Peak memory 285512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073200642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1073200642
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.133148296
Short name T337
Test name
Test status
Simulation time 33527034214 ps
CPU time 220.62 seconds
Started Aug 24 12:00:55 AM UTC 24
Finished Aug 24 12:04:38 AM UTC 24
Peak memory 263044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133148296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.133148296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.3253062760
Short name T410
Test name
Test status
Simulation time 425870499 ps
CPU time 21.56 seconds
Started Aug 24 12:00:21 AM UTC 24
Finished Aug 24 12:00:44 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253062760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3253062760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.179217926
Short name T412
Test name
Test status
Simulation time 77079126 ps
CPU time 4.11 seconds
Started Aug 24 12:00:45 AM UTC 24
Finished Aug 24 12:00:50 AM UTC 24
Peak memory 265280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179217926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.179217926
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.2406870180
Short name T414
Test name
Test status
Simulation time 1422642717 ps
CPU time 17.74 seconds
Started Aug 24 12:00:51 AM UTC 24
Finished Aug 24 12:01:10 AM UTC 24
Peak memory 262928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406870180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2406870180
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.1864586456
Short name T411
Test name
Test status
Simulation time 615471162 ps
CPU time 26.93 seconds
Started Aug 24 12:00:16 AM UTC 24
Finished Aug 24 12:00:44 AM UTC 24
Peak memory 269448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864586456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1864586456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.2204366365
Short name T217
Test name
Test status
Simulation time 29318419815 ps
CPU time 609.56 seconds
Started Aug 24 12:01:31 AM UTC 24
Finished Aug 24 12:11:47 AM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204366365 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.2204366365
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all_with_rand_reset.3961278352
Short name T198
Test name
Test status
Simulation time 1283433773 ps
CPU time 57.18 seconds
Started Aug 24 12:01:48 AM UTC 24
Finished Aug 24 12:02:47 AM UTC 24
Peak memory 283840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3961278352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.a
lert_handler_stress_all_with_rand_reset.3961278352
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.2617303684
Short name T231
Test name
Test status
Simulation time 472532063 ps
CPU time 2.76 seconds
Started Aug 24 12:03:45 AM UTC 24
Finished Aug 24 12:03:49 AM UTC 24
Peak memory 263500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617303684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2617303684
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy.3399039124
Short name T295
Test name
Test status
Simulation time 17805263598 ps
CPU time 1217.45 seconds
Started Aug 24 12:03:05 AM UTC 24
Finished Aug 24 12:23:34 AM UTC 24
Peak memory 304684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399039124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3399039124
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.688266626
Short name T422
Test name
Test status
Simulation time 411175192 ps
CPU time 15.4 seconds
Started Aug 24 12:03:30 AM UTC 24
Finished Aug 24 12:03:47 AM UTC 24
Peak memory 262916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688266626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.688266626
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.250760397
Short name T421
Test name
Test status
Simulation time 2780691841 ps
CPU time 40.54 seconds
Started Aug 24 12:03:03 AM UTC 24
Finished Aug 24 12:03:45 AM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250760397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.250760397
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.249067640
Short name T420
Test name
Test status
Simulation time 1104081368 ps
CPU time 45.1 seconds
Started Aug 24 12:02:48 AM UTC 24
Finished Aug 24 12:03:34 AM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249067640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.249067640
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.4087921012
Short name T367
Test name
Test status
Simulation time 59368567265 ps
CPU time 1291.78 seconds
Started Aug 24 12:03:14 AM UTC 24
Finished Aug 24 12:24:59 AM UTC 24
Peak memory 288220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087921012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.4087921012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.433569760
Short name T451
Test name
Test status
Simulation time 28964112061 ps
CPU time 892.49 seconds
Started Aug 24 12:03:24 AM UTC 24
Finished Aug 24 12:18:26 AM UTC 24
Peak memory 297860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433569760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.433569760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.1265758824
Short name T107
Test name
Test status
Simulation time 27752683644 ps
CPU time 216.44 seconds
Started Aug 24 12:03:12 AM UTC 24
Finished Aug 24 12:06:51 AM UTC 24
Peak memory 263312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265758824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1265758824
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.2270724384
Short name T416
Test name
Test status
Simulation time 721650840 ps
CPU time 32.6 seconds
Started Aug 24 12:02:29 AM UTC 24
Finished Aug 24 12:03:03 AM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270724384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2270724384
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.2090701074
Short name T419
Test name
Test status
Simulation time 3737575081 ps
CPU time 45.91 seconds
Started Aug 24 12:02:42 AM UTC 24
Finished Aug 24 12:03:29 AM UTC 24
Peak memory 263324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090701074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2090701074
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.1840244676
Short name T417
Test name
Test status
Simulation time 850030604 ps
CPU time 38.46 seconds
Started Aug 24 12:02:24 AM UTC 24
Finished Aug 24 12:03:04 AM UTC 24
Peak memory 269128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840244676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1840244676
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all_with_rand_reset.2562833792
Short name T91
Test name
Test status
Simulation time 32525764092 ps
CPU time 214.22 seconds
Started Aug 24 12:03:47 AM UTC 24
Finished Aug 24 12:07:24 AM UTC 24
Peak memory 279872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2562833792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.a
lert_handler_stress_all_with_rand_reset.2562833792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.795832510
Short name T232
Test name
Test status
Simulation time 23801607 ps
CPU time 2.32 seconds
Started Aug 24 12:06:52 AM UTC 24
Finished Aug 24 12:06:55 AM UTC 24
Peak memory 263244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795832510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.795832510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.1889694158
Short name T279
Test name
Test status
Simulation time 142055384918 ps
CPU time 1556.35 seconds
Started Aug 24 12:05:24 AM UTC 24
Finished Aug 24 12:31:36 AM UTC 24
Peak memory 298464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889694158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1889694158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.4190939823
Short name T249
Test name
Test status
Simulation time 8699400596 ps
CPU time 61.39 seconds
Started Aug 24 12:06:43 AM UTC 24
Finished Aug 24 12:07:46 AM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190939823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.4190939823
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.874761693
Short name T426
Test name
Test status
Simulation time 10047007222 ps
CPU time 122.03 seconds
Started Aug 24 12:04:38 AM UTC 24
Finished Aug 24 12:06:43 AM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874761693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.874761693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.1827040841
Short name T424
Test name
Test status
Simulation time 956563302 ps
CPU time 17.24 seconds
Started Aug 24 12:04:30 AM UTC 24
Finished Aug 24 12:04:50 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827040841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1827040841
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.2572843067
Short name T366
Test name
Test status
Simulation time 31198880453 ps
CPU time 1197.04 seconds
Started Aug 24 12:06:33 AM UTC 24
Finished Aug 24 12:26:43 AM UTC 24
Peak memory 287040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572843067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2572843067
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.419827447
Short name T447
Test name
Test status
Simulation time 37315568782 ps
CPU time 602.95 seconds
Started Aug 24 12:06:43 AM UTC 24
Finished Aug 24 12:16:52 AM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419827447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.419827447
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.3460751570
Short name T298
Test name
Test status
Simulation time 11305533514 ps
CPU time 322.49 seconds
Started Aug 24 12:06:19 AM UTC 24
Finished Aug 24 12:11:46 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460751570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3460751570
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.2651524396
Short name T56
Test name
Test status
Simulation time 122781328 ps
CPU time 8.88 seconds
Started Aug 24 12:04:04 AM UTC 24
Finished Aug 24 12:04:15 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651524396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2651524396
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.3253753158
Short name T290
Test name
Test status
Simulation time 2663981830 ps
CPU time 13.04 seconds
Started Aug 24 12:04:15 AM UTC 24
Finished Aug 24 12:04:30 AM UTC 24
Peak memory 263196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253753158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3253753158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.119466577
Short name T423
Test name
Test status
Simulation time 434187003 ps
CPU time 11.84 seconds
Started Aug 24 12:03:50 AM UTC 24
Finished Aug 24 12:04:03 AM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119466577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.119466577
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/16.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.862602714
Short name T233
Test name
Test status
Simulation time 22129572 ps
CPU time 1.94 seconds
Started Aug 24 12:10:12 AM UTC 24
Finished Aug 24 12:10:15 AM UTC 24
Peak memory 260572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862602714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.862602714
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.3181679903
Short name T101
Test name
Test status
Simulation time 10688134807 ps
CPU time 676.49 seconds
Started Aug 24 12:08:23 AM UTC 24
Finished Aug 24 12:19:46 AM UTC 24
Peak memory 295740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181679903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3181679903
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.2591298845
Short name T427
Test name
Test status
Simulation time 151913342 ps
CPU time 6.96 seconds
Started Aug 24 12:09:54 AM UTC 24
Finished Aug 24 12:10:02 AM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591298845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2591298845
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.350454106
Short name T255
Test name
Test status
Simulation time 3666992910 ps
CPU time 22.02 seconds
Started Aug 24 12:08:16 AM UTC 24
Finished Aug 24 12:08:39 AM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350454106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.350454106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.3931642309
Short name T254
Test name
Test status
Simulation time 584859120 ps
CPU time 14.69 seconds
Started Aug 24 12:08:10 AM UTC 24
Finished Aug 24 12:08:26 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931642309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3931642309
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.3546540132
Short name T349
Test name
Test status
Simulation time 46042999667 ps
CPU time 835.42 seconds
Started Aug 24 12:08:40 AM UTC 24
Finished Aug 24 12:22:44 AM UTC 24
Peak memory 295740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546540132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3546540132
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.2196423156
Short name T476
Test name
Test status
Simulation time 124600950825 ps
CPU time 1374.57 seconds
Started Aug 24 12:08:46 AM UTC 24
Finished Aug 24 12:31:55 AM UTC 24
Peak memory 298472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196423156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2196423156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.3820298008
Short name T340
Test name
Test status
Simulation time 26098064124 ps
CPU time 225.3 seconds
Started Aug 24 12:08:27 AM UTC 24
Finished Aug 24 12:12:16 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820298008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3820298008
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.3533498749
Short name T252
Test name
Test status
Simulation time 542646584 ps
CPU time 27.18 seconds
Started Aug 24 12:07:46 AM UTC 24
Finished Aug 24 12:08:15 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533498749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3533498749
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.3408342120
Short name T253
Test name
Test status
Simulation time 508436297 ps
CPU time 21.54 seconds
Started Aug 24 12:07:52 AM UTC 24
Finished Aug 24 12:08:15 AM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408342120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3408342120
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.2656392894
Short name T256
Test name
Test status
Simulation time 3723911885 ps
CPU time 27.86 seconds
Started Aug 24 12:08:16 AM UTC 24
Finished Aug 24 12:08:45 AM UTC 24
Peak memory 269396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656392894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2656392894
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.1115132936
Short name T250
Test name
Test status
Simulation time 555124439 ps
CPU time 24.3 seconds
Started Aug 24 12:07:25 AM UTC 24
Finished Aug 24 12:07:51 AM UTC 24
Peak memory 269040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115132936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1115132936
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.305515123
Short name T63
Test name
Test status
Simulation time 183699393188 ps
CPU time 2035.11 seconds
Started Aug 24 12:10:03 AM UTC 24
Finished Aug 24 12:44:18 AM UTC 24
Peak memory 304600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305515123 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.305515123
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/17.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.1469489891
Short name T234
Test name
Test status
Simulation time 220970079 ps
CPU time 1.9 seconds
Started Aug 24 12:11:55 AM UTC 24
Finished Aug 24 12:11:58 AM UTC 24
Peak memory 260512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469489891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1469489891
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.2509773182
Short name T480
Test name
Test status
Simulation time 532480217654 ps
CPU time 1324.49 seconds
Started Aug 24 12:11:07 AM UTC 24
Finished Aug 24 12:33:25 AM UTC 24
Peak memory 288224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509773182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2509773182
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.577782252
Short name T435
Test name
Test status
Simulation time 2316717656 ps
CPU time 5.78 seconds
Started Aug 24 12:11:47 AM UTC 24
Finished Aug 24 12:11:54 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577782252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.577782252
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.3326525786
Short name T440
Test name
Test status
Simulation time 18666695185 ps
CPU time 193.1 seconds
Started Aug 24 12:10:48 AM UTC 24
Finished Aug 24 12:14:03 AM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326525786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3326525786
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.1009544277
Short name T432
Test name
Test status
Simulation time 161580409 ps
CPU time 14.16 seconds
Started Aug 24 12:10:32 AM UTC 24
Finished Aug 24 12:10:47 AM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009544277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1009544277
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.1917207824
Short name T350
Test name
Test status
Simulation time 32232699815 ps
CPU time 1326.7 seconds
Started Aug 24 12:11:18 AM UTC 24
Finished Aug 24 12:33:37 AM UTC 24
Peak memory 286968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917207824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1917207824
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.518469693
Short name T500
Test name
Test status
Simulation time 158896827756 ps
CPU time 1677.4 seconds
Started Aug 24 12:11:46 AM UTC 24
Finished Aug 24 12:40:00 AM UTC 24
Peak memory 288224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518469693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.518469693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.3950757000
Short name T431
Test name
Test status
Simulation time 1444173306 ps
CPU time 8.77 seconds
Started Aug 24 12:10:21 AM UTC 24
Finished Aug 24 12:10:31 AM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950757000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3950757000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.56696480
Short name T433
Test name
Test status
Simulation time 1502849897 ps
CPU time 32.97 seconds
Started Aug 24 12:10:31 AM UTC 24
Finished Aug 24 12:11:06 AM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56696480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran
dom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.56696480
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.4132491524
Short name T429
Test name
Test status
Simulation time 212485106 ps
CPU time 3.57 seconds
Started Aug 24 12:10:16 AM UTC 24
Finished Aug 24 12:10:20 AM UTC 24
Peak memory 263240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132491524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.4132491524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.911973356
Short name T111
Test name
Test status
Simulation time 11929854083 ps
CPU time 766.68 seconds
Started Aug 24 12:11:49 AM UTC 24
Finished Aug 24 12:24:44 AM UTC 24
Peak memory 297852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911973356 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.911973356
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/18.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.2781542038
Short name T235
Test name
Test status
Simulation time 21674325 ps
CPU time 1.81 seconds
Started Aug 24 12:14:05 AM UTC 24
Finished Aug 24 12:14:08 AM UTC 24
Peak memory 260512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781542038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2781542038
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.1015013301
Short name T518
Test name
Test status
Simulation time 98345833048 ps
CPU time 1963.5 seconds
Started Aug 24 12:12:51 AM UTC 24
Finished Aug 24 12:45:53 AM UTC 24
Peak memory 304680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015013301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1015013301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.1252806766
Short name T439
Test name
Test status
Simulation time 309498711 ps
CPU time 6.99 seconds
Started Aug 24 12:13:07 AM UTC 24
Finished Aug 24 12:13:16 AM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252806766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1252806766
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.46714510
Short name T438
Test name
Test status
Simulation time 231806996 ps
CPU time 10.42 seconds
Started Aug 24 12:12:46 AM UTC 24
Finished Aug 24 12:12:58 AM UTC 24
Peak memory 267292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46714510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc
_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.46714510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.1975189552
Short name T113
Test name
Test status
Simulation time 135917003 ps
CPU time 13.33 seconds
Started Aug 24 12:12:32 AM UTC 24
Finished Aug 24 12:12:47 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975189552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1975189552
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.2509224043
Short name T304
Test name
Test status
Simulation time 153588462359 ps
CPU time 1573.95 seconds
Started Aug 24 12:12:58 AM UTC 24
Finished Aug 24 12:39:28 AM UTC 24
Peak memory 288296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509224043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2509224043
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.3287806637
Short name T515
Test name
Test status
Simulation time 157074899079 ps
CPU time 1882.51 seconds
Started Aug 24 12:13:07 AM UTC 24
Finished Aug 24 12:44:49 AM UTC 24
Peak memory 304948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287806637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3287806637
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.970827403
Short name T344
Test name
Test status
Simulation time 12431858920 ps
CPU time 109.41 seconds
Started Aug 24 12:12:56 AM UTC 24
Finished Aug 24 12:14:48 AM UTC 24
Peak memory 263364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970827403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.970827403
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.1757644845
Short name T102
Test name
Test status
Simulation time 3728020835 ps
CPU time 44.3 seconds
Started Aug 24 12:12:20 AM UTC 24
Finished Aug 24 12:13:06 AM UTC 24
Peak memory 263324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757644845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1757644845
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.3769875244
Short name T110
Test name
Test status
Simulation time 270772422 ps
CPU time 7.07 seconds
Started Aug 24 12:12:47 AM UTC 24
Finished Aug 24 12:12:55 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769875244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3769875244
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.1120131339
Short name T437
Test name
Test status
Simulation time 316401310 ps
CPU time 13.6 seconds
Started Aug 24 12:12:16 AM UTC 24
Finished Aug 24 12:12:31 AM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120131339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1120131339
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/19.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.4141348169
Short name T434
Test name
Test status
Simulation time 51795038511 ps
CPU time 2398.57 seconds
Started Aug 23 11:30:54 PM UTC 24
Finished Aug 24 12:11:16 AM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141348169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.4141348169
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.3776802334
Short name T7
Test name
Test status
Simulation time 481878920 ps
CPU time 16.88 seconds
Started Aug 23 11:30:57 PM UTC 24
Finished Aug 23 11:31:15 PM UTC 24
Peak memory 262920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776802334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3776802334
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.1981823639
Short name T32
Test name
Test status
Simulation time 1347604423 ps
CPU time 55.94 seconds
Started Aug 23 11:30:49 PM UTC 24
Finished Aug 23 11:31:47 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981823639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1981823639
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.2590124482
Short name T239
Test name
Test status
Simulation time 97133573910 ps
CPU time 590.15 seconds
Started Aug 23 11:30:55 PM UTC 24
Finished Aug 23 11:40:52 PM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590124482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2590124482
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.1285130749
Short name T351
Test name
Test status
Simulation time 39426253828 ps
CPU time 971.65 seconds
Started Aug 23 11:30:55 PM UTC 24
Finished Aug 23 11:47:17 PM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285130749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1285130749
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.3641361139
Short name T38
Test name
Test status
Simulation time 7125066577 ps
CPU time 47.28 seconds
Started Aug 23 11:30:47 PM UTC 24
Finished Aug 23 11:31:36 PM UTC 24
Peak memory 263036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641361139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3641361139
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.2009948236
Short name T14
Test name
Test status
Simulation time 585586760 ps
CPU time 15.19 seconds
Started Aug 23 11:30:49 PM UTC 24
Finished Aug 23 11:31:06 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009948236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2009948236
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.3932908321
Short name T26
Test name
Test status
Simulation time 1435935661 ps
CPU time 7.88 seconds
Started Aug 23 11:30:45 PM UTC 24
Finished Aug 23 11:30:54 PM UTC 24
Peak memory 269052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932908321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3932908321
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.2907836650
Short name T57
Test name
Test status
Simulation time 178549004340 ps
CPU time 2118.85 seconds
Started Aug 23 11:31:01 PM UTC 24
Finished Aug 24 12:06:41 AM UTC 24
Peak memory 318256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907836650 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.2907836650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/2.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.2773634811
Short name T306
Test name
Test status
Simulation time 100315467808 ps
CPU time 832.48 seconds
Started Aug 24 12:15:49 AM UTC 24
Finished Aug 24 12:29:50 AM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773634811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2773634811
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/20.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.230919841
Short name T445
Test name
Test status
Simulation time 21260355646 ps
CPU time 89.81 seconds
Started Aug 24 12:15:04 AM UTC 24
Finished Aug 24 12:16:36 AM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230919841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.230919841
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.1510939089
Short name T128
Test name
Test status
Simulation time 1260286244 ps
CPU time 53.93 seconds
Started Aug 24 12:14:53 AM UTC 24
Finished Aug 24 12:15:48 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510939089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1510939089
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.802023129
Short name T374
Test name
Test status
Simulation time 127188518337 ps
CPU time 1209.59 seconds
Started Aug 24 12:16:28 AM UTC 24
Finished Aug 24 12:36:50 AM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802023129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.802023129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/20.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.4264426092
Short name T492
Test name
Test status
Simulation time 132491877665 ps
CPU time 1176.39 seconds
Started Aug 24 12:16:36 AM UTC 24
Finished Aug 24 12:36:25 AM UTC 24
Peak memory 285508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264426092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.4264426092
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.2610406871
Short name T316
Test name
Test status
Simulation time 7234048428 ps
CPU time 218.23 seconds
Started Aug 24 12:16:08 AM UTC 24
Finished Aug 24 12:19:50 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610406871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2610406871
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.142867886
Short name T442
Test name
Test status
Simulation time 101131188 ps
CPU time 3.64 seconds
Started Aug 24 12:14:48 AM UTC 24
Finished Aug 24 12:14:52 AM UTC 24
Peak memory 265272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142867886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.142867886
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.123680374
Short name T443
Test name
Test status
Simulation time 1064436317 ps
CPU time 37.93 seconds
Started Aug 24 12:14:49 AM UTC 24
Finished Aug 24 12:15:28 AM UTC 24
Peak memory 263040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123680374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.123680374
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/20.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.1838532567
Short name T444
Test name
Test status
Simulation time 1634172515 ps
CPU time 36.91 seconds
Started Aug 24 12:15:29 AM UTC 24
Finished Aug 24 12:16:07 AM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838532567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1838532567
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.1735145442
Short name T441
Test name
Test status
Simulation time 1150031593 ps
CPU time 12.62 seconds
Started Aug 24 12:14:34 AM UTC 24
Finished Aug 24 12:14:47 AM UTC 24
Peak memory 269128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735145442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1735145442
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/20.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all.2233567739
Short name T115
Test name
Test status
Simulation time 6144128136 ps
CPU time 395.17 seconds
Started Aug 24 12:16:39 AM UTC 24
Finished Aug 24 12:23:19 AM UTC 24
Peak memory 279348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233567739 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all.2233567739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/20.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.2053796895
Short name T454
Test name
Test status
Simulation time 1927194078 ps
CPU time 160.72 seconds
Started Aug 24 12:16:54 AM UTC 24
Finished Aug 24 12:19:37 AM UTC 24
Peak memory 279612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2053796895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.a
lert_handler_stress_all_with_rand_reset.2053796895
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.299492274
Short name T455
Test name
Test status
Simulation time 6896973065 ps
CPU time 69.69 seconds
Started Aug 24 12:18:50 AM UTC 24
Finished Aug 24 12:20:02 AM UTC 24
Peak memory 269140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299492274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.299492274
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.2803578704
Short name T452
Test name
Test status
Simulation time 276744636 ps
CPU time 21.1 seconds
Started Aug 24 12:18:27 AM UTC 24
Finished Aug 24 12:18:49 AM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803578704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2803578704
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.3070901152
Short name T357
Test name
Test status
Simulation time 155295120413 ps
CPU time 1711.09 seconds
Started Aug 24 12:19:38 AM UTC 24
Finished Aug 24 12:48:25 AM UTC 24
Peak memory 304936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070901152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3070901152
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/21.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.3615916238
Short name T486
Test name
Test status
Simulation time 52550135560 ps
CPU time 924.89 seconds
Started Aug 24 12:19:48 AM UTC 24
Finished Aug 24 12:35:23 AM UTC 24
Peak memory 295748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615916238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3615916238
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.4020988497
Short name T346
Test name
Test status
Simulation time 11133958296 ps
CPU time 88.05 seconds
Started Aug 24 12:19:29 AM UTC 24
Finished Aug 24 12:20:59 AM UTC 24
Peak memory 262984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020988497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.4020988497
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.2098805310
Short name T450
Test name
Test status
Simulation time 2843090361 ps
CPU time 24.85 seconds
Started Aug 24 12:17:59 AM UTC 24
Finished Aug 24 12:18:25 AM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098805310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2098805310
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.2375785504
Short name T453
Test name
Test status
Simulation time 1386966973 ps
CPU time 31.31 seconds
Started Aug 24 12:18:27 AM UTC 24
Finished Aug 24 12:19:00 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375785504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2375785504
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/21.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.817470511
Short name T221
Test name
Test status
Simulation time 7297954127 ps
CPU time 29.97 seconds
Started Aug 24 12:18:57 AM UTC 24
Finished Aug 24 12:19:28 AM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817470511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.817470511
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.71085904
Short name T449
Test name
Test status
Simulation time 81707016 ps
CPU time 4.97 seconds
Started Aug 24 12:17:52 AM UTC 24
Finished Aug 24 12:17:58 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71085904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.71085904
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/21.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.1745750535
Short name T485
Test name
Test status
Simulation time 44592068142 ps
CPU time 910.72 seconds
Started Aug 24 12:19:50 AM UTC 24
Finished Aug 24 12:35:11 AM UTC 24
Peak memory 296064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745750535 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.1745750535
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/21.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.292248056
Short name T64
Test name
Test status
Simulation time 398691461266 ps
CPU time 1450.77 seconds
Started Aug 24 12:20:53 AM UTC 24
Finished Aug 24 12:45:18 AM UTC 24
Peak memory 300520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292248056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.292248056
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/22.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.1110456390
Short name T460
Test name
Test status
Simulation time 2225083575 ps
CPU time 94.09 seconds
Started Aug 24 12:20:36 AM UTC 24
Finished Aug 24 12:22:12 AM UTC 24
Peak memory 263292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110456390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1110456390
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.1043904986
Short name T459
Test name
Test status
Simulation time 1647303833 ps
CPU time 17.6 seconds
Started Aug 24 12:20:33 AM UTC 24
Finished Aug 24 12:20:52 AM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043904986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1043904986
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.859779223
Short name T472
Test name
Test status
Simulation time 6140653320 ps
CPU time 458.38 seconds
Started Aug 24 12:21:18 AM UTC 24
Finished Aug 24 12:29:02 AM UTC 24
Peak memory 279428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859779223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.859779223
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/22.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.3190626252
Short name T532
Test name
Test status
Simulation time 42491572180 ps
CPU time 1777.91 seconds
Started Aug 24 12:22:13 AM UTC 24
Finished Aug 24 12:52:08 AM UTC 24
Peak memory 298472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190626252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3190626252
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.2742289136
Short name T458
Test name
Test status
Simulation time 5572432829 ps
CPU time 33.16 seconds
Started Aug 24 12:20:03 AM UTC 24
Finished Aug 24 12:20:37 AM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742289136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2742289136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.2849016249
Short name T457
Test name
Test status
Simulation time 409066015 ps
CPU time 28.37 seconds
Started Aug 24 12:20:06 AM UTC 24
Finished Aug 24 12:20:36 AM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849016249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2849016249
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/22.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.3908412491
Short name T456
Test name
Test status
Simulation time 821579293 ps
CPU time 33.05 seconds
Started Aug 24 12:19:58 AM UTC 24
Finished Aug 24 12:20:32 AM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908412491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3908412491
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/22.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.1619342989
Short name T292
Test name
Test status
Simulation time 34244990045 ps
CPU time 707.92 seconds
Started Aug 24 12:22:46 AM UTC 24
Finished Aug 24 12:34:42 AM UTC 24
Peak memory 301880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619342989 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.1619342989
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/22.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.3734994844
Short name T125
Test name
Test status
Simulation time 59484430293 ps
CPU time 924.38 seconds
Started Aug 24 12:24:48 AM UTC 24
Finished Aug 24 12:40:22 AM UTC 24
Peak memory 299836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734994844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3734994844
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/23.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.302490980
Short name T465
Test name
Test status
Simulation time 5388336361 ps
CPU time 86.16 seconds
Started Aug 24 12:24:32 AM UTC 24
Finished Aug 24 12:26:01 AM UTC 24
Peak memory 269468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302490980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.302490980
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.1643645112
Short name T464
Test name
Test status
Simulation time 1247125967 ps
CPU time 22.59 seconds
Started Aug 24 12:24:23 AM UTC 24
Finished Aug 24 12:24:47 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643645112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1643645112
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.184319040
Short name T479
Test name
Test status
Simulation time 9804012059 ps
CPU time 463.16 seconds
Started Aug 24 12:25:36 AM UTC 24
Finished Aug 24 12:33:24 AM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184319040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.184319040
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.2296178991
Short name T462
Test name
Test status
Simulation time 101175094 ps
CPU time 8.88 seconds
Started Aug 24 12:24:12 AM UTC 24
Finished Aug 24 12:24:23 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296178991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2296178991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.3290462038
Short name T463
Test name
Test status
Simulation time 402224277 ps
CPU time 13.7 seconds
Started Aug 24 12:24:16 AM UTC 24
Finished Aug 24 12:24:31 AM UTC 24
Peak memory 263260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290462038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3290462038
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/23.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.3290832209
Short name T262
Test name
Test status
Simulation time 405257854 ps
CPU time 20.16 seconds
Started Aug 24 12:24:45 AM UTC 24
Finished Aug 24 12:25:07 AM UTC 24
Peak memory 269080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290832209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3290832209
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.2246220959
Short name T461
Test name
Test status
Simulation time 1686959068 ps
CPU time 38.49 seconds
Started Aug 24 12:23:36 AM UTC 24
Finished Aug 24 12:24:16 AM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246220959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2246220959
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/23.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.3105586226
Short name T61
Test name
Test status
Simulation time 8177084438 ps
CPU time 633.86 seconds
Started Aug 24 12:27:54 AM UTC 24
Finished Aug 24 12:38:35 AM UTC 24
Peak memory 301888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105586226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3105586226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/24.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.2326482570
Short name T470
Test name
Test status
Simulation time 3225308514 ps
CPU time 38.91 seconds
Started Aug 24 12:27:13 AM UTC 24
Finished Aug 24 12:27:54 AM UTC 24
Peak memory 269504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326482570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2326482570
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.641328303
Short name T469
Test name
Test status
Simulation time 671275218 ps
CPU time 31.9 seconds
Started Aug 24 12:27:11 AM UTC 24
Finished Aug 24 12:27:44 AM UTC 24
Peak memory 269052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641328303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.641328303
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.3226304422
Short name T372
Test name
Test status
Simulation time 10855335692 ps
CPU time 563.77 seconds
Started Aug 24 12:28:24 AM UTC 24
Finished Aug 24 12:37:54 AM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226304422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3226304422
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/24.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.2620889419
Short name T524
Test name
Test status
Simulation time 51369540276 ps
CPU time 1154.87 seconds
Started Aug 24 12:29:03 AM UTC 24
Finished Aug 24 12:48:30 AM UTC 24
Peak memory 302284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620889419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2620889419
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.3758214854
Short name T467
Test name
Test status
Simulation time 324753068 ps
CPU time 9.95 seconds
Started Aug 24 12:26:53 AM UTC 24
Finished Aug 24 12:27:04 AM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758214854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3758214854
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.2725922302
Short name T468
Test name
Test status
Simulation time 30166134 ps
CPU time 3.9 seconds
Started Aug 24 12:27:05 AM UTC 24
Finished Aug 24 12:27:10 AM UTC 24
Peak memory 263004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725922302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2725922302
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/24.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.2407389932
Short name T471
Test name
Test status
Simulation time 1144031285 ps
CPU time 16.45 seconds
Started Aug 24 12:27:45 AM UTC 24
Finished Aug 24 12:28:03 AM UTC 24
Peak memory 269408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407389932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2407389932
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.1772137988
Short name T466
Test name
Test status
Simulation time 230338021 ps
CPU time 7.36 seconds
Started Aug 24 12:26:44 AM UTC 24
Finished Aug 24 12:26:52 AM UTC 24
Peak memory 263240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772137988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1772137988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/24.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.2309341076
Short name T293
Test name
Test status
Simulation time 9608353267 ps
CPU time 226.44 seconds
Started Aug 24 12:29:52 AM UTC 24
Finished Aug 24 12:33:42 AM UTC 24
Peak memory 269504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309341076 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.2309341076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/24.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all_with_rand_reset.2432284994
Short name T473
Test name
Test status
Simulation time 3793957283 ps
CPU time 84.67 seconds
Started Aug 24 12:29:52 AM UTC 24
Finished Aug 24 12:31:19 AM UTC 24
Peak memory 279808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2432284994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.a
lert_handler_stress_all_with_rand_reset.2432284994
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.343182274
Short name T555
Test name
Test status
Simulation time 142563927578 ps
CPU time 1635.66 seconds
Started Aug 24 12:31:57 AM UTC 24
Finished Aug 24 12:59:28 AM UTC 24
Peak memory 304680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343182274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.343182274
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/25.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.278041960
Short name T478
Test name
Test status
Simulation time 575939492 ps
CPU time 40.09 seconds
Started Aug 24 12:31:51 AM UTC 24
Finished Aug 24 12:32:32 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278041960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.278041960
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.1231710647
Short name T477
Test name
Test status
Simulation time 3043352659 ps
CPU time 32.53 seconds
Started Aug 24 12:31:39 AM UTC 24
Finished Aug 24 12:32:13 AM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231710647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1231710647
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.828613533
Short name T506
Test name
Test status
Simulation time 14416303822 ps
CPU time 533.99 seconds
Started Aug 24 12:32:14 AM UTC 24
Finished Aug 24 12:41:14 AM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828613533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.828613533
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/25.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.983980563
Short name T569
Test name
Test status
Simulation time 93530647851 ps
CPU time 1977.53 seconds
Started Aug 24 12:32:14 AM UTC 24
Finished Aug 24 01:05:31 AM UTC 24
Peak memory 304200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983980563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.983980563
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.1489928732
Short name T474
Test name
Test status
Simulation time 508489844 ps
CPU time 8.87 seconds
Started Aug 24 12:31:28 AM UTC 24
Finished Aug 24 12:31:38 AM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489928732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1489928732
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.1983424333
Short name T302
Test name
Test status
Simulation time 168236973 ps
CPU time 12.38 seconds
Started Aug 24 12:31:37 AM UTC 24
Finished Aug 24 12:31:50 AM UTC 24
Peak memory 263260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983424333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1983424333
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/25.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.3515731885
Short name T475
Test name
Test status
Simulation time 1242454355 ps
CPU time 28.66 seconds
Started Aug 24 12:31:20 AM UTC 24
Finished Aug 24 12:31:50 AM UTC 24
Peak memory 263240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515731885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3515731885
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/25.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.1231501318
Short name T264
Test name
Test status
Simulation time 26041866318 ps
CPU time 906.71 seconds
Started Aug 24 12:32:33 AM UTC 24
Finished Aug 24 12:47:50 AM UTC 24
Peak memory 301952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231501318 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.1231501318
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/25.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all_with_rand_reset.1407023254
Short name T483
Test name
Test status
Simulation time 2710437998 ps
CPU time 36.51 seconds
Started Aug 24 12:33:06 AM UTC 24
Finished Aug 24 12:33:44 AM UTC 24
Peak memory 281600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1407023254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.a
lert_handler_stress_all_with_rand_reset.1407023254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.1997384847
Short name T301
Test name
Test status
Simulation time 24033104151 ps
CPU time 895.33 seconds
Started Aug 24 12:33:44 AM UTC 24
Finished Aug 24 12:48:48 AM UTC 24
Peak memory 297788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997384847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1997384847
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/26.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.3095720685
Short name T487
Test name
Test status
Simulation time 1740180453 ps
CPU time 101.49 seconds
Started Aug 24 12:33:43 AM UTC 24
Finished Aug 24 12:35:26 AM UTC 24
Peak memory 269248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095720685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3095720685
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.3144919801
Short name T484
Test name
Test status
Simulation time 475647513 ps
CPU time 12.02 seconds
Started Aug 24 12:33:40 AM UTC 24
Finished Aug 24 12:33:53 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144919801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3144919801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.4209136065
Short name T534
Test name
Test status
Simulation time 143791256895 ps
CPU time 1065.29 seconds
Started Aug 24 12:34:18 AM UTC 24
Finished Aug 24 12:52:14 AM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209136065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.4209136065
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.1018851349
Short name T494
Test name
Test status
Simulation time 12554937538 ps
CPU time 250.19 seconds
Started Aug 24 12:33:54 AM UTC 24
Finished Aug 24 12:38:07 AM UTC 24
Peak memory 263052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018851349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1018851349
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.529035746
Short name T481
Test name
Test status
Simulation time 130893948 ps
CPU time 10.16 seconds
Started Aug 24 12:33:27 AM UTC 24
Finished Aug 24 12:33:38 AM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529035746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.529035746
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.604841614
Short name T482
Test name
Test status
Simulation time 761879009 ps
CPU time 13.67 seconds
Started Aug 24 12:33:27 AM UTC 24
Finished Aug 24 12:33:42 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604841614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.604841614
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/26.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.913553170
Short name T218
Test name
Test status
Simulation time 87545657107 ps
CPU time 1417.43 seconds
Started Aug 24 12:34:43 AM UTC 24
Finished Aug 24 12:58:34 AM UTC 24
Peak memory 298528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913553170 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.913553170
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/26.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all_with_rand_reset.1539033864
Short name T281
Test name
Test status
Simulation time 15500664645 ps
CPU time 359.04 seconds
Started Aug 24 12:35:12 AM UTC 24
Finished Aug 24 12:41:15 AM UTC 24
Peak memory 285888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1539033864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.a
lert_handler_stress_all_with_rand_reset.1539033864
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.3366124364
Short name T546
Test name
Test status
Simulation time 26347387535 ps
CPU time 1126.37 seconds
Started Aug 24 12:36:10 AM UTC 24
Finished Aug 24 12:55:08 AM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366124364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3366124364
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/27.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.1497318103
Short name T493
Test name
Test status
Simulation time 5789439751 ps
CPU time 79.61 seconds
Started Aug 24 12:35:58 AM UTC 24
Finished Aug 24 12:37:19 AM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497318103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1497318103
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.4155724074
Short name T490
Test name
Test status
Simulation time 250955884 ps
CPU time 17.65 seconds
Started Aug 24 12:35:38 AM UTC 24
Finished Aug 24 12:35:57 AM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155724074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.4155724074
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.812491500
Short name T356
Test name
Test status
Simulation time 11720479409 ps
CPU time 680.65 seconds
Started Aug 24 12:36:27 AM UTC 24
Finished Aug 24 12:47:55 AM UTC 24
Peak memory 285764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812491500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.812491500
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/27.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.1268783134
Short name T118
Test name
Test status
Simulation time 52329253507 ps
CPU time 2226.33 seconds
Started Aug 24 12:36:52 AM UTC 24
Finished Aug 24 01:14:21 AM UTC 24
Peak memory 304616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268783134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1268783134
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.2696336319
Short name T345
Test name
Test status
Simulation time 31256920343 ps
CPU time 291.29 seconds
Started Aug 24 12:36:24 AM UTC 24
Finished Aug 24 12:41:19 AM UTC 24
Peak memory 263056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696336319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2696336319
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.3958539072
Short name T489
Test name
Test status
Simulation time 480768474 ps
CPU time 9.61 seconds
Started Aug 24 12:35:27 AM UTC 24
Finished Aug 24 12:35:37 AM UTC 24
Peak memory 267072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958539072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3958539072
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.2065194131
Short name T491
Test name
Test status
Simulation time 798178482 ps
CPU time 35.35 seconds
Started Aug 24 12:35:31 AM UTC 24
Finished Aug 24 12:36:07 AM UTC 24
Peak memory 269052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065194131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2065194131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/27.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.4220987984
Short name T60
Test name
Test status
Simulation time 1196979156 ps
CPU time 14.25 seconds
Started Aug 24 12:36:08 AM UTC 24
Finished Aug 24 12:36:23 AM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220987984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.4220987984
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.2768162437
Short name T488
Test name
Test status
Simulation time 185832531 ps
CPU time 4.64 seconds
Started Aug 24 12:35:25 AM UTC 24
Finished Aug 24 12:35:30 AM UTC 24
Peak memory 263240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768162437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2768162437
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/27.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.2379817089
Short name T590
Test name
Test status
Simulation time 44773835298 ps
CPU time 2066.75 seconds
Started Aug 24 12:37:21 AM UTC 24
Finished Aug 24 01:12:07 AM UTC 24
Peak memory 314844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379817089 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.2379817089
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/27.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all_with_rand_reset.2862187592
Short name T499
Test name
Test status
Simulation time 692701918 ps
CPU time 59.12 seconds
Started Aug 24 12:37:55 AM UTC 24
Finished Aug 24 12:38:56 AM UTC 24
Peak memory 279416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2862187592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.a
lert_handler_stress_all_with_rand_reset.2862187592
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.2014166436
Short name T587
Test name
Test status
Simulation time 338837568140 ps
CPU time 1938.77 seconds
Started Aug 24 12:38:47 AM UTC 24
Finished Aug 24 01:11:25 AM UTC 24
Peak memory 304612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014166436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2014166436
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/28.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.3661346982
Short name T503
Test name
Test status
Simulation time 3041610100 ps
CPU time 140.66 seconds
Started Aug 24 12:38:30 AM UTC 24
Finished Aug 24 12:40:54 AM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661346982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3661346982
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.10650043
Short name T498
Test name
Test status
Simulation time 713524530 ps
CPU time 19.9 seconds
Started Aug 24 12:38:25 AM UTC 24
Finished Aug 24 12:38:47 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10650043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc
_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.10650043
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.4029980244
Short name T574
Test name
Test status
Simulation time 145077891210 ps
CPU time 1609.78 seconds
Started Aug 24 12:39:29 AM UTC 24
Finished Aug 24 01:06:35 AM UTC 24
Peak memory 288240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029980244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.4029980244
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.1580426161
Short name T501
Test name
Test status
Simulation time 27577151780 ps
CPU time 82 seconds
Started Aug 24 12:38:55 AM UTC 24
Finished Aug 24 12:40:19 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580426161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1580426161
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.1610559874
Short name T497
Test name
Test status
Simulation time 1668392075 ps
CPU time 19.81 seconds
Started Aug 24 12:38:08 AM UTC 24
Finished Aug 24 12:38:29 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610559874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1610559874
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.2609209969
Short name T496
Test name
Test status
Simulation time 742614042 ps
CPU time 10.08 seconds
Started Aug 24 12:38:13 AM UTC 24
Finished Aug 24 12:38:24 AM UTC 24
Peak memory 263260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609209969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2609209969
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/28.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.501621780
Short name T495
Test name
Test status
Simulation time 51238002 ps
CPU time 2.54 seconds
Started Aug 24 12:38:08 AM UTC 24
Finished Aug 24 12:38:12 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501621780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.501621780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/28.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.3302683177
Short name T580
Test name
Test status
Simulation time 79824933646 ps
CPU time 1731.78 seconds
Started Aug 24 12:41:15 AM UTC 24
Finished Aug 24 01:10:24 AM UTC 24
Peak memory 302560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302683177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3302683177
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/29.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.1057482785
Short name T508
Test name
Test status
Simulation time 1412594542 ps
CPU time 26.21 seconds
Started Aug 24 12:41:09 AM UTC 24
Finished Aug 24 12:41:36 AM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057482785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1057482785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.4162280867
Short name T507
Test name
Test status
Simulation time 385139984 ps
CPU time 12.74 seconds
Started Aug 24 12:41:04 AM UTC 24
Finished Aug 24 12:41:17 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162280867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.4162280867
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.3189670963
Short name T593
Test name
Test status
Simulation time 424762184081 ps
CPU time 1885.9 seconds
Started Aug 24 12:41:20 AM UTC 24
Finished Aug 24 01:13:04 AM UTC 24
Peak memory 304688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189670963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3189670963
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.3657489205
Short name T342
Test name
Test status
Simulation time 174185715561 ps
CPU time 342.09 seconds
Started Aug 24 12:41:16 AM UTC 24
Finished Aug 24 12:47:02 AM UTC 24
Peak memory 263244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657489205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3657489205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.2168374995
Short name T505
Test name
Test status
Simulation time 743040398 ps
CPU time 29.88 seconds
Started Aug 24 12:40:36 AM UTC 24
Finished Aug 24 12:41:07 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168374995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2168374995
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.2333722282
Short name T504
Test name
Test status
Simulation time 128280169 ps
CPU time 7.72 seconds
Started Aug 24 12:40:54 AM UTC 24
Finished Aug 24 12:41:03 AM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333722282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2333722282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/29.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.1016891275
Short name T502
Test name
Test status
Simulation time 2921958843 ps
CPU time 10.21 seconds
Started Aug 24 12:40:24 AM UTC 24
Finished Aug 24 12:40:36 AM UTC 24
Peak memory 267400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016891275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1016891275
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/29.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.1541415742
Short name T509
Test name
Test status
Simulation time 1897202205 ps
CPU time 28.78 seconds
Started Aug 24 12:41:37 AM UTC 24
Finished Aug 24 12:42:07 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541415742 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.1541415742
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/29.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all_with_rand_reset.3458156012
Short name T95
Test name
Test status
Simulation time 775447119 ps
CPU time 57.13 seconds
Started Aug 24 12:42:03 AM UTC 24
Finished Aug 24 12:43:02 AM UTC 24
Peak memory 279740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3458156012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.a
lert_handler_stress_all_with_rand_reset.3458156012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.3275170147
Short name T82
Test name
Test status
Simulation time 31964046 ps
CPU time 2.43 seconds
Started Aug 23 11:31:41 PM UTC 24
Finished Aug 23 11:31:44 PM UTC 24
Peak memory 263500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275170147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3275170147
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.3371284100
Short name T21
Test name
Test status
Simulation time 1311158430 ps
CPU time 14.52 seconds
Started Aug 23 11:31:36 PM UTC 24
Finished Aug 23 11:31:52 PM UTC 24
Peak memory 263268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371284100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3371284100
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.3741081654
Short name T24
Test name
Test status
Simulation time 9452896149 ps
CPU time 108.17 seconds
Started Aug 23 11:31:20 PM UTC 24
Finished Aug 23 11:33:10 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741081654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3741081654
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.1871650655
Short name T83
Test name
Test status
Simulation time 895862357 ps
CPU time 38.23 seconds
Started Aug 23 11:31:19 PM UTC 24
Finished Aug 23 11:31:59 PM UTC 24
Peak memory 269052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871650655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1871650655
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.1576041601
Short name T317
Test name
Test status
Simulation time 25989233769 ps
CPU time 1159.06 seconds
Started Aug 23 11:31:32 PM UTC 24
Finished Aug 23 11:51:03 PM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576041601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1576041601
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.4242644521
Short name T96
Test name
Test status
Simulation time 76165630034 ps
CPU time 988.47 seconds
Started Aug 23 11:31:35 PM UTC 24
Finished Aug 23 11:48:14 PM UTC 24
Peak memory 301960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242644521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.4242644521
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.3488610217
Short name T20
Test name
Test status
Simulation time 7228406054 ps
CPU time 217.42 seconds
Started Aug 23 11:31:30 PM UTC 24
Finished Aug 23 11:35:11 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488610217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3488610217
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.3009430564
Short name T92
Test name
Test status
Simulation time 737236593 ps
CPU time 32.14 seconds
Started Aug 23 11:31:14 PM UTC 24
Finished Aug 23 11:31:47 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009430564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3009430564
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.1605140874
Short name T33
Test name
Test status
Simulation time 4639790613 ps
CPU time 49.06 seconds
Started Aug 23 11:31:16 PM UTC 24
Finished Aug 23 11:32:06 PM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605140874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1605140874
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.3829341365
Short name T42
Test name
Test status
Simulation time 3737717095 ps
CPU time 18.77 seconds
Started Aug 23 11:31:47 PM UTC 24
Finished Aug 23 11:32:07 PM UTC 24
Peak memory 297400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829341365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3829341365
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.2718263018
Short name T41
Test name
Test status
Simulation time 248823979 ps
CPU time 12.11 seconds
Started Aug 23 11:31:21 PM UTC 24
Finished Aug 23 11:31:34 PM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718263018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2718263018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.343430750
Short name T78
Test name
Test status
Simulation time 2319617550 ps
CPU time 27.24 seconds
Started Aug 23 11:31:12 PM UTC 24
Finished Aug 23 11:31:40 PM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343430750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.343430750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.1397491009
Short name T46
Test name
Test status
Simulation time 400157979 ps
CPU time 16.82 seconds
Started Aug 23 11:31:36 PM UTC 24
Finished Aug 23 11:31:54 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397491009 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.1397491009
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/3.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.374084972
Short name T602
Test name
Test status
Simulation time 255794044127 ps
CPU time 2043.69 seconds
Started Aug 24 12:43:14 AM UTC 24
Finished Aug 24 01:17:38 AM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374084972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.374084972
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/30.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.2822582384
Short name T514
Test name
Test status
Simulation time 671489730 ps
CPU time 10.69 seconds
Started Aug 24 12:43:02 AM UTC 24
Finished Aug 24 12:43:14 AM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822582384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2822582384
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.3030472063
Short name T512
Test name
Test status
Simulation time 976589590 ps
CPU time 27.08 seconds
Started Aug 24 12:42:44 AM UTC 24
Finished Aug 24 12:43:12 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030472063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3030472063
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.2785292492
Short name T362
Test name
Test status
Simulation time 150844396127 ps
CPU time 1954.9 seconds
Started Aug 24 12:43:25 AM UTC 24
Finished Aug 24 01:16:20 AM UTC 24
Peak memory 304680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785292492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2785292492
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/30.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.2163170228
Short name T558
Test name
Test status
Simulation time 23480562176 ps
CPU time 919.8 seconds
Started Aug 24 12:44:20 AM UTC 24
Finished Aug 24 12:59:49 AM UTC 24
Peak memory 285512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163170228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2163170228
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.645367432
Short name T343
Test name
Test status
Simulation time 11516481098 ps
CPU time 338.67 seconds
Started Aug 24 12:43:14 AM UTC 24
Finished Aug 24 12:48:57 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645367432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.645367432
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.770252848
Short name T511
Test name
Test status
Simulation time 4412548167 ps
CPU time 34.43 seconds
Started Aug 24 12:42:08 AM UTC 24
Finished Aug 24 12:42:44 AM UTC 24
Peak memory 262960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770252848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.770252848
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.3631071720
Short name T513
Test name
Test status
Simulation time 1042855928 ps
CPU time 34.11 seconds
Started Aug 24 12:42:38 AM UTC 24
Finished Aug 24 12:43:14 AM UTC 24
Peak memory 262936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631071720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3631071720
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/30.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.2145571521
Short name T280
Test name
Test status
Simulation time 215878788 ps
CPU time 9.48 seconds
Started Aug 24 12:43:13 AM UTC 24
Finished Aug 24 12:43:24 AM UTC 24
Peak memory 269408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145571521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2145571521
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.4225759979
Short name T510
Test name
Test status
Simulation time 700317426 ps
CPU time 33.13 seconds
Started Aug 24 12:42:03 AM UTC 24
Finished Aug 24 12:42:37 AM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225759979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.4225759979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/30.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.1264711062
Short name T516
Test name
Test status
Simulation time 6997848719 ps
CPU time 24.54 seconds
Started Aug 24 12:44:51 AM UTC 24
Finished Aug 24 12:45:17 AM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264711062 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.1264711062
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/30.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all_with_rand_reset.1707441046
Short name T529
Test name
Test status
Simulation time 13072649884 ps
CPU time 320.49 seconds
Started Aug 24 12:45:18 AM UTC 24
Finished Aug 24 12:50:43 AM UTC 24
Peak memory 283576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1707441046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.a
lert_handler_stress_all_with_rand_reset.1707441046
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.2666012498
Short name T575
Test name
Test status
Simulation time 53948837309 ps
CPU time 1204.85 seconds
Started Aug 24 12:46:39 AM UTC 24
Finished Aug 24 01:06:56 AM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666012498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2666012498
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/31.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.3756551246
Short name T522
Test name
Test status
Simulation time 1425147549 ps
CPU time 19.7 seconds
Started Aug 24 12:46:18 AM UTC 24
Finished Aug 24 12:46:39 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756551246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3756551246
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.3418728123
Short name T520
Test name
Test status
Simulation time 123536262 ps
CPU time 4.8 seconds
Started Aug 24 12:46:11 AM UTC 24
Finished Aug 24 12:46:17 AM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418728123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3418728123
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.3356460730
Short name T360
Test name
Test status
Simulation time 23061477263 ps
CPU time 913.22 seconds
Started Aug 24 12:47:03 AM UTC 24
Finished Aug 24 01:02:26 AM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356460730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3356460730
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/31.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.4180938686
Short name T335
Test name
Test status
Simulation time 12704841120 ps
CPU time 382.3 seconds
Started Aug 24 12:46:43 AM UTC 24
Finished Aug 24 12:53:09 AM UTC 24
Peak memory 262984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180938686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.4180938686
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.2480548777
Short name T519
Test name
Test status
Simulation time 1405421146 ps
CPU time 31.2 seconds
Started Aug 24 12:45:37 AM UTC 24
Finished Aug 24 12:46:10 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480548777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2480548777
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.2635417468
Short name T521
Test name
Test status
Simulation time 1616913583 ps
CPU time 35.42 seconds
Started Aug 24 12:45:55 AM UTC 24
Finished Aug 24 12:46:32 AM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635417468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2635417468
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/31.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.2312448174
Short name T523
Test name
Test status
Simulation time 384222731 ps
CPU time 9.09 seconds
Started Aug 24 12:46:32 AM UTC 24
Finished Aug 24 12:46:42 AM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312448174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2312448174
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.3424729909
Short name T517
Test name
Test status
Simulation time 631284906 ps
CPU time 14.41 seconds
Started Aug 24 12:45:20 AM UTC 24
Finished Aug 24 12:45:36 AM UTC 24
Peak memory 269448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424729909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3424729909
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/31.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.273273908
Short name T658
Test name
Test status
Simulation time 219271038112 ps
CPU time 2608.25 seconds
Started Aug 24 12:47:52 AM UTC 24
Finished Aug 24 01:31:45 AM UTC 24
Peak memory 320980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273273908 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.273273908
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/31.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all_with_rand_reset.1388013116
Short name T536
Test name
Test status
Simulation time 3151426264 ps
CPU time 266.37 seconds
Started Aug 24 12:47:56 AM UTC 24
Finished Aug 24 12:52:26 AM UTC 24
Peak memory 281600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1388013116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.a
lert_handler_stress_all_with_rand_reset.1388013116
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.1796611797
Short name T603
Test name
Test status
Simulation time 34764781393 ps
CPU time 1709.63 seconds
Started Aug 24 12:49:07 AM UTC 24
Finished Aug 24 01:17:54 AM UTC 24
Peak memory 304684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796611797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1796611797
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/32.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.3738325546
Short name T530
Test name
Test status
Simulation time 1932728997 ps
CPU time 123.32 seconds
Started Aug 24 12:49:03 AM UTC 24
Finished Aug 24 12:51:08 AM UTC 24
Peak memory 269040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738325546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3738325546
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.1843992568
Short name T525
Test name
Test status
Simulation time 170256152 ps
CPU time 3.21 seconds
Started Aug 24 12:48:58 AM UTC 24
Finished Aug 24 12:49:02 AM UTC 24
Peak memory 252732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843992568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1843992568
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.2341320591
Short name T568
Test name
Test status
Simulation time 56062752298 ps
CPU time 915.47 seconds
Started Aug 24 12:49:46 AM UTC 24
Finished Aug 24 01:05:11 AM UTC 24
Peak memory 301968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341320591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2341320591
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.1118268382
Short name T541
Test name
Test status
Simulation time 37310813315 ps
CPU time 310.24 seconds
Started Aug 24 12:49:09 AM UTC 24
Finished Aug 24 12:54:23 AM UTC 24
Peak memory 263052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118268382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1118268382
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.3237624140
Short name T527
Test name
Test status
Simulation time 3171170622 ps
CPU time 33.17 seconds
Started Aug 24 12:48:32 AM UTC 24
Finished Aug 24 12:49:06 AM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237624140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3237624140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.2921496280
Short name T526
Test name
Test status
Simulation time 165579346 ps
CPU time 11.15 seconds
Started Aug 24 12:48:51 AM UTC 24
Finished Aug 24 12:49:03 AM UTC 24
Peak memory 262932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921496280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2921496280
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/32.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.3304786531
Short name T528
Test name
Test status
Simulation time 975931889 ps
CPU time 39.62 seconds
Started Aug 24 12:48:27 AM UTC 24
Finished Aug 24 12:49:09 AM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304786531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3304786531
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/32.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.4105762896
Short name T584
Test name
Test status
Simulation time 36605739456 ps
CPU time 1202.76 seconds
Started Aug 24 12:50:44 AM UTC 24
Finished Aug 24 01:10:58 AM UTC 24
Peak memory 301952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105762896 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.4105762896
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/32.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all_with_rand_reset.594332006
Short name T539
Test name
Test status
Simulation time 2638552952 ps
CPU time 122 seconds
Started Aug 24 12:51:10 AM UTC 24
Finished Aug 24 12:53:14 AM UTC 24
Peak memory 279808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=594332006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.al
ert_handler_stress_all_with_rand_reset.594332006
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/33.alert_handler_entropy.949140715
Short name T563
Test name
Test status
Simulation time 18808838796 ps
CPU time 642.7 seconds
Started Aug 24 12:52:27 AM UTC 24
Finished Aug 24 01:03:17 AM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949140715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.949140715
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/33.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.912563172
Short name T540
Test name
Test status
Simulation time 6834084889 ps
CPU time 107.15 seconds
Started Aug 24 12:52:16 AM UTC 24
Finished Aug 24 12:54:05 AM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912563172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.912563172
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.1588939594
Short name T537
Test name
Test status
Simulation time 433906460 ps
CPU time 24.3 seconds
Started Aug 24 12:52:16 AM UTC 24
Finished Aug 24 12:52:41 AM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588939594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1588939594
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.885063104
Short name T369
Test name
Test status
Simulation time 330907695155 ps
CPU time 1181.76 seconds
Started Aug 24 12:52:53 AM UTC 24
Finished Aug 24 01:12:47 AM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885063104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.885063104
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/33.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.1164538012
Short name T671
Test name
Test status
Simulation time 230559264947 ps
CPU time 2559.39 seconds
Started Aug 24 12:53:10 AM UTC 24
Finished Aug 24 01:36:14 AM UTC 24
Peak memory 304616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164538012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1164538012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.4254553572
Short name T549
Test name
Test status
Simulation time 15862233660 ps
CPU time 245.13 seconds
Started Aug 24 12:52:42 AM UTC 24
Finished Aug 24 12:56:50 AM UTC 24
Peak memory 263052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254553572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.4254553572
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.2580692520
Short name T535
Test name
Test status
Simulation time 3751076322 ps
CPU time 40 seconds
Started Aug 24 12:51:39 AM UTC 24
Finished Aug 24 12:52:21 AM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580692520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2580692520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.2350344040
Short name T533
Test name
Test status
Simulation time 18969071 ps
CPU time 2.73 seconds
Started Aug 24 12:52:10 AM UTC 24
Finished Aug 24 12:52:14 AM UTC 24
Peak memory 252992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350344040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2350344040
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/33.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.2459669024
Short name T538
Test name
Test status
Simulation time 606529772 ps
CPU time 29.78 seconds
Started Aug 24 12:52:22 AM UTC 24
Finished Aug 24 12:52:53 AM UTC 24
Peak memory 269344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459669024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2459669024
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.175995711
Short name T531
Test name
Test status
Simulation time 1299386238 ps
CPU time 26.94 seconds
Started Aug 24 12:51:10 AM UTC 24
Finished Aug 24 12:51:38 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175995711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.175995711
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/33.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.2247317060
Short name T104
Test name
Test status
Simulation time 157125321774 ps
CPU time 1803.7 seconds
Started Aug 24 12:53:15 AM UTC 24
Finished Aug 24 01:23:36 AM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247317060 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.2247317060
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/33.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all_with_rand_reset.2293453373
Short name T547
Test name
Test status
Simulation time 7352880879 ps
CPU time 136.41 seconds
Started Aug 24 12:53:24 AM UTC 24
Finished Aug 24 12:55:43 AM UTC 24
Peak memory 279812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2293453373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.a
lert_handler_stress_all_with_rand_reset.2293453373
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.2734750156
Short name T583
Test name
Test status
Simulation time 25143657081 ps
CPU time 929.58 seconds
Started Aug 24 12:55:06 AM UTC 24
Finished Aug 24 01:10:46 AM UTC 24
Peak memory 298120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734750156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2734750156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/34.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.1936889750
Short name T548
Test name
Test status
Simulation time 2116630865 ps
CPU time 95.4 seconds
Started Aug 24 12:54:52 AM UTC 24
Finished Aug 24 12:56:29 AM UTC 24
Peak memory 269244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936889750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1936889750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.2614634973
Short name T545
Test name
Test status
Simulation time 423429044 ps
CPU time 8.25 seconds
Started Aug 24 12:54:44 AM UTC 24
Finished Aug 24 12:54:53 AM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614634973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2614634973
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.3990579986
Short name T660
Test name
Test status
Simulation time 209565572210 ps
CPU time 2107.89 seconds
Started Aug 24 12:56:30 AM UTC 24
Finished Aug 24 01:31:58 AM UTC 24
Peak memory 304692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990579986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3990579986
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.1949623265
Short name T554
Test name
Test status
Simulation time 8179678277 ps
CPU time 239.95 seconds
Started Aug 24 12:55:09 AM UTC 24
Finished Aug 24 12:59:12 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949623265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1949623265
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.439347830
Short name T542
Test name
Test status
Simulation time 224431112 ps
CPU time 17.12 seconds
Started Aug 24 12:54:23 AM UTC 24
Finished Aug 24 12:54:42 AM UTC 24
Peak memory 263224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439347830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.439347830
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.3502429419
Short name T544
Test name
Test status
Simulation time 363373435 ps
CPU time 7.6 seconds
Started Aug 24 12:54:43 AM UTC 24
Finished Aug 24 12:54:51 AM UTC 24
Peak memory 262932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502429419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3502429419
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/34.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.2389790187
Short name T283
Test name
Test status
Simulation time 407130001 ps
CPU time 9.99 seconds
Started Aug 24 12:54:54 AM UTC 24
Finished Aug 24 12:55:05 AM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389790187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2389790187
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.56036603
Short name T543
Test name
Test status
Simulation time 809076278 ps
CPU time 36.01 seconds
Started Aug 24 12:54:05 AM UTC 24
Finished Aug 24 12:54:43 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56036603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.56036603
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/34.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.2855411071
Short name T550
Test name
Test status
Simulation time 1653620008 ps
CPU time 67.73 seconds
Started Aug 24 12:56:51 AM UTC 24
Finished Aug 24 12:58:00 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855411071 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.2855411071
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/34.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all_with_rand_reset.3534160901
Short name T561
Test name
Test status
Simulation time 3437422100 ps
CPU time 317.88 seconds
Started Aug 24 12:57:47 AM UTC 24
Finished Aug 24 01:03:09 AM UTC 24
Peak memory 285624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3534160901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.a
lert_handler_stress_all_with_rand_reset.3534160901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.4248389495
Short name T611
Test name
Test status
Simulation time 60980539331 ps
CPU time 1274.42 seconds
Started Aug 24 12:59:29 AM UTC 24
Finished Aug 24 01:20:57 AM UTC 24
Peak memory 304936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248389495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.4248389495
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/35.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.3669402415
Short name T559
Test name
Test status
Simulation time 27411260736 ps
CPU time 190.97 seconds
Started Aug 24 12:58:58 AM UTC 24
Finished Aug 24 01:02:11 AM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669402415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3669402415
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.2700381033
Short name T557
Test name
Test status
Simulation time 1015175752 ps
CPU time 46.59 seconds
Started Aug 24 12:58:55 AM UTC 24
Finished Aug 24 12:59:43 AM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700381033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2700381033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.2712994407
Short name T651
Test name
Test status
Simulation time 182768537504 ps
CPU time 1807.63 seconds
Started Aug 24 12:59:44 AM UTC 24
Finished Aug 24 01:30:09 AM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712994407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2712994407
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/35.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.3728796334
Short name T631
Test name
Test status
Simulation time 137602269036 ps
CPU time 1539.27 seconds
Started Aug 24 12:59:50 AM UTC 24
Finished Aug 24 01:25:44 AM UTC 24
Peak memory 300516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728796334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3728796334
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.2433232358
Short name T560
Test name
Test status
Simulation time 6643735275 ps
CPU time 212.06 seconds
Started Aug 24 12:59:35 AM UTC 24
Finished Aug 24 01:03:09 AM UTC 24
Peak memory 263056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433232358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2433232358
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.2564971296
Short name T552
Test name
Test status
Simulation time 5787864153 ps
CPU time 17.4 seconds
Started Aug 24 12:58:35 AM UTC 24
Finished Aug 24 12:58:54 AM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564971296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2564971296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.4083936680
Short name T553
Test name
Test status
Simulation time 658216536 ps
CPU time 13.97 seconds
Started Aug 24 12:58:41 AM UTC 24
Finished Aug 24 12:58:57 AM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083936680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.4083936680
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/35.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.290742936
Short name T556
Test name
Test status
Simulation time 223293923 ps
CPU time 18.84 seconds
Started Aug 24 12:59:14 AM UTC 24
Finished Aug 24 12:59:34 AM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290742936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.290742936
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.1176994860
Short name T551
Test name
Test status
Simulation time 1822260768 ps
CPU time 37.34 seconds
Started Aug 24 12:58:02 AM UTC 24
Finished Aug 24 12:58:40 AM UTC 24
Peak memory 269320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176994860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1176994860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/35.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.1850977881
Short name T622
Test name
Test status
Simulation time 36963111012 ps
CPU time 1272.21 seconds
Started Aug 24 01:02:13 AM UTC 24
Finished Aug 24 01:23:38 AM UTC 24
Peak memory 302212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850977881 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.1850977881
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/35.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.1953275129
Short name T595
Test name
Test status
Simulation time 33040101271 ps
CPU time 585.99 seconds
Started Aug 24 01:03:43 AM UTC 24
Finished Aug 24 01:13:36 AM UTC 24
Peak memory 283528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953275129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1953275129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/36.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.2032206032
Short name T567
Test name
Test status
Simulation time 708818141 ps
CPU time 39.53 seconds
Started Aug 24 01:03:18 AM UTC 24
Finished Aug 24 01:03:59 AM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032206032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2032206032
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.443167023
Short name T565
Test name
Test status
Simulation time 740414709 ps
CPU time 35.18 seconds
Started Aug 24 01:03:17 AM UTC 24
Finished Aug 24 01:03:53 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443167023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.443167023
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg.814810360
Short name T364
Test name
Test status
Simulation time 39300190041 ps
CPU time 1070.2 seconds
Started Aug 24 01:03:55 AM UTC 24
Finished Aug 24 01:21:55 AM UTC 24
Peak memory 299832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814810360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.814810360
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/36.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.3212885249
Short name T303
Test name
Test status
Simulation time 37152951639 ps
CPU time 1565.13 seconds
Started Aug 24 01:04:00 AM UTC 24
Finished Aug 24 01:30:20 AM UTC 24
Peak memory 300520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212885249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3212885249
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.3524747214
Short name T341
Test name
Test status
Simulation time 84009871892 ps
CPU time 253.4 seconds
Started Aug 24 01:03:55 AM UTC 24
Finished Aug 24 01:08:11 AM UTC 24
Peak memory 263056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524747214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3524747214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.2569330670
Short name T566
Test name
Test status
Simulation time 4511228955 ps
CPU time 41.21 seconds
Started Aug 24 01:03:10 AM UTC 24
Finished Aug 24 01:03:53 AM UTC 24
Peak memory 269504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569330670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2569330670
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.490533765
Short name T562
Test name
Test status
Simulation time 268455378 ps
CPU time 4.37 seconds
Started Aug 24 01:03:10 AM UTC 24
Finished Aug 24 01:03:16 AM UTC 24
Peak memory 252992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490533765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.490533765
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/36.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.3012209041
Short name T564
Test name
Test status
Simulation time 4193534422 ps
CPU time 38.94 seconds
Started Aug 24 01:03:02 AM UTC 24
Finished Aug 24 01:03:42 AM UTC 24
Peak memory 269192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012209041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3012209041
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/36.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.2285710877
Short name T642
Test name
Test status
Simulation time 31927627830 ps
CPU time 1387.23 seconds
Started Aug 24 01:04:21 AM UTC 24
Finished Aug 24 01:27:42 AM UTC 24
Peak memory 304676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285710877 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.2285710877
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/36.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.3844922708
Short name T609
Test name
Test status
Simulation time 18374387910 ps
CPU time 840.07 seconds
Started Aug 24 01:06:36 AM UTC 24
Finished Aug 24 01:20:45 AM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844922708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3844922708
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/37.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.2330519456
Short name T576
Test name
Test status
Simulation time 5578751970 ps
CPU time 62.01 seconds
Started Aug 24 01:06:17 AM UTC 24
Finished Aug 24 01:07:21 AM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330519456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2330519456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.3365008696
Short name T573
Test name
Test status
Simulation time 44375606 ps
CPU time 3.22 seconds
Started Aug 24 01:06:12 AM UTC 24
Finished Aug 24 01:06:16 AM UTC 24
Peak memory 252732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365008696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3365008696
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.3861850775
Short name T633
Test name
Test status
Simulation time 56814933537 ps
CPU time 1125.56 seconds
Started Aug 24 01:06:57 AM UTC 24
Finished Aug 24 01:25:53 AM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861850775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3861850775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/37.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.2706128365
Short name T637
Test name
Test status
Simulation time 152552319385 ps
CPU time 1144.76 seconds
Started Aug 24 01:07:22 AM UTC 24
Finished Aug 24 01:26:38 AM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706128365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2706128365
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.1870671609
Short name T582
Test name
Test status
Simulation time 7895073089 ps
CPU time 239.48 seconds
Started Aug 24 01:06:41 AM UTC 24
Finished Aug 24 01:10:43 AM UTC 24
Peak memory 263376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870671609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1870671609
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.3084278917
Short name T572
Test name
Test status
Simulation time 917996735 ps
CPU time 41.59 seconds
Started Aug 24 01:05:33 AM UTC 24
Finished Aug 24 01:06:16 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084278917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3084278917
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.744601519
Short name T571
Test name
Test status
Simulation time 77490034 ps
CPU time 5.13 seconds
Started Aug 24 01:06:05 AM UTC 24
Finished Aug 24 01:06:11 AM UTC 24
Peak memory 252664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744601519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.744601519
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/37.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.262183852
Short name T570
Test name
Test status
Simulation time 1528008511 ps
CPU time 34.8 seconds
Started Aug 24 01:05:28 AM UTC 24
Finished Aug 24 01:06:04 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262183852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.262183852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/37.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.1094463076
Short name T610
Test name
Test status
Simulation time 73309590145 ps
CPU time 752.41 seconds
Started Aug 24 01:08:12 AM UTC 24
Finished Aug 24 01:20:53 AM UTC 24
Peak memory 302208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094463076 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.1094463076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/37.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.4241054206
Short name T652
Test name
Test status
Simulation time 26924188712 ps
CPU time 1172.01 seconds
Started Aug 24 01:10:26 AM UTC 24
Finished Aug 24 01:30:10 AM UTC 24
Peak memory 288300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241054206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.4241054206
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/38.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.2422588794
Short name T586
Test name
Test status
Simulation time 4796412951 ps
CPU time 74.85 seconds
Started Aug 24 01:10:01 AM UTC 24
Finished Aug 24 01:11:18 AM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422588794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2422588794
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.1614444173
Short name T581
Test name
Test status
Simulation time 5145741448 ps
CPU time 25.16 seconds
Started Aug 24 01:09:59 AM UTC 24
Finished Aug 24 01:10:25 AM UTC 24
Peak memory 269500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614444173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1614444173
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.1870390299
Short name T632
Test name
Test status
Simulation time 24924370481 ps
CPU time 891.49 seconds
Started Aug 24 01:10:47 AM UTC 24
Finished Aug 24 01:25:48 AM UTC 24
Peak memory 295812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870390299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1870390299
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/38.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.2362572627
Short name T684
Test name
Test status
Simulation time 78349371292 ps
CPU time 1665.83 seconds
Started Aug 24 01:11:00 AM UTC 24
Finished Aug 24 01:39:02 AM UTC 24
Peak memory 300520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362572627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2362572627
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.674324142
Short name T604
Test name
Test status
Simulation time 14378886080 ps
CPU time 429.09 seconds
Started Aug 24 01:10:44 AM UTC 24
Finished Aug 24 01:17:58 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674324142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.674324142
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.147657555
Short name T578
Test name
Test status
Simulation time 749150879 ps
CPU time 29.36 seconds
Started Aug 24 01:09:05 AM UTC 24
Finished Aug 24 01:09:35 AM UTC 24
Peak memory 263224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147657555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.147657555
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.2111673023
Short name T579
Test name
Test status
Simulation time 1184319541 ps
CPU time 20.65 seconds
Started Aug 24 01:09:36 AM UTC 24
Finished Aug 24 01:09:58 AM UTC 24
Peak memory 263004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111673023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2111673023
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/38.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.3073957269
Short name T585
Test name
Test status
Simulation time 6415451100 ps
CPU time 39.88 seconds
Started Aug 24 01:10:25 AM UTC 24
Finished Aug 24 01:11:06 AM UTC 24
Peak memory 263072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073957269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3073957269
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.4219684212
Short name T577
Test name
Test status
Simulation time 460820811 ps
CPU time 6.57 seconds
Started Aug 24 01:08:57 AM UTC 24
Finished Aug 24 01:09:04 AM UTC 24
Peak memory 269448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219684212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.4219684212
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/38.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.3943920818
Short name T596
Test name
Test status
Simulation time 18157565243 ps
CPU time 147.66 seconds
Started Aug 24 01:11:07 AM UTC 24
Finished Aug 24 01:13:37 AM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943920818 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.3943920818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/38.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all_with_rand_reset.529823337
Short name T594
Test name
Test status
Simulation time 8114008847 ps
CPU time 109.85 seconds
Started Aug 24 01:11:18 AM UTC 24
Finished Aug 24 01:13:10 AM UTC 24
Peak memory 285620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=529823337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.al
ert_handler_stress_all_with_rand_reset.529823337
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.467807109
Short name T699
Test name
Test status
Simulation time 184337103242 ps
CPU time 1967.99 seconds
Started Aug 24 01:12:25 AM UTC 24
Finished Aug 24 01:45:31 AM UTC 24
Peak memory 304940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467807109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.467807109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/39.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.2850663292
Short name T601
Test name
Test status
Simulation time 29209421643 ps
CPU time 252.73 seconds
Started Aug 24 01:12:09 AM UTC 24
Finished Aug 24 01:16:25 AM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850663292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2850663292
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.4219984036
Short name T592
Test name
Test status
Simulation time 2182623371 ps
CPU time 25.08 seconds
Started Aug 24 01:11:57 AM UTC 24
Finished Aug 24 01:12:24 AM UTC 24
Peak memory 262964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219984036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.4219984036
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.3714106314
Short name T615
Test name
Test status
Simulation time 27806239242 ps
CPU time 504.68 seconds
Started Aug 24 01:12:48 AM UTC 24
Finished Aug 24 01:21:19 AM UTC 24
Peak memory 285320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714106314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3714106314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/39.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.3318385046
Short name T670
Test name
Test status
Simulation time 61705253944 ps
CPU time 1366.18 seconds
Started Aug 24 01:13:05 AM UTC 24
Finished Aug 24 01:36:05 AM UTC 24
Peak memory 298472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318385046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3318385046
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.1188570615
Short name T336
Test name
Test status
Simulation time 46319721678 ps
CPU time 342.3 seconds
Started Aug 24 01:12:48 AM UTC 24
Finished Aug 24 01:18:35 AM UTC 24
Peak memory 262992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188570615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1188570615
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.2168853144
Short name T591
Test name
Test status
Simulation time 1994523938 ps
CPU time 44.26 seconds
Started Aug 24 01:11:30 AM UTC 24
Finished Aug 24 01:12:16 AM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168853144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2168853144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.3214691533
Short name T589
Test name
Test status
Simulation time 251714490 ps
CPU time 19.66 seconds
Started Aug 24 01:11:35 AM UTC 24
Finished Aug 24 01:11:56 AM UTC 24
Peak memory 269052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214691533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3214691533
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/39.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.3101391566
Short name T588
Test name
Test status
Simulation time 148073148 ps
CPU time 7.03 seconds
Started Aug 24 01:11:26 AM UTC 24
Finished Aug 24 01:11:34 AM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101391566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3101391566
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/39.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.1785406444
Short name T659
Test name
Test status
Simulation time 62666643332 ps
CPU time 1107.39 seconds
Started Aug 24 01:13:11 AM UTC 24
Finished Aug 24 01:31:50 AM UTC 24
Peak memory 301952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785406444 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.1785406444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/39.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.1292255346
Short name T68
Test name
Test status
Simulation time 123295563 ps
CPU time 2.56 seconds
Started Aug 23 11:32:18 PM UTC 24
Finished Aug 23 11:32:21 PM UTC 24
Peak memory 263568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292255346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1292255346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.3653704935
Short name T331
Test name
Test status
Simulation time 27751767883 ps
CPU time 1205.13 seconds
Started Aug 23 11:32:05 PM UTC 24
Finished Aug 23 11:52:23 PM UTC 24
Peak memory 297792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653704935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3653704935
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.1199710849
Short name T22
Test name
Test status
Simulation time 618642088 ps
CPU time 7.12 seconds
Started Aug 23 11:32:10 PM UTC 24
Finished Aug 23 11:32:18 PM UTC 24
Peak memory 263012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199710849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1199710849
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.691639752
Short name T23
Test name
Test status
Simulation time 2621290403 ps
CPU time 31.66 seconds
Started Aug 23 11:31:58 PM UTC 24
Finished Aug 23 11:32:31 PM UTC 24
Peak memory 262996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691639752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.691639752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.3883881713
Short name T238
Test name
Test status
Simulation time 28147243527 ps
CPU time 481.51 seconds
Started Aug 23 11:32:09 PM UTC 24
Finished Aug 23 11:40:16 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883881713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3883881713
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.3412229068
Short name T365
Test name
Test status
Simulation time 130595073571 ps
CPU time 1403.09 seconds
Started Aug 23 11:32:09 PM UTC 24
Finished Aug 23 11:55:46 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412229068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3412229068
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.56167680
Short name T201
Test name
Test status
Simulation time 8200403034 ps
CPU time 239.16 seconds
Started Aug 23 11:32:08 PM UTC 24
Finished Aug 23 11:36:11 PM UTC 24
Peak memory 263300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56167680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.56167680
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.3389982305
Short name T40
Test name
Test status
Simulation time 463953059 ps
CPU time 17.05 seconds
Started Aug 23 11:31:48 PM UTC 24
Finished Aug 23 11:32:06 PM UTC 24
Peak memory 269140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389982305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3389982305
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.2524884477
Short name T39
Test name
Test status
Simulation time 577134771 ps
CPU time 25.73 seconds
Started Aug 23 11:31:53 PM UTC 24
Finished Aug 23 11:32:20 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524884477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2524884477
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.3637723123
Short name T43
Test name
Test status
Simulation time 778650400 ps
CPU time 10.6 seconds
Started Aug 23 11:32:19 PM UTC 24
Finished Aug 23 11:32:31 PM UTC 24
Peak memory 295272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637723123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3637723123
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.2251077898
Short name T93
Test name
Test status
Simulation time 251344608 ps
CPU time 4.07 seconds
Started Aug 23 11:31:59 PM UTC 24
Finished Aug 23 11:32:04 PM UTC 24
Peak memory 252736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251077898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2251077898
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.399258191
Short name T67
Test name
Test status
Simulation time 1178187447 ps
CPU time 27.58 seconds
Started Aug 23 11:31:48 PM UTC 24
Finished Aug 23 11:32:17 PM UTC 24
Peak memory 262688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399258191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.399258191
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.644191591
Short name T51
Test name
Test status
Simulation time 15886615072 ps
CPU time 1139.98 seconds
Started Aug 23 11:32:10 PM UTC 24
Finished Aug 23 11:51:21 PM UTC 24
Peak memory 301952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644191591 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.644191591
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.256981187
Short name T665
Test name
Test status
Simulation time 470352034797 ps
CPU time 1143.47 seconds
Started Aug 24 01:14:59 AM UTC 24
Finished Aug 24 01:34:14 AM UTC 24
Peak memory 284456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256981187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.256981187
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/40.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.3371445371
Short name T600
Test name
Test status
Simulation time 1247422165 ps
CPU time 51.05 seconds
Started Aug 24 01:14:47 AM UTC 24
Finished Aug 24 01:15:40 AM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371445371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3371445371
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.3422319472
Short name T599
Test name
Test status
Simulation time 63815807 ps
CPU time 5.67 seconds
Started Aug 24 01:14:39 AM UTC 24
Finished Aug 24 01:14:46 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422319472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3422319472
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.1086318755
Short name T701
Test name
Test status
Simulation time 174602221181 ps
CPU time 1844.57 seconds
Started Aug 24 01:16:22 AM UTC 24
Finished Aug 24 01:47:24 AM UTC 24
Peak memory 304684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086318755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1086318755
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/40.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.4008369037
Short name T650
Test name
Test status
Simulation time 35470601868 ps
CPU time 801.44 seconds
Started Aug 24 01:16:26 AM UTC 24
Finished Aug 24 01:29:56 AM UTC 24
Peak memory 297872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008369037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.4008369037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.1281274933
Short name T608
Test name
Test status
Simulation time 7101742474 ps
CPU time 205.72 seconds
Started Aug 24 01:15:41 AM UTC 24
Finished Aug 24 01:19:09 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281274933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1281274933
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.1748936772
Short name T598
Test name
Test status
Simulation time 343596557 ps
CPU time 15.33 seconds
Started Aug 24 01:14:22 AM UTC 24
Finished Aug 24 01:14:39 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748936772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1748936772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.2748769529
Short name T300
Test name
Test status
Simulation time 293388246 ps
CPU time 15.01 seconds
Started Aug 24 01:14:30 AM UTC 24
Finished Aug 24 01:14:46 AM UTC 24
Peak memory 269080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748769529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2748769529
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/40.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.1530128238
Short name T597
Test name
Test status
Simulation time 1461027978 ps
CPU time 50.35 seconds
Started Aug 24 01:13:38 AM UTC 24
Finished Aug 24 01:14:30 AM UTC 24
Peak memory 269040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530128238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1530128238
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/40.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.1334811134
Short name T617
Test name
Test status
Simulation time 23507008987 ps
CPU time 294.24 seconds
Started Aug 24 01:16:36 AM UTC 24
Finished Aug 24 01:21:34 AM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334811134 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.1334811134
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/40.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.1587031791
Short name T685
Test name
Test status
Simulation time 133252141043 ps
CPU time 1201.87 seconds
Started Aug 24 01:18:49 AM UTC 24
Finished Aug 24 01:39:03 AM UTC 24
Peak memory 288300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587031791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1587031791
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/41.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.1380258255
Short name T612
Test name
Test status
Simulation time 3452635256 ps
CPU time 141.82 seconds
Started Aug 24 01:18:38 AM UTC 24
Finished Aug 24 01:21:02 AM UTC 24
Peak memory 265340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380258255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1380258255
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.939534113
Short name T309
Test name
Test status
Simulation time 119065473 ps
CPU time 6.37 seconds
Started Aug 24 01:18:35 AM UTC 24
Finished Aug 24 01:18:43 AM UTC 24
Peak memory 263292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939534113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.939534113
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.582951791
Short name T354
Test name
Test status
Simulation time 24222541060 ps
CPU time 482.63 seconds
Started Aug 24 01:19:10 AM UTC 24
Finished Aug 24 01:27:18 AM UTC 24
Peak memory 285892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582951791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.582951791
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/41.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.3968909548
Short name T668
Test name
Test status
Simulation time 54784350525 ps
CPU time 879.85 seconds
Started Aug 24 01:20:17 AM UTC 24
Finished Aug 24 01:35:06 AM UTC 24
Peak memory 295740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968909548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3968909548
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.1581653993
Short name T640
Test name
Test status
Simulation time 175639496425 ps
CPU time 457 seconds
Started Aug 24 01:19:06 AM UTC 24
Finished Aug 24 01:26:48 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581653993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1581653993
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.1956769999
Short name T605
Test name
Test status
Simulation time 165022329 ps
CPU time 8.61 seconds
Started Aug 24 01:17:59 AM UTC 24
Finished Aug 24 01:18:09 AM UTC 24
Peak memory 267000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956769999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1956769999
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.1435726650
Short name T607
Test name
Test status
Simulation time 4784253371 ps
CPU time 37.71 seconds
Started Aug 24 01:18:09 AM UTC 24
Finished Aug 24 01:18:48 AM UTC 24
Peak memory 262992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435726650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1435726650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/41.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.2023905312
Short name T219
Test name
Test status
Simulation time 970651875 ps
CPU time 19.84 seconds
Started Aug 24 01:18:44 AM UTC 24
Finished Aug 24 01:19:05 AM UTC 24
Peak memory 262936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023905312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2023905312
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.583680359
Short name T606
Test name
Test status
Simulation time 3995828463 ps
CPU time 40.33 seconds
Started Aug 24 01:17:55 AM UTC 24
Finished Aug 24 01:18:37 AM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583680359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.583680359
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/41.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.2747857165
Short name T715
Test name
Test status
Simulation time 132930136410 ps
CPU time 2609.15 seconds
Started Aug 24 01:20:47 AM UTC 24
Finished Aug 24 02:04:42 AM UTC 24
Peak memory 318940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747857165 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.2747857165
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/41.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all_with_rand_reset.1704786542
Short name T638
Test name
Test status
Simulation time 4352150988 ps
CPU time 343.48 seconds
Started Aug 24 01:20:54 AM UTC 24
Finished Aug 24 01:26:41 AM UTC 24
Peak memory 285696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1704786542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.a
lert_handler_stress_all_with_rand_reset.1704786542
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.2196616898
Short name T707
Test name
Test status
Simulation time 264457056776 ps
CPU time 1991.66 seconds
Started Aug 24 01:21:35 AM UTC 24
Finished Aug 24 01:55:06 AM UTC 24
Peak memory 302560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196616898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2196616898
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/42.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.1871696696
Short name T620
Test name
Test status
Simulation time 21430817242 ps
CPU time 122.84 seconds
Started Aug 24 01:21:20 AM UTC 24
Finished Aug 24 01:23:26 AM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871696696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1871696696
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.1129291998
Short name T616
Test name
Test status
Simulation time 3725020537 ps
CPU time 19.56 seconds
Started Aug 24 01:21:12 AM UTC 24
Finished Aug 24 01:21:33 AM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129291998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1129291998
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg.1678310259
Short name T647
Test name
Test status
Simulation time 100714956036 ps
CPU time 465.47 seconds
Started Aug 24 01:21:43 AM UTC 24
Finished Aug 24 01:29:34 AM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678310259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1678310259
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/42.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.3004588773
Short name T669
Test name
Test status
Simulation time 12218804796 ps
CPU time 791.64 seconds
Started Aug 24 01:21:57 AM UTC 24
Finished Aug 24 01:35:17 AM UTC 24
Peak memory 301892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004588773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3004588773
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.3213181481
Short name T630
Test name
Test status
Simulation time 14893030348 ps
CPU time 232.67 seconds
Started Aug 24 01:21:38 AM UTC 24
Finished Aug 24 01:25:33 AM UTC 24
Peak memory 263052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213181481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3213181481
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.1466458798
Short name T614
Test name
Test status
Simulation time 306101256 ps
CPU time 6.74 seconds
Started Aug 24 01:21:03 AM UTC 24
Finished Aug 24 01:21:11 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466458798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1466458798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.933235356
Short name T619
Test name
Test status
Simulation time 2578153561 ps
CPU time 31.27 seconds
Started Aug 24 01:21:10 AM UTC 24
Finished Aug 24 01:21:42 AM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933235356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.933235356
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/42.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.4244235477
Short name T618
Test name
Test status
Simulation time 60126399 ps
CPU time 2.43 seconds
Started Aug 24 01:21:33 AM UTC 24
Finished Aug 24 01:21:37 AM UTC 24
Peak memory 252768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244235477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.4244235477
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.1196684479
Short name T613
Test name
Test status
Simulation time 500359487 ps
CPU time 9.34 seconds
Started Aug 24 01:20:58 AM UTC 24
Finished Aug 24 01:21:09 AM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196684479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1196684479
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/42.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.2175726409
Short name T710
Test name
Test status
Simulation time 169652344817 ps
CPU time 2042.37 seconds
Started Aug 24 01:23:27 AM UTC 24
Finished Aug 24 01:57:50 AM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175726409 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.2175726409
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/42.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all_with_rand_reset.2391742977
Short name T628
Test name
Test status
Simulation time 651784489 ps
CPU time 57.17 seconds
Started Aug 24 01:23:40 AM UTC 24
Finished Aug 24 01:24:39 AM UTC 24
Peak memory 283900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2391742977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.a
lert_handler_stress_all_with_rand_reset.2391742977
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.2909414274
Short name T705
Test name
Test status
Simulation time 217924360403 ps
CPU time 1727.22 seconds
Started Aug 24 01:24:18 AM UTC 24
Finished Aug 24 01:53:22 AM UTC 24
Peak memory 300652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909414274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2909414274
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/43.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.4281015486
Short name T629
Test name
Test status
Simulation time 1002512255 ps
CPU time 64.3 seconds
Started Aug 24 01:24:09 AM UTC 24
Finished Aug 24 01:25:15 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281015486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.4281015486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.460406625
Short name T626
Test name
Test status
Simulation time 532978493 ps
CPU time 11.7 seconds
Started Aug 24 01:23:59 AM UTC 24
Finished Aug 24 01:24:12 AM UTC 24
Peak memory 262932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460406625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.460406625
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.3646655667
Short name T373
Test name
Test status
Simulation time 87194492704 ps
CPU time 1758.68 seconds
Started Aug 24 01:25:17 AM UTC 24
Finished Aug 24 01:54:52 AM UTC 24
Peak memory 304684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646655667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3646655667
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/43.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.4086994732
Short name T308
Test name
Test status
Simulation time 5229386011 ps
CPU time 478.9 seconds
Started Aug 24 01:25:35 AM UTC 24
Finished Aug 24 01:33:39 AM UTC 24
Peak memory 285584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086994732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.4086994732
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.1880906471
Short name T623
Test name
Test status
Simulation time 212681998 ps
CPU time 7.82 seconds
Started Aug 24 01:23:40 AM UTC 24
Finished Aug 24 01:23:49 AM UTC 24
Peak memory 267000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880906471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1880906471
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.2733375369
Short name T625
Test name
Test status
Simulation time 404194283 ps
CPU time 17.25 seconds
Started Aug 24 01:23:50 AM UTC 24
Finished Aug 24 01:24:08 AM UTC 24
Peak memory 269404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733375369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2733375369
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/43.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.4211305807
Short name T627
Test name
Test status
Simulation time 103103751 ps
CPU time 4.07 seconds
Started Aug 24 01:24:12 AM UTC 24
Finished Aug 24 01:24:17 AM UTC 24
Peak memory 253024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211305807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.4211305807
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.3113713347
Short name T624
Test name
Test status
Simulation time 405675965 ps
CPU time 17.18 seconds
Started Aug 24 01:23:40 AM UTC 24
Finished Aug 24 01:23:58 AM UTC 24
Peak memory 263240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113713347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3113713347
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/43.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.1613302396
Short name T697
Test name
Test status
Simulation time 14761566452 ps
CPU time 1092.66 seconds
Started Aug 24 01:25:45 AM UTC 24
Finished Aug 24 01:44:10 AM UTC 24
Peak memory 302208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613302396 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.1613302396
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/43.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.3306164837
Short name T682
Test name
Test status
Simulation time 9086206469 ps
CPU time 646.95 seconds
Started Aug 24 01:26:44 AM UTC 24
Finished Aug 24 01:37:38 AM UTC 24
Peak memory 283456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306164837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3306164837
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/44.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.3781745373
Short name T644
Test name
Test status
Simulation time 3176773486 ps
CPU time 141.02 seconds
Started Aug 24 01:26:40 AM UTC 24
Finished Aug 24 01:29:03 AM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781745373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3781745373
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.1149928814
Short name T639
Test name
Test status
Simulation time 279976701 ps
CPU time 17.16 seconds
Started Aug 24 01:26:25 AM UTC 24
Finished Aug 24 01:26:43 AM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149928814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1149928814
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.4280643739
Short name T700
Test name
Test status
Simulation time 28326185242 ps
CPU time 1149.8 seconds
Started Aug 24 01:27:19 AM UTC 24
Finished Aug 24 01:46:40 AM UTC 24
Peak memory 280824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280643739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.4280643739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.1852792665
Short name T662
Test name
Test status
Simulation time 27553822077 ps
CPU time 388.87 seconds
Started Aug 24 01:26:48 AM UTC 24
Finished Aug 24 01:33:21 AM UTC 24
Peak memory 269124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852792665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1852792665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.929612193
Short name T635
Test name
Test status
Simulation time 205032261 ps
CPU time 5.72 seconds
Started Aug 24 01:26:06 AM UTC 24
Finished Aug 24 01:26:13 AM UTC 24
Peak memory 266992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929612193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.929612193
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.981151222
Short name T636
Test name
Test status
Simulation time 233487695 ps
CPU time 9.07 seconds
Started Aug 24 01:26:14 AM UTC 24
Finished Aug 24 01:26:24 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981151222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.981151222
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/44.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.1903863754
Short name T641
Test name
Test status
Simulation time 551817937 ps
CPU time 14.81 seconds
Started Aug 24 01:26:42 AM UTC 24
Finished Aug 24 01:26:58 AM UTC 24
Peak memory 269408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903863754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1903863754
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.1359558274
Short name T634
Test name
Test status
Simulation time 1168356803 ps
CPU time 9.35 seconds
Started Aug 24 01:25:55 AM UTC 24
Finished Aug 24 01:26:05 AM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359558274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1359558274
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/44.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.3887925652
Short name T278
Test name
Test status
Simulation time 130767188767 ps
CPU time 1596.34 seconds
Started Aug 24 01:27:33 AM UTC 24
Finished Aug 24 01:54:25 AM UTC 24
Peak memory 304996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887925652 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.3887925652
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/44.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.256444917
Short name T702
Test name
Test status
Simulation time 56289638988 ps
CPU time 1206.46 seconds
Started Aug 24 01:29:35 AM UTC 24
Finished Aug 24 01:49:53 AM UTC 24
Peak memory 288296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256444917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.256444917
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/45.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.1260627214
Short name T654
Test name
Test status
Simulation time 9609717607 ps
CPU time 99.96 seconds
Started Aug 24 01:29:22 AM UTC 24
Finished Aug 24 01:31:04 AM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260627214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1260627214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.2899751959
Short name T648
Test name
Test status
Simulation time 2862409874 ps
CPU time 31.8 seconds
Started Aug 24 01:29:07 AM UTC 24
Finished Aug 24 01:29:40 AM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899751959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2899751959
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg.3271904522
Short name T714
Test name
Test status
Simulation time 47812848941 ps
CPU time 1935.53 seconds
Started Aug 24 01:29:48 AM UTC 24
Finished Aug 24 02:02:22 AM UTC 24
Peak memory 298796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271904522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3271904522
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/45.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.437528908
Short name T717
Test name
Test status
Simulation time 250332691384 ps
CPU time 2495.66 seconds
Started Aug 24 01:29:58 AM UTC 24
Finished Aug 24 02:11:57 AM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437528908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.437528908
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.3436651404
Short name T680
Test name
Test status
Simulation time 15078842493 ps
CPU time 452.81 seconds
Started Aug 24 01:29:41 AM UTC 24
Finished Aug 24 01:37:19 AM UTC 24
Peak memory 269196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436651404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3436651404
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.3463599111
Short name T645
Test name
Test status
Simulation time 577617844 ps
CPU time 29.61 seconds
Started Aug 24 01:28:35 AM UTC 24
Finished Aug 24 01:29:06 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463599111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3463599111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.2372361230
Short name T646
Test name
Test status
Simulation time 213137187 ps
CPU time 16.01 seconds
Started Aug 24 01:29:04 AM UTC 24
Finished Aug 24 01:29:21 AM UTC 24
Peak memory 269468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372361230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2372361230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/45.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.3160526972
Short name T649
Test name
Test status
Simulation time 201816294 ps
CPU time 18.08 seconds
Started Aug 24 01:29:27 AM UTC 24
Finished Aug 24 01:29:47 AM UTC 24
Peak memory 263328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160526972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3160526972
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.1887972735
Short name T643
Test name
Test status
Simulation time 2402324856 ps
CPU time 45.87 seconds
Started Aug 24 01:27:47 AM UTC 24
Finished Aug 24 01:28:34 AM UTC 24
Peak memory 269448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887972735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1887972735
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/45.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.982124477
Short name T693
Test name
Test status
Simulation time 9419077047 ps
CPU time 676.21 seconds
Started Aug 24 01:30:11 AM UTC 24
Finished Aug 24 01:41:35 AM UTC 24
Peak memory 301872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982124477 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.982124477
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/45.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all_with_rand_reset.1609990434
Short name T277
Test name
Test status
Simulation time 3159531698 ps
CPU time 273.52 seconds
Started Aug 24 01:30:11 AM UTC 24
Finished Aug 24 01:34:49 AM UTC 24
Peak memory 281528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1609990434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.a
lert_handler_stress_all_with_rand_reset.1609990434
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.3251607913
Short name T711
Test name
Test status
Simulation time 158149500789 ps
CPU time 1749.99 seconds
Started Aug 24 01:31:48 AM UTC 24
Finished Aug 24 02:01:15 AM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251607913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3251607913
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/46.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.93810100
Short name T661
Test name
Test status
Simulation time 1849596428 ps
CPU time 83.86 seconds
Started Aug 24 01:31:24 AM UTC 24
Finished Aug 24 01:32:50 AM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93810100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc
_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.93810100
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.2579453129
Short name T657
Test name
Test status
Simulation time 2301339544 ps
CPU time 22.06 seconds
Started Aug 24 01:31:10 AM UTC 24
Finished Aug 24 01:31:34 AM UTC 24
Peak memory 262964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579453129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2579453129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.1547532410
Short name T694
Test name
Test status
Simulation time 121420365740 ps
CPU time 618.16 seconds
Started Aug 24 01:31:59 AM UTC 24
Finished Aug 24 01:42:24 AM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547532410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1547532410
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/46.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.725715029
Short name T704
Test name
Test status
Simulation time 63003318117 ps
CPU time 1110.16 seconds
Started Aug 24 01:32:23 AM UTC 24
Finished Aug 24 01:51:04 AM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725715029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.725715029
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.2997482498
Short name T677
Test name
Test status
Simulation time 10676153620 ps
CPU time 312.12 seconds
Started Aug 24 01:31:52 AM UTC 24
Finished Aug 24 01:37:08 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997482498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2997482498
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.575063793
Short name T656
Test name
Test status
Simulation time 1841024910 ps
CPU time 41.94 seconds
Started Aug 24 01:30:40 AM UTC 24
Finished Aug 24 01:31:23 AM UTC 24
Peak memory 269040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575063793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.575063793
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.4243941148
Short name T655
Test name
Test status
Simulation time 20648537 ps
CPU time 2.66 seconds
Started Aug 24 01:31:05 AM UTC 24
Finished Aug 24 01:31:09 AM UTC 24
Peak memory 252676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243941148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4243941148
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/46.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.1367517775
Short name T653
Test name
Test status
Simulation time 736673023 ps
CPU time 16.59 seconds
Started Aug 24 01:30:21 AM UTC 24
Finished Aug 24 01:30:39 AM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367517775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1367517775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/46.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.3477041407
Short name T683
Test name
Test status
Simulation time 9637794332 ps
CPU time 365.01 seconds
Started Aug 24 01:32:51 AM UTC 24
Finished Aug 24 01:39:00 AM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477041407 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.3477041407
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/46.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all_with_rand_reset.3263168229
Short name T275
Test name
Test status
Simulation time 9492366759 ps
CPU time 391.42 seconds
Started Aug 24 01:33:22 AM UTC 24
Finished Aug 24 01:39:58 AM UTC 24
Peak memory 302336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3263168229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.a
lert_handler_stress_all_with_rand_reset.3263168229
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.2227942831
Short name T712
Test name
Test status
Simulation time 64557767027 ps
CPU time 1588.64 seconds
Started Aug 24 01:34:49 AM UTC 24
Finished Aug 24 02:01:33 AM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227942831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2227942831
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/47.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.1726799713
Short name T674
Test name
Test status
Simulation time 12205281973 ps
CPU time 122.72 seconds
Started Aug 24 01:34:38 AM UTC 24
Finished Aug 24 01:36:43 AM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726799713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1726799713
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.2627953367
Short name T667
Test name
Test status
Simulation time 1761905112 ps
CPU time 23.95 seconds
Started Aug 24 01:34:16 AM UTC 24
Finished Aug 24 01:34:41 AM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627953367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2627953367
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.3915499314
Short name T706
Test name
Test status
Simulation time 23320058957 ps
CPU time 1090.24 seconds
Started Aug 24 01:35:08 AM UTC 24
Finished Aug 24 01:53:29 AM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915499314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3915499314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/47.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.462547984
Short name T716
Test name
Test status
Simulation time 41735948200 ps
CPU time 1757.9 seconds
Started Aug 24 01:35:18 AM UTC 24
Finished Aug 24 02:04:53 AM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462547984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.462547984
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.1842624520
Short name T692
Test name
Test status
Simulation time 11229748118 ps
CPU time 334.41 seconds
Started Aug 24 01:35:02 AM UTC 24
Finished Aug 24 01:40:40 AM UTC 24
Peak memory 262984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842624520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1842624520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.3079074688
Short name T664
Test name
Test status
Simulation time 916237907 ps
CPU time 11.77 seconds
Started Aug 24 01:33:48 AM UTC 24
Finished Aug 24 01:34:01 AM UTC 24
Peak memory 263168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079074688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3079074688
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.487605384
Short name T666
Test name
Test status
Simulation time 801465381 ps
CPU time 33.54 seconds
Started Aug 24 01:34:02 AM UTC 24
Finished Aug 24 01:34:37 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487605384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.487605384
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/47.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.466052561
Short name T282
Test name
Test status
Simulation time 342670558 ps
CPU time 18.1 seconds
Started Aug 24 01:34:42 AM UTC 24
Finished Aug 24 01:35:01 AM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466052561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.466052561
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.3738236066
Short name T663
Test name
Test status
Simulation time 38782742 ps
CPU time 4.78 seconds
Started Aug 24 01:33:41 AM UTC 24
Finished Aug 24 01:33:47 AM UTC 24
Peak memory 262984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738236066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3738236066
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/47.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.518372515
Short name T672
Test name
Test status
Simulation time 556028981 ps
CPU time 11.92 seconds
Started Aug 24 01:36:07 AM UTC 24
Finished Aug 24 01:36:20 AM UTC 24
Peak memory 269040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518372515 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.518372515
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/47.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all_with_rand_reset.3010338550
Short name T695
Test name
Test status
Simulation time 17606272384 ps
CPU time 363.83 seconds
Started Aug 24 01:36:16 AM UTC 24
Finished Aug 24 01:42:24 AM UTC 24
Peak memory 283900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3010338550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.a
lert_handler_stress_all_with_rand_reset.3010338550
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.461066417
Short name T709
Test name
Test status
Simulation time 27333441731 ps
CPU time 1150.77 seconds
Started Aug 24 01:37:15 AM UTC 24
Finished Aug 24 01:56:37 AM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461066417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.461066417
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/48.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.3058273315
Short name T679
Test name
Test status
Simulation time 1517696183 ps
CPU time 23.52 seconds
Started Aug 24 01:36:50 AM UTC 24
Finished Aug 24 01:37:15 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058273315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3058273315
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.4004888207
Short name T681
Test name
Test status
Simulation time 905945474 ps
CPU time 46.54 seconds
Started Aug 24 01:36:44 AM UTC 24
Finished Aug 24 01:37:32 AM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004888207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.4004888207
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.4046073490
Short name T708
Test name
Test status
Simulation time 19814463622 ps
CPU time 1083.7 seconds
Started Aug 24 01:37:20 AM UTC 24
Finished Aug 24 01:55:35 AM UTC 24
Peak memory 302212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046073490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.4046073490
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/48.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.3021614169
Short name T713
Test name
Test status
Simulation time 66967014975 ps
CPU time 1466.42 seconds
Started Aug 24 01:37:33 AM UTC 24
Finished Aug 24 02:02:14 AM UTC 24
Peak memory 302568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021614169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3021614169
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.2415117018
Short name T696
Test name
Test status
Simulation time 10944976327 ps
CPU time 319.7 seconds
Started Aug 24 01:37:16 AM UTC 24
Finished Aug 24 01:42:39 AM UTC 24
Peak memory 269200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415117018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2415117018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.3575770913
Short name T675
Test name
Test status
Simulation time 19550801 ps
CPU time 2.29 seconds
Started Aug 24 01:36:40 AM UTC 24
Finished Aug 24 01:36:43 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575770913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3575770913
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.1284619333
Short name T676
Test name
Test status
Simulation time 117223102 ps
CPU time 5.22 seconds
Started Aug 24 01:36:43 AM UTC 24
Finished Aug 24 01:36:50 AM UTC 24
Peak memory 262928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284619333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1284619333
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/48.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.939931067
Short name T678
Test name
Test status
Simulation time 113006070 ps
CPU time 3.34 seconds
Started Aug 24 01:37:08 AM UTC 24
Finished Aug 24 01:37:14 AM UTC 24
Peak memory 252992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939931067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.939931067
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.3794341852
Short name T673
Test name
Test status
Simulation time 255358357 ps
CPU time 16.88 seconds
Started Aug 24 01:36:21 AM UTC 24
Finished Aug 24 01:36:39 AM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794341852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3794341852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/48.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.4056081829
Short name T719
Test name
Test status
Simulation time 950433935397 ps
CPU time 3063.93 seconds
Started Aug 24 01:37:39 AM UTC 24
Finished Aug 24 02:29:12 AM UTC 24
Peak memory 317284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056081829 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.4056081829
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/48.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.2797794859
Short name T310
Test name
Test status
Simulation time 8903502775 ps
CPU time 564.77 seconds
Started Aug 24 01:39:54 AM UTC 24
Finished Aug 24 01:49:25 AM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797794859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2797794859
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/49.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.1464475989
Short name T688
Test name
Test status
Simulation time 225130791 ps
CPU time 13.19 seconds
Started Aug 24 01:39:38 AM UTC 24
Finished Aug 24 01:39:52 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464475989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1464475989
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.2371083983
Short name T690
Test name
Test status
Simulation time 1021273558 ps
CPU time 43.92 seconds
Started Aug 24 01:39:33 AM UTC 24
Finished Aug 24 01:40:18 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371083983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2371083983
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.964179986
Short name T718
Test name
Test status
Simulation time 286678484885 ps
CPU time 2090.44 seconds
Started Aug 24 01:40:19 AM UTC 24
Finished Aug 24 02:15:30 AM UTC 24
Peak memory 304680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964179986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.964179986
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/49.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.667086016
Short name T703
Test name
Test status
Simulation time 8221688436 ps
CPU time 585.77 seconds
Started Aug 24 01:40:28 AM UTC 24
Finished Aug 24 01:50:21 AM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667086016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.667086016
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.32698705
Short name T698
Test name
Test status
Simulation time 32762613909 ps
CPU time 290.91 seconds
Started Aug 24 01:39:59 AM UTC 24
Finished Aug 24 01:44:53 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32698705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.32698705
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.4107571559
Short name T687
Test name
Test status
Simulation time 2435319393 ps
CPU time 31.4 seconds
Started Aug 24 01:39:04 AM UTC 24
Finished Aug 24 01:39:37 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107571559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.4107571559
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.1874070215
Short name T689
Test name
Test status
Simulation time 452132900 ps
CPU time 28.99 seconds
Started Aug 24 01:39:22 AM UTC 24
Finished Aug 24 01:39:53 AM UTC 24
Peak memory 262932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874070215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1874070215
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/49.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.659834688
Short name T691
Test name
Test status
Simulation time 1202471438 ps
CPU time 33.53 seconds
Started Aug 24 01:39:53 AM UTC 24
Finished Aug 24 01:40:28 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659834688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.659834688
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.2197892286
Short name T686
Test name
Test status
Simulation time 239539309 ps
CPU time 16.39 seconds
Started Aug 24 01:39:04 AM UTC 24
Finished Aug 24 01:39:22 AM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197892286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2197892286
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/49.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.216470615
Short name T223
Test name
Test status
Simulation time 54647618 ps
CPU time 2.02 seconds
Started Aug 23 11:33:14 PM UTC 24
Finished Aug 23 11:33:17 PM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216470615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.216470615
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.1775772783
Short name T25
Test name
Test status
Simulation time 360431238 ps
CPU time 8.05 seconds
Started Aug 23 11:33:10 PM UTC 24
Finished Aug 23 11:33:19 PM UTC 24
Peak memory 263076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775772783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1775772783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.979064544
Short name T324
Test name
Test status
Simulation time 3726596334 ps
CPU time 115.29 seconds
Started Aug 23 11:32:32 PM UTC 24
Finished Aug 23 11:34:29 PM UTC 24
Peak memory 269140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979064544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.979064544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.77347491
Short name T84
Test name
Test status
Simulation time 1096430702 ps
CPU time 23.83 seconds
Started Aug 23 11:32:31 PM UTC 24
Finished Aug 23 11:32:56 PM UTC 24
Peak memory 263004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77347491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc
_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.77347491
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.1157703909
Short name T305
Test name
Test status
Simulation time 164983264302 ps
CPU time 1662.56 seconds
Started Aug 23 11:32:54 PM UTC 24
Finished Aug 24 12:00:52 AM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157703909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1157703909
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.3095301221
Short name T418
Test name
Test status
Simulation time 410677294899 ps
CPU time 1807.38 seconds
Started Aug 23 11:32:57 PM UTC 24
Finished Aug 24 12:03:22 AM UTC 24
Peak memory 302216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095301221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3095301221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.439247186
Short name T112
Test name
Test status
Simulation time 4455741651 ps
CPU time 139.25 seconds
Started Aug 23 11:32:51 PM UTC 24
Finished Aug 23 11:35:13 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439247186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.439247186
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.619754589
Short name T69
Test name
Test status
Simulation time 193106356 ps
CPU time 3.71 seconds
Started Aug 23 11:32:22 PM UTC 24
Finished Aug 23 11:32:27 PM UTC 24
Peak memory 252736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619754589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.619754589
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.561614714
Short name T284
Test name
Test status
Simulation time 1866330890 ps
CPU time 40.87 seconds
Started Aug 23 11:32:27 PM UTC 24
Finished Aug 23 11:33:09 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561614714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.561614714
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.3579123947
Short name T105
Test name
Test status
Simulation time 5612202863 ps
CPU time 33.71 seconds
Started Aug 23 11:32:38 PM UTC 24
Finished Aug 23 11:33:13 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579123947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3579123947
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.3377143938
Short name T388
Test name
Test status
Simulation time 755328317 ps
CPU time 20.45 seconds
Started Aug 23 11:32:21 PM UTC 24
Finished Aug 23 11:32:43 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377143938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3377143938
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all.807736134
Short name T242
Test name
Test status
Simulation time 41874870266 ps
CPU time 885.91 seconds
Started Aug 23 11:33:11 PM UTC 24
Finished Aug 23 11:48:06 PM UTC 24
Peak memory 301880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807736134 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.807736134
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/5.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.3224064364
Short name T199
Test name
Test status
Simulation time 46233820 ps
CPU time 2.95 seconds
Started Aug 23 11:35:14 PM UTC 24
Finished Aug 23 11:35:18 PM UTC 24
Peak memory 263500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224064364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3224064364
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.1507105753
Short name T130
Test name
Test status
Simulation time 220194172 ps
CPU time 5.65 seconds
Started Aug 23 11:35:07 PM UTC 24
Finished Aug 23 11:35:14 PM UTC 24
Peak memory 263012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507105753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1507105753
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.3589339795
Short name T312
Test name
Test status
Simulation time 26026991250 ps
CPU time 183.71 seconds
Started Aug 23 11:33:32 PM UTC 24
Finished Aug 23 11:36:39 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589339795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3589339795
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.3759761209
Short name T79
Test name
Test status
Simulation time 1401851157 ps
CPU time 24.5 seconds
Started Aug 23 11:33:31 PM UTC 24
Finished Aug 23 11:33:57 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759761209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3759761209
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.1985811680
Short name T348
Test name
Test status
Simulation time 17318211378 ps
CPU time 788.28 seconds
Started Aug 23 11:34:37 PM UTC 24
Finished Aug 23 11:47:53 PM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985811680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1985811680
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.432982450
Short name T246
Test name
Test status
Simulation time 21365438422 ps
CPU time 206.96 seconds
Started Aug 23 11:34:03 PM UTC 24
Finished Aug 23 11:37:33 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432982450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.432982450
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.2542452747
Short name T390
Test name
Test status
Simulation time 1043327606 ps
CPU time 10.43 seconds
Started Aug 23 11:33:20 PM UTC 24
Finished Aug 23 11:33:32 PM UTC 24
Peak memory 267068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542452747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2542452747
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.3595268987
Short name T34
Test name
Test status
Simulation time 661623856 ps
CPU time 13.74 seconds
Started Aug 23 11:33:27 PM UTC 24
Finished Aug 23 11:33:42 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595268987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3595268987
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.2436362969
Short name T109
Test name
Test status
Simulation time 840625009 ps
CPU time 18.85 seconds
Started Aug 23 11:33:42 PM UTC 24
Finished Aug 23 11:34:02 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436362969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2436362969
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.1764277139
Short name T389
Test name
Test status
Simulation time 1081416751 ps
CPU time 7.02 seconds
Started Aug 23 11:33:18 PM UTC 24
Finished Aug 23 11:33:26 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764277139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1764277139
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.2976301930
Short name T100
Test name
Test status
Simulation time 57616996927 ps
CPU time 820.84 seconds
Started Aug 23 11:35:11 PM UTC 24
Finished Aug 23 11:49:00 PM UTC 24
Peak memory 295732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976301930 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.2976301930
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all_with_rand_reset.3112543653
Short name T81
Test name
Test status
Simulation time 4479030923 ps
CPU time 105.67 seconds
Started Aug 23 11:35:14 PM UTC 24
Finished Aug 23 11:37:02 PM UTC 24
Peak memory 279548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3112543653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.al
ert_handler_stress_all_with_rand_reset.3112543653
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.3220564552
Short name T224
Test name
Test status
Simulation time 64022652 ps
CPU time 2.15 seconds
Started Aug 23 11:37:51 PM UTC 24
Finished Aug 23 11:37:54 PM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220564552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3220564552
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy.4285894161
Short name T327
Test name
Test status
Simulation time 130679371202 ps
CPU time 1568.63 seconds
Started Aug 23 11:36:36 PM UTC 24
Finished Aug 24 12:03:01 AM UTC 24
Peak memory 301960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285894161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.4285894161
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.2214140645
Short name T132
Test name
Test status
Simulation time 3209421905 ps
CPU time 19.87 seconds
Started Aug 23 11:37:29 PM UTC 24
Finished Aug 23 11:37:50 PM UTC 24
Peak memory 263076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214140645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2214140645
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.2655936977
Short name T220
Test name
Test status
Simulation time 2741944111 ps
CPU time 122.23 seconds
Started Aug 23 11:36:21 PM UTC 24
Finished Aug 23 11:38:25 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655936977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2655936977
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.1956766901
Short name T126
Test name
Test status
Simulation time 399352513 ps
CPU time 14.32 seconds
Started Aug 23 11:36:12 PM UTC 24
Finished Aug 23 11:36:27 PM UTC 24
Peak memory 269124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956766901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1956766901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.1394171229
Short name T320
Test name
Test status
Simulation time 30844370459 ps
CPU time 1425.52 seconds
Started Aug 23 11:36:51 PM UTC 24
Finished Aug 24 12:00:52 AM UTC 24
Peak memory 295740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394171229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1394171229
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.1052106609
Short name T355
Test name
Test status
Simulation time 22383359870 ps
CPU time 980.59 seconds
Started Aug 23 11:37:02 PM UTC 24
Finished Aug 23 11:53:32 PM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052106609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1052106609
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.2256271494
Short name T106
Test name
Test status
Simulation time 9816099259 ps
CPU time 287.98 seconds
Started Aug 23 11:36:40 PM UTC 24
Finished Aug 23 11:41:32 PM UTC 24
Peak memory 269448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256271494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2256271494
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.3890674307
Short name T47
Test name
Test status
Simulation time 898140428 ps
CPU time 8.72 seconds
Started Aug 23 11:36:01 PM UTC 24
Finished Aug 23 11:36:10 PM UTC 24
Peak memory 266996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890674307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3890674307
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.233559802
Short name T99
Test name
Test status
Simulation time 291130723 ps
CPU time 7.11 seconds
Started Aug 23 11:36:12 PM UTC 24
Finished Aug 23 11:36:20 PM UTC 24
Peak memory 262916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233559802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.233559802
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.321141816
Short name T80
Test name
Test status
Simulation time 75787508 ps
CPU time 6.18 seconds
Started Aug 23 11:36:28 PM UTC 24
Finished Aug 23 11:36:35 PM UTC 24
Peak memory 263260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321141816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.321141816
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.2852246258
Short name T200
Test name
Test status
Simulation time 864982148 ps
CPU time 38.52 seconds
Started Aug 23 11:35:19 PM UTC 24
Finished Aug 23 11:35:59 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852246258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2852246258
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all_with_rand_reset.2072989663
Short name T36
Test name
Test status
Simulation time 1296671025 ps
CPU time 119.13 seconds
Started Aug 23 11:37:55 PM UTC 24
Finished Aug 23 11:39:56 PM UTC 24
Peak memory 279412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2072989663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.al
ert_handler_stress_all_with_rand_reset.2072989663
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.1278003636
Short name T225
Test name
Test status
Simulation time 30152417 ps
CPU time 2.52 seconds
Started Aug 23 11:41:57 PM UTC 24
Finished Aug 23 11:42:00 PM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278003636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1278003636
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.989989118
Short name T50
Test name
Test status
Simulation time 36032071426 ps
CPU time 645.49 seconds
Started Aug 23 11:40:13 PM UTC 24
Finished Aug 23 11:51:05 PM UTC 24
Peak memory 295812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989989118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.989989118
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.894957894
Short name T133
Test name
Test status
Simulation time 692531042 ps
CPU time 22.5 seconds
Started Aug 23 11:41:33 PM UTC 24
Finished Aug 23 11:41:57 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894957894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.894957894
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.2763002432
Short name T325
Test name
Test status
Simulation time 2128379932 ps
CPU time 86.15 seconds
Started Aug 23 11:40:03 PM UTC 24
Finished Aug 23 11:41:32 PM UTC 24
Peak memory 269404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763002432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2763002432
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.2962769718
Short name T85
Test name
Test status
Simulation time 81427299 ps
CPU time 6.25 seconds
Started Aug 23 11:39:57 PM UTC 24
Finished Aug 23 11:40:05 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962769718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2962769718
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.3282052212
Short name T70
Test name
Test status
Simulation time 18534945348 ps
CPU time 595.94 seconds
Started Aug 23 11:41:04 PM UTC 24
Finished Aug 23 11:51:06 PM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282052212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3282052212
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.1531336920
Short name T294
Test name
Test status
Simulation time 79088648999 ps
CPU time 134.3 seconds
Started Aug 23 11:40:17 PM UTC 24
Finished Aug 23 11:42:33 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531336920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1531336920
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.1545083274
Short name T236
Test name
Test status
Simulation time 974210845 ps
CPU time 41.72 seconds
Started Aug 23 11:38:47 PM UTC 24
Finished Aug 23 11:39:30 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545083274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1545083274
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.3063637420
Short name T237
Test name
Test status
Simulation time 87736988 ps
CPU time 4.71 seconds
Started Aug 23 11:40:05 PM UTC 24
Finished Aug 23 11:40:11 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063637420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3063637420
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.1689705034
Short name T202
Test name
Test status
Simulation time 470891141 ps
CPU time 18.54 seconds
Started Aug 23 11:38:26 PM UTC 24
Finished Aug 23 11:38:46 PM UTC 24
Peak memory 269124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689705034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1689705034
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.505310471
Short name T94
Test name
Test status
Simulation time 609335516048 ps
CPU time 2713.23 seconds
Started Aug 23 11:41:33 PM UTC 24
Finished Aug 24 12:27:12 AM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505310471 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.505310471
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/8.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.513522822
Short name T226
Test name
Test status
Simulation time 22005256 ps
CPU time 1.84 seconds
Started Aug 23 11:47:55 PM UTC 24
Finished Aug 23 11:47:57 PM UTC 24
Peak memory 260640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513522822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.513522822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.3291113978
Short name T55
Test name
Test status
Simulation time 238389568255 ps
CPU time 982.49 seconds
Started Aug 23 11:45:55 PM UTC 24
Finished Aug 24 12:02:27 AM UTC 24
Peak memory 302216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291113978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3291113978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.2339558070
Short name T394
Test name
Test status
Simulation time 2708308497 ps
CPU time 38.38 seconds
Started Aug 23 11:47:50 PM UTC 24
Finished Aug 23 11:48:30 PM UTC 24
Peak memory 263332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339558070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2339558070
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.3068703495
Short name T296
Test name
Test status
Simulation time 4517876137 ps
CPU time 112.54 seconds
Started Aug 23 11:43:59 PM UTC 24
Finished Aug 23 11:45:53 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068703495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3068703495
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.301525722
Short name T86
Test name
Test status
Simulation time 279219810 ps
CPU time 9.14 seconds
Started Aug 23 11:43:48 PM UTC 24
Finished Aug 23 11:43:58 PM UTC 24
Peak memory 269052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301525722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.301525722
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.3065701017
Short name T323
Test name
Test status
Simulation time 106525465128 ps
CPU time 1218.72 seconds
Started Aug 23 11:46:01 PM UTC 24
Finished Aug 24 12:06:32 AM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065701017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3065701017
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.515526885
Short name T97
Test name
Test status
Simulation time 7902244430 ps
CPU time 568.85 seconds
Started Aug 23 11:47:19 PM UTC 24
Finished Aug 23 11:56:54 PM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515526885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.515526885
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.1736504491
Short name T392
Test name
Test status
Simulation time 607849420 ps
CPU time 29.09 seconds
Started Aug 23 11:43:00 PM UTC 24
Finished Aug 23 11:43:31 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736504491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1736504491
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.1623871234
Short name T393
Test name
Test status
Simulation time 1090338474 ps
CPU time 13.68 seconds
Started Aug 23 11:43:31 PM UTC 24
Finished Aug 23 11:43:46 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623871234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1623871234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.1396595456
Short name T87
Test name
Test status
Simulation time 1752745353 ps
CPU time 13.24 seconds
Started Aug 23 11:45:39 PM UTC 24
Finished Aug 23 11:45:54 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396595456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1396595456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.4200161878
Short name T391
Test name
Test status
Simulation time 490838755 ps
CPU time 24.3 seconds
Started Aug 23 11:42:34 PM UTC 24
Finished Aug 23 11:43:00 PM UTC 24
Peak memory 269380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200161878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.4200161878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.3905364921
Short name T251
Test name
Test status
Simulation time 15393185000 ps
CPU time 1204.81 seconds
Started Aug 23 11:47:50 PM UTC 24
Finished Aug 24 12:08:07 AM UTC 24
Peak memory 312116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905364921 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.3905364921
Directory /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/9.alert_handler_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%