Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T17
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T26
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	1799582132	13196	0	0
DisabledNoTrigBkwd_A	1799582132	562767	0	0
DisabledNoTrigFwd_A	1799582132	1005807580	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	13196	0	0
T2	1371	586	0	0
T3	3898	0	0	0
T4	92468	0	0	0
T5	71091	0	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	82130	0	0	0
T13	36064	0	0	0
T14	2492	253	0	0
T15	62442	0	0	0
T16	6308	0	0	0
T17	65522	0	0	0
T26	1083	282	0	0
T27	54270	0	0	0
T64	26889	0	0	0
T75	0	402	0	0
T78	78200	0	0	0
T79	43207	0	0	0
T80	11381	0	0	0
T81	25927	0	0	0
T83	0	653	0	0
T108	0	760	0	0
T139	0	737	0	0
T162	0	1112	0	0
T246	0	665	0	0
T247	0	913	0	0
T248	0	343	0	0
T249	3338	937	0	0
T250	0	764	0	0
T251	0	657	0	0
T252	0	156	0	0
T253	0	226	0	0
T254	0	1462	0	0
T255	0	761	0	0
T256	0	534	0	0
T257	0	993	0	0
T258	1769	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	562767	0	0
T1	2682	2	0	0
T2	2742	27	0	0
T3	7796	2	0	0
T4	138702	0	0	0
T5	142182	0	0	0
T6	67490	0	0	0
T9	20879	0	0	0
T10	46840	0	0	0
T11	60734	0	0	0
T12	164260	4	0	0
T13	54096	18	0	0
T14	2492	9	0	0
T15	124884	0	0	0
T16	12616	0	0	0
T17	131044	0	0	0
T26	2166	0	0	0
T27	108540	42	0	0
T28	0	13	0	0
T29	0	2	0	0
T32	0	23	0	0
T44	0	75	0	0
T53	0	54	0	0
T54	0	3	0	0
T55	0	9	0	0
T56	0	5	0	0
T57	0	1	0	0
T58	0	46	0	0
T59	0	67	0	0
T60	0	9	0	0
T61	0	2	0	0
T62	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	1005807580	0	0
T1	10728	8462	0	0
T2	5484	2416	0	0
T3	15592	12071	0	0
T10	93680	34003	0	0
T11	121468	86824	0	0
T12	164260	155226	0	0
T13	72128	49215	0	0
T14	4984	3200	0	0
T15	124884	60747	0	0
T17	131044	98718	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T3 T10 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T17
1	1	Covered	T1,T3,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T246,T83
1	1	Covered	T1,T3,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	449895533	2869	0	0
DisabledNoTrigBkwd_A	449895533	154447	0	0
DisabledNoTrigFwd_A	449895533	230197798	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	2869	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T12	41065	0	0	0
T13	18032	0	0	0
T14	1246	253	0	0
T15	31221	0	0	0
T16	6308	0	0	0
T17	32761	0	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T83	0	653	0	0
T246	0	665	0	0
T250	0	764	0	0
T256	0	534	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	154447	0	0
T1	2682	2	0	0
T2	1371	0	0	0
T3	3898	2	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	4	0	0
T13	18032	3	0	0
T14	1246	9	0	0
T15	31221	0	0	0
T17	32761	0	0	0
T29	0	2	0	0
T32	0	23	0	0
T44	0	75	0	0
T53	0	32	0	0
T56	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	230197798	0	0
T1	2682	605	0	0
T2	1371	598	0	0
T3	3898	641	0	0
T10	23420	11400	0	0
T11	30367	1874	0	0
T12	41065	37374	0	0
T13	18032	14205	0	0
T14	1246	794	0	0
T15	31221	15632	0	0
T17	32761	32697	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T11
1	0	Covered	T13,T17,T15
1	1	Covered	T2,T10,T13

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T162,T248
1	1	Covered	T2,T10,T13

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T13,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	449895533	4678	0	0
DisabledNoTrigBkwd_A	449895533	129400	0	0
DisabledNoTrigFwd_A	449895533	257247778	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	4678	0	0
T2	1371	586	0	0
T3	3898	0	0	0
T4	46234	0	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	0	0	0
T14	1246	0	0	0
T15	31221	0	0	0
T17	32761	0	0	0
T162	0	1112	0	0
T248	0	343	0	0
T251	0	657	0	0
T253	0	226	0	0
T255	0	761	0	0
T257	0	993	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	129400	0	0
T2	1371	27	0	0
T3	3898	0	0	0
T4	46234	0	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	4	0	0
T14	1246	0	0	0
T15	31221	0	0	0
T17	32761	0	0	0
T27	0	32	0	0
T28	0	10	0	0
T53	0	20	0	0
T54	0	3	0	0
T55	0	7	0	0
T58	0	27	0	0
T60	0	9	0	0
T61	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	257247778	0	0
T1	2682	2619	0	0
T2	1371	602	0	0
T3	3898	3810	0	0
T10	23420	2111	0	0
T11	30367	24316	0	0
T12	41065	41001	0	0
T13	18032	16787	0	0
T14	1246	798	0	0
T15	31221	17217	0	0
T17	32761	32697	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T3 T10 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T14
1	0	Covered	T10,T13,T17
1	1	Covered	T10,T13,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T249,T139,T252
1	1	Covered	T10,T13,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T27,T28

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	449895533	3292	0	0
DisabledNoTrigBkwd_A	449895533	117114	0	0
DisabledNoTrigFwd_A	449895533	278000717	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	3292	0	0
T64	26889	0	0	0
T78	78200	0	0	0
T79	43207	0	0	0
T80	11381	0	0	0
T81	25927	0	0	0
T82	15873	0	0	0
T83	3510	0	0	0
T84	135115	0	0	0
T139	0	737	0	0
T249	3338	937	0	0
T252	0	156	0	0
T254	0	1462	0	0
T258	1769	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	117114	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T12	41065	0	0	0
T13	18032	11	0	0
T15	31221	0	0	0
T16	6308	0	0	0
T17	32761	0	0	0
T26	1083	0	0	0
T27	54270	10	0	0
T28	0	3	0	0
T53	0	2	0	0
T55	0	2	0	0
T57	0	1	0	0
T58	0	19	0	0
T59	0	67	0	0
T62	0	4	0	0
T63	0	133	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	278000717	0	0
T1	2682	2619	0	0
T2	1371	606	0	0
T3	3898	3810	0	0
T10	23420	18353	0	0
T11	30367	30317	0	0
T12	41065	35850	0	0
T13	18032	3105	0	0
T14	1246	802	0	0
T15	31221	3324	0	0
T17	32761	32697	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T3 T10 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T14
1	0	Covered	T13,T15,T16
1	1	Covered	T10,T13,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T75,T108
1	1	Covered	T10,T13,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T26,T28

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	449895533	2357	0	0
DisabledNoTrigBkwd_A	449895533	161806	0	0
DisabledNoTrigFwd_A	449895533	240361287	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	2357	0	0
T6	33745	0	0	0
T7	78779	0	0	0
T9	20879	0	0	0
T26	1083	282	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T31	42720	0	0	0
T32	15379	0	0	0
T75	0	402	0	0
T108	0	760	0	0
T247	0	913	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	161806	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T12	41065	0	0	0
T15	31221	0	0	0
T16	6308	0	0	0
T17	32761	44	0	0
T26	1083	8	0	0
T27	54270	0	0	0
T28	0	5	0	0
T53	0	30	0	0
T55	0	18	0	0
T58	0	3	0	0
T60	0	22	0	0
T61	0	12	0	0
T75	0	8	0	0
T108	0	10	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	240361287	0	0
T1	2682	2619	0	0
T2	1371	610	0	0
T3	3898	3810	0	0
T10	23420	2139	0	0
T11	30367	30317	0	0
T12	41065	41001	0	0
T13	18032	15118	0	0
T14	1246	806	0	0
T15	31221	24574	0	0
T17	32761	627	0	0