Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_reg_wrap.u_reg.u_intr_test_classa

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_intr_test_classb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_intr_test_classc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_intr_test_classd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_classa_accum_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_classa_esc_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_classa_state

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_classb_accum_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_classb_esc_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_classb_state

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_accum_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_esc_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_state

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_accum_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_esc_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_state

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.14 100.00 96.56 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_subreg_ext
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T49 T66 T144  30 1/1 assign qre = re; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_intr_test_classa
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T49 T66 T144  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_intr_test_classb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T49 T66 T144  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_intr_test_classc
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T49 T66 T144  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_intr_test_classd
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T49 T66 T144  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_accum_cnt
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T3 T10  27 1/1 assign qs = d; Tests: T1 T3 T10  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_esc_cnt
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T1 T3 T10 
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_state
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T1 T3 T10 
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_accum_cnt
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_esc_cnt
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T1 T3 T10 
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_state
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T1 T3 T10 
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_accum_cnt
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T3 T10  27 1/1 assign qs = d; Tests: T1 T3 T10  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_esc_cnt
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T1 T3 T10 
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_state
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T1 T3 T10 
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_accum_cnt
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T3 T10  27 1/1 assign qs = d; Tests: T1 T3 T10  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_esc_cnt
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T1 T3 T10 
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_state
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T1 T3 T10 
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%