Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T2 T3 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T2 T3 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T2 T3 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T15 T16 
159        1/1                    state_d = TimeoutSt;
           Tests:       T10 T15 T16 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T10 T15 T16 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T10 T15 T16 
172        1/1                    state_d    = Phase0St;
           Tests:       T15 T16 T27 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T15 T16 T27 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T15 T16 T27 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T15 T16 T27 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T10 T15 T16 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T15 T16 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T10 T15 T16 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T15 T16 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T2 T3 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T2 T3 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T2 T3 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T2 T3 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
194        1/1                    state_d = IdleSt;
           Tests:       T33 T34 T35 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T34 T35 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T34 T35 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T2 T3 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T2 T3 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T2 T3 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T2 T3 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
211        1/1                    state_d = IdleSt;
           Tests:       T29 T36 T37 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T36 T37 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T36 T37 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T2 T3 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T2 T3 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T2 T3 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T2 T3 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T2 T3 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
229        1/1                    state_d = IdleSt;
           Tests:       T38 T39 T40 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T38 T39 T40 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T38 T39 T40 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T2 T3 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T2 T3 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T2 T3 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T2 T3 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T2 T3 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
245        1/1                    state_d = IdleSt;
           Tests:       T41 T42 T40 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T41 T42 T40 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T41 T42 T40 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T2 T3 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T2 T3 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T2 T3 
260        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
261        1/1                    state_d = IdleSt;
           Tests:       T1 T13 T15 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T43
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T13
1	0	1	Covered	T2,T14,T13
1	1	0	Covered	T10,T13,T17
1	1	1	Covered	T10,T15,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T15,T16
0	1	Covered	T15,T16,T27
1	0	Covered	T32,T44,T45

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T15,T16
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T32,T44,T45

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T16
1	0	Covered	T46,T47,T48
1	1	Covered	T15,T16,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T2,T14,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T16,T27

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T14
1	Covered	T1,T12,T28

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T3,T28,T29

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T4,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T2,T14,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T2,T14,T13

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T10,T15,T16

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T4,T6,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T10,T15,T16
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T49,T37,T40
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T29,T36,T37
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T38,T50,T37
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T41,T42,T40
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T13,T15
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T10,T15,T16
TimeoutSt->Phase0St	172	Covered	T15,T16,T27

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T15,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T15,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T15,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T34,T35
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T36,T37
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T38,T39,T40
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T41,T42,T40
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T13,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	1799582132	966	0	0
CheckAccumTrig0_A	1799582132	2228	0	0
CheckAccumTrig1_A	1799582132	100	0	0
CheckClr_A	1799582132	960	0	0
CheckEn_A	1798681824	759345626	0	0
CheckPhase0_A	1799582132	2456	0	0
CheckPhase1_A	1799582132	2404	0	0
CheckPhase2_A	1799582132	2361	0	0
CheckPhase3_A	1799582132	2327	0	0
CheckTimeout0_A	1799582132	2737	0	0
CheckTimeoutSt1_A	1799582132	339186	0	0
CheckTimeoutSt2_A	1799582132	2407	0	0
CheckTimeoutStTrig_A	1799582132	206	0	0
ErrorStAllEscAsserted_A	1799582132	5098	0	0
ErrorStIsTerminal_A	1799582132	4138	0	0
EscStateOut_A	1798674296	1798391556	0	0
u_state_regs_A	1799582132	1798892160	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	966	0	0
T4	184936	258	0	0
T5	284364	0	0	0
T6	134980	226	0	0
T9	83516	110	0	0
T16	25232	0	0	0
T26	4332	0	0	0
T27	217080	0	0	0
T28	70432	0	0	0
T29	179732	0	0	0
T30	61220	0	0	0
T51	0	86	0	0
T52	0	286	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	2228	0	0
T1	2682	1	0	0
T2	2742	1	0	0
T3	7796	1	0	0
T4	138702	0	0	0
T5	142182	0	0	0
T6	67490	0	0	0
T9	20879	0	0	0
T10	46840	0	0	0
T11	60734	0	0	0
T12	164260	1	0	0
T13	54096	3	0	0
T14	2492	1	0	0
T15	124884	0	0	0
T16	12616	0	0	0
T17	131044	0	0	0
T26	2166	0	0	0
T27	108540	3	0	0
T28	0	3	0	0
T29	0	2	0	0
T44	0	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	4	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	3	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	100	0	0
T7	78779	0	0	0
T8	41042	0	0	0
T21	11266	0	0	0
T32	15379	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	1	0	0
T44	35967	1	0	0
T45	0	1	0	0
T49	151699	0	0	0
T50	0	1	0	0
T51	17151	0	0	0
T53	22055	0	0	0
T64	26889	1	0	0
T65	0	1	0	0
T66	143499	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	2715	0	0	0
T76	9583	0	0	0
T77	4755	0	0	0
T78	78200	0	0	0
T79	43207	0	0	0
T80	11381	0	0	0
T81	25927	0	0	0
T82	15873	0	0	0
T83	3510	0	0	0
T84	135115	0	0	0
T85	10071	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	960	0	0
T1	2682	1	0	0
T2	1371	0	0	0
T3	3898	0	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	67490	0	0	0
T9	41758	0	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	1	0	0
T14	1246	0	0	0
T15	62442	1	0	0
T16	6308	0	0	0
T17	32761	0	0	0
T26	1083	0	0	0
T27	108540	2	0	0
T28	35216	0	0	0
T29	89866	1	0	0
T30	15305	0	0	0
T31	42720	0	0	0
T40	0	2	0	0
T44	0	1	0	0
T50	0	4	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	0	2	0	0
T61	0	3	0	0
T64	0	4	0	0
T66	0	3	0	0
T77	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1798681824	759345626	0	0
T1	10728	8459	0	0
T2	5484	2416	0	0
T3	15592	12068	0	0
T10	93680	34002	0	0
T11	121468	86821	0	0
T12	164260	119891	0	0
T13	72128	32380	0	0
T14	4984	3200	0	0
T15	124884	60745	0	0
T17	131044	98715	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	2456	0	0
T1	2682	1	0	0
T2	2742	1	0	0
T3	7796	1	0	0
T4	138702	0	0	0
T5	142182	0	0	0
T6	67490	0	0	0
T9	20879	0	0	0
T10	46840	0	0	0
T11	60734	0	0	0
T12	164260	1	0	0
T13	54096	3	0	0
T14	2492	1	0	0
T15	124884	1	0	0
T16	12616	1	0	0
T17	131044	0	0	0
T26	2166	0	0	0
T27	108540	4	0	0
T28	0	3	0	0
T29	0	2	0	0
T32	0	1	0	0
T44	0	2	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	4	0	0
T57	0	1	0	0
T58	0	3	0	0
T59	0	1	0	0
T61	0	2	0	0
T77	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	2404	0	0
T1	2682	1	0	0
T2	2742	1	0	0
T3	7796	1	0	0
T4	138702	0	0	0
T5	142182	0	0	0
T6	67490	0	0	0
T9	20879	0	0	0
T10	46840	0	0	0
T11	60734	0	0	0
T12	164260	1	0	0
T13	54096	3	0	0
T14	2492	1	0	0
T15	124884	1	0	0
T16	12616	1	0	0
T17	131044	0	0	0
T26	2166	0	0	0
T27	108540	4	0	0
T28	0	3	0	0
T29	0	1	0	0
T32	0	1	0	0
T44	0	2	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	4	0	0
T57	0	1	0	0
T58	0	3	0	0
T59	0	1	0	0
T61	0	2	0	0
T77	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	2361	0	0
T1	2682	1	0	0
T2	2742	1	0	0
T3	7796	1	0	0
T4	138702	0	0	0
T5	142182	0	0	0
T6	67490	0	0	0
T9	20879	0	0	0
T10	46840	0	0	0
T11	60734	0	0	0
T12	164260	1	0	0
T13	54096	3	0	0
T14	2492	1	0	0
T15	124884	1	0	0
T16	12616	1	0	0
T17	131044	0	0	0
T26	2166	0	0	0
T27	108540	4	0	0
T28	0	3	0	0
T29	0	1	0	0
T32	0	1	0	0
T44	0	2	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	4	0	0
T57	0	1	0	0
T58	0	3	0	0
T59	0	1	0	0
T61	0	2	0	0
T77	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	2327	0	0
T1	2682	1	0	0
T2	2742	1	0	0
T3	7796	1	0	0
T4	138702	0	0	0
T5	142182	0	0	0
T6	67490	0	0	0
T9	20879	0	0	0
T10	46840	0	0	0
T11	60734	0	0	0
T12	164260	1	0	0
T13	54096	3	0	0
T14	2492	1	0	0
T15	124884	1	0	0
T16	12616	1	0	0
T17	131044	0	0	0
T26	2166	0	0	0
T27	108540	4	0	0
T28	0	3	0	0
T29	0	1	0	0
T32	0	1	0	0
T44	0	2	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	4	0	0
T57	0	1	0	0
T58	0	3	0	0
T59	0	1	0	0
T61	0	2	0	0
T77	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	2737	0	0
T4	184936	0	0	0
T5	284364	0	0	0
T6	67490	0	0	0
T9	41758	0	0	0
T10	46840	4	0	0
T11	60734	0	0	0
T12	82130	0	0	0
T13	36064	0	0	0
T14	2492	0	0	0
T15	124884	6	0	0
T16	25232	6	0	0
T17	65522	0	0	0
T26	2166	0	0	0
T27	108540	3	0	0
T28	35216	1	0	0
T29	89866	0	0	0
T32	0	1	0	0
T44	0	1	0	0
T46	0	6	0	0
T55	0	8	0	0
T57	0	3	0	0
T58	0	4	0	0
T61	0	8	0	0
T64	0	5	0	0
T76	0	1	0	0
T77	0	2	0	0
T88	0	1	0	0
T92	0	1	0	0
T93	0	9	0	0
T94	0	1	0	0
T95	0	3	0	0
T96	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	339186	0	0
T4	184936	0	0	0
T5	284364	0	0	0
T6	67490	0	0	0
T9	41758	0	0	0
T10	46840	595	0	0
T11	60734	0	0	0
T12	82130	0	0	0
T13	36064	0	0	0
T14	2492	0	0	0
T15	124884	1016	0	0
T16	25232	534	0	0
T17	65522	0	0	0
T26	2166	0	0	0
T27	108540	761	0	0
T28	35216	7	0	0
T29	89866	0	0	0
T32	0	8	0	0
T44	0	3	0	0
T46	0	1481	0	0
T55	0	851	0	0
T57	0	192	0	0
T58	0	268	0	0
T61	0	3064	0	0
T64	0	1361	0	0
T76	0	128	0	0
T77	0	201	0	0
T88	0	218	0	0
T92	0	71	0	0
T93	0	1824	0	0
T94	0	187	0	0
T95	0	442	0	0
T96	0	235	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	2407	0	0
T4	184936	0	0	0
T5	284364	0	0	0
T6	67490	0	0	0
T9	41758	0	0	0
T10	46840	3	0	0
T11	60734	0	0	0
T12	82130	0	0	0
T13	36064	0	0	0
T14	2492	0	0	0
T15	124884	5	0	0
T16	25232	3	0	0
T17	65522	0	0	0
T26	2166	0	0	0
T27	108540	2	0	0
T28	35216	1	0	0
T29	89866	0	0	0
T49	0	9	0	0
T55	0	4	0	0
T57	0	2	0	0
T58	0	4	0	0
T61	0	6	0	0
T64	0	2	0	0
T76	0	1	0	0
T77	0	1	0	0
T92	0	1	0	0
T93	0	7	0	0
T94	0	1	0	0
T95	0	7	0	0
T96	0	2	0	0
T97	0	3	0	0
T98	0	1	0	0
T99	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	206	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	67490	0	0	0
T9	41758	0	0	0
T15	31221	1	0	0
T16	6308	1	0	0
T26	1083	0	0	0
T27	108540	1	0	0
T28	35216	0	0	0
T29	89866	0	0	0
T30	15305	0	0	0
T38	0	1	0	0
T40	0	3	0	0
T41	0	1	0	0
T51	17151	0	0	0
T54	26816	0	0	0
T55	60194	0	0	0
T56	16796	0	0	0
T57	8636	0	0	0
T58	36460	0	0	0
T59	156956	0	0	0
T64	0	2	0	0
T66	0	2	0	0
T71	0	1	0	0
T77	4755	1	0	0
T89	0	2	0	0
T92	22585	0	0	0
T95	0	1	0	0
T99	0	1	0	0
T100	0	2	0	0
T101	0	3	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	3328	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	5098	0	0
T4	184936	1326	0	0
T5	284364	0	0	0
T6	134980	1298	0	0
T9	83516	614	0	0
T16	25232	0	0	0
T26	4332	0	0	0
T27	217080	0	0	0
T28	70432	0	0	0
T29	179732	0	0	0
T30	61220	0	0	0
T51	0	584	0	0
T52	0	1276	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	4138	0	0
T4	184936	1086	0	0
T5	284364	0	0	0
T6	134980	1058	0	0
T9	83516	494	0	0
T16	25232	0	0	0
T26	4332	0	0	0
T27	217080	0	0	0
T28	70432	0	0	0
T29	179732	0	0	0
T30	61220	0	0	0
T51	0	464	0	0
T52	0	1036	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1798674296	1798391556	0	0
T1	10728	10476	0	0
T2	5484	5224	0	0
T3	15592	15240	0	0
T10	93680	93324	0	0
T11	121468	121268	0	0
T12	164260	164004	0	0
T13	72128	71912	0	0
T14	4984	4680	0	0
T15	124884	124600	0	0
T17	131044	130788	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1799582132	1798892160	0	0
T1	10728	10476	0	0
T2	5484	5224	0	0
T3	15592	15240	0	0
T10	93680	93324	0	0
T11	121468	121268	0	0
T12	164260	164004	0	0
T13	72128	71912	0	0
T14	4984	4680	0	0
T15	124884	124600	0	0
T17	131044	130788	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T3 T14 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T3 T14 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T3 T14 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T15 T16 T32 
159        1/1                    state_d = TimeoutSt;
           Tests:       T15 T16 T32 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T15 T16 T32 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T15 T16 T32 
172        1/1                    state_d    = Phase0St;
           Tests:       T32 T44 T77 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T32 T44 T77 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T32 T44 T77 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T32 T44 T77 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T15 T16 T32 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T15 T16 T32 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T15 T16 T55 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T16 T55 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T14 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T3 T14 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T3 T14 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T3 T14 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T3 T14 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T3 T14 
194        1/1                    state_d = IdleSt;
           Tests:       T34 T109 T110 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T109 T110 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T109 T110 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T14 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T3 T14 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T14 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T14 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T14 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T3 T14 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T3 T14 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T3 T14 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T3 T14 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T3 T14 
211        1/1                    state_d = IdleSt;
           Tests:       T29 T36 T37 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T36 T37 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T36 T37 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T14 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T3 T14 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T14 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T14 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T14 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T3 T14 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T3 T14 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T3 T14 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T3 T14 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T3 T14 
229        1/1                    state_d = IdleSt;
           Tests:       T38 T39 T111 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T38 T39 T111 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T38 T39 T111 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T14 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T3 T14 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T14 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T14 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T3 T14 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T3 T14 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T3 T14 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T3 T14 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T3 T14 
245        1/1                    state_d = IdleSt;
           Tests:       T41 T42 T112 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T41 T42 T112 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T41 T42 T112 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T14 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T3 T14 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T14 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T3 T14 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T3 T14 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T3 T14 
260        1/1                  if (clr_i) begin
           Tests:       T1 T3 T14 
261        1/1                    state_d = IdleSt;
           Tests:       T1 T13 T44 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T9
1	0	Covered	T1,T3,T14
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T14

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T14

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T13,T15
1	0	1	Covered	T14,T54,T59
1	1	0	Covered	T10,T13,T17
1	1	1	Covered	T15,T16,T32

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T32
0	1	Covered	T77,T99,T38
1	0	Covered	T32,T44,T45

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T15,T16,T32
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T32,T44,T45

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T32
1	0	Not Covered
1	1	Covered	T77,T99,T38

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T14,T13,T44

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T14
1	Covered	T32,T57,T60

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T14,T13
1	Covered	T1,T12,T53

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T14,T13
1	Covered	T3,T29,T59

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T4,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T1,T3,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T14,T12,T53

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T1,T3,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T14,T13,T12

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T14
Phase1St	198	Covered	T1,T3,T14
Phase2St	215	Covered	T1,T3,T14
Phase3St	233	Covered	T1,T3,T14
TerminalSt	249	Covered	T1,T3,T14
TimeoutSt	159	Covered	T15,T16,T32

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T6,T9
IdleSt->Phase0St	152	Covered	T1,T3,T14
IdleSt->TimeoutSt	159	Covered	T15,T16,T32
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T37,T40,T102
Phase0St->Phase1St	198	Covered	T1,T3,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T36,T37
Phase1St->Phase2St	215	Covered	T1,T3,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T38,T37,T39
Phase2St->Phase3St	233	Covered	T1,T3,T14
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T41,T42,T112
Phase3St->TerminalSt	249	Covered	T1,T3,T14
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T13,T44
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T15,T16,T55
TimeoutSt->Phase0St	172	Covered	T32,T44,T77

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T32
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T32,T44,T77
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T32
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T55
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T109,T110
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T36,T37
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T38,T39,T111
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T41,T42,T112
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T13,T44
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	449895533	238	0	0
CheckAccumTrig0_A	449895533	790	0	0
CheckAccumTrig1_A	449895533	50	0	0
CheckClr_A	449895533	369	0	0
CheckEn_A	449670456	174378040	0	0
CheckPhase0_A	449895533	882	0	0
CheckPhase1_A	449895533	856	0	0
CheckPhase2_A	449895533	840	0	0
CheckPhase3_A	449895533	825	0	0
CheckTimeout0_A	449895533	596	0	0
CheckTimeoutSt1_A	449895533	70748	0	0
CheckTimeoutSt2_A	449895533	480	0	0
CheckTimeoutStTrig_A	449895533	60	0	0
ErrorStAllEscAsserted_A	449895533	1201	0	0
ErrorStIsTerminal_A	449895533	961	0	0
EscStateOut_A	449668574	449597889	0	0
u_state_regs_A	449895533	449723040	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	238	0	0
T4	46234	60	0	0
T5	71091	0	0	0
T6	33745	64	0	0
T9	20879	29	0	0
T16	6308	0	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T51	0	18	0	0
T52	0	67	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	790	0	0
T1	2682	1	0	0
T2	1371	0	0	0
T3	3898	1	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	1	0	0
T13	18032	1	0	0
T14	1246	1	0	0
T15	31221	0	0	0
T17	32761	0	0	0
T29	0	2	0	0
T44	0	1	0	0
T53	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	50	0	0
T7	78779	0	0	0
T8	41042	0	0	0
T21	11266	0	0	0
T32	15379	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T44	35967	1	0	0
T45	0	1	0	0
T51	17151	0	0	0
T53	22055	0	0	0
T65	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T75	2715	0	0	0
T76	9583	0	0	0
T77	4755	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	369	0	0
T1	2682	1	0	0
T2	1371	0	0	0
T3	3898	0	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	1	0	0
T14	1246	0	0	0
T15	31221	0	0	0
T17	32761	0	0	0
T29	0	1	0	0
T44	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T77	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449670456	174378040	0	0
T1	2682	605	0	0
T2	1371	598	0	0
T3	3898	641	0	0
T10	23420	11400	0	0
T11	30367	1874	0	0
T12	41065	2042	0	0
T13	18032	14204	0	0
T14	1246	794	0	0
T15	31221	15632	0	0
T17	32761	32696	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	882	0	0
T1	2682	1	0	0
T2	1371	0	0	0
T3	3898	1	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	1	0	0
T13	18032	1	0	0
T14	1246	1	0	0
T15	31221	0	0	0
T17	32761	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T44	0	2	0	0
T53	0	1	0	0
T77	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	856	0	0
T1	2682	1	0	0
T2	1371	0	0	0
T3	3898	1	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	1	0	0
T13	18032	1	0	0
T14	1246	1	0	0
T15	31221	0	0	0
T17	32761	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T44	0	2	0	0
T53	0	1	0	0
T77	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	840	0	0
T1	2682	1	0	0
T2	1371	0	0	0
T3	3898	1	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	1	0	0
T13	18032	1	0	0
T14	1246	1	0	0
T15	31221	0	0	0
T17	32761	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T44	0	2	0	0
T53	0	1	0	0
T77	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	825	0	0
T1	2682	1	0	0
T2	1371	0	0	0
T3	3898	1	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	1	0	0
T13	18032	1	0	0
T14	1246	1	0	0
T15	31221	0	0	0
T17	32761	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T44	0	2	0	0
T53	0	1	0	0
T77	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	596	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T15	31221	2	0	0
T16	6308	1	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T32	0	1	0	0
T44	0	1	0	0
T55	0	1	0	0
T58	0	1	0	0
T77	0	1	0	0
T92	0	1	0	0
T93	0	4	0	0
T94	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	70748	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T15	31221	400	0	0
T16	6308	116	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T32	0	8	0	0
T44	0	3	0	0
T55	0	123	0	0
T58	0	38	0	0
T77	0	91	0	0
T92	0	71	0	0
T93	0	845	0	0
T94	0	187	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	480	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T15	31221	2	0	0
T16	6308	1	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T55	0	1	0	0
T58	0	1	0	0
T92	0	1	0	0
T93	0	4	0	0
T94	0	1	0	0
T95	0	7	0	0
T97	0	3	0	0
T98	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	60	0	0
T38	0	1	0	0
T41	0	1	0	0
T51	17151	0	0	0
T54	26816	0	0	0
T55	60194	0	0	0
T56	16796	0	0	0
T57	8636	0	0	0
T58	36460	0	0	0
T59	156956	0	0	0
T66	0	2	0	0
T77	4755	1	0	0
T92	22585	0	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T102	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T108	3328	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	1201	0	0
T4	46234	324	0	0
T5	71091	0	0	0
T6	33745	294	0	0
T9	20879	146	0	0
T16	6308	0	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T51	0	146	0	0
T52	0	291	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	961	0	0
T4	46234	264	0	0
T5	71091	0	0	0
T6	33745	234	0	0
T9	20879	116	0	0
T16	6308	0	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T51	0	116	0	0
T52	0	231	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449668574	449597889	0	0
T1	2682	2619	0	0
T2	1371	1306	0	0
T3	3898	3810	0	0
T10	23420	23331	0	0
T11	30367	30317	0	0
T12	41065	41001	0	0
T13	18032	17978	0	0
T14	1246	1170	0	0
T15	31221	31150	0	0
T17	32761	32697	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	449723040	0	0
T1	2682	2619	0	0
T2	1371	1306	0	0
T3	3898	3810	0	0
T10	23420	23331	0	0
T11	30367	30317	0	0
T12	41065	41001	0	0
T13	18032	17978	0	0
T14	1246	1170	0	0
T15	31221	31150	0	0
T17	32761	32697	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T13 T5 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T13 T5 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T13 T5 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T15 T16 
159        1/1                    state_d = TimeoutSt;
           Tests:       T10 T15 T16 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T10 T15 T16 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T10 T15 T16 
172        1/1                    state_d    = Phase0St;
           Tests:       T15 T16 T95 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T15 T16 T95 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T15 T16 T95 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T15 T16 T95 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T10 T15 T16 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T15 T16 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T10 T16 T76 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T16 T76 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T13 T15 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T13 T15 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T13 T15 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T13 T15 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T13 T15 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T13 T15 
194        1/1                    state_d = IdleSt;
           Tests:       T33 T35 T113 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T35 T113 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T35 T113 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T13 T15 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T13 T15 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T13 T15 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T13 T15 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T13 T15 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T13 T15 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T13 T15 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T13 T15 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T13 T15 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T13 T15 
211        1/1                    state_d = IdleSt;
           Tests:       T43 T114 T115 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T43 T114 T115 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T43 T114 T115 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T13 T15 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T13 T15 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T13 T15 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T13 T15 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T13 T15 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T13 T15 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T13 T15 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T13 T15 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T13 T15 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T13 T15 
229        1/1                    state_d = IdleSt;
           Tests:       T116 T117 T118 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T116 T117 T118 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T116 T117 T118 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T13 T15 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T13 T15 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T13 T15 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T13 T15 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T13 T15 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T13 T15 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T13 T15 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T13 T15 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T13 T15 
245        1/1                    state_d = IdleSt;
           Tests:       T119 T74 T120 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T119 T74 T120 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T119 T74 T120 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T13 T15 
249        1/1                    state_d = TerminalSt;
           Tests:       T2 T13 T15 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T13 T15 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T13 T15 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T2 T13 T15 
259        1/1                  esc_state_o = Terminal;
           Tests:       T2 T13 T15 
260        1/1                  if (clr_i) begin
           Tests:       T2 T13 T15 
261        1/1                    state_d = IdleSt;
           Tests:       T15 T55 T61 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T9
1	0	Covered	T2,T10,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T10,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T13,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T15
1	0	1	Covered	T2,T31,T57
1	1	0	Covered	T17,T15,T30
1	1	1	Covered	T10,T15,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T15,T16
0	1	Covered	T15,T16,T95
1	0	Covered	T64,T41,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T10,T15,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T64,T41,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T16
1	0	Covered	T48
1	1	Covered	T15,T16,T95

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T16,T27
1	Covered	T2,T13,T60

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T13,T28
1	Covered	T15,T16,T27

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T13,T15
1	Covered	T121,T122,T123

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T13,T15
1	Covered	T28,T54,T55

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T4,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T2,T13,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T2,T13,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T2,T13,T27

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T2,T15,T27

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T13,T15
Phase1St	198	Covered	T2,T13,T15
Phase2St	215	Covered	T2,T13,T15
Phase3St	233	Covered	T2,T13,T15
TerminalSt	249	Covered	T2,T13,T15
TimeoutSt	159	Covered	T10,T15,T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T6,T9
IdleSt->Phase0St	152	Covered	T2,T13,T27
IdleSt->TimeoutSt	159	Covered	T10,T15,T16
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T106,T71,T33
Phase0St->Phase1St	198	Covered	T2,T13,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T43,T114,T115
Phase1St->Phase2St	215	Covered	T2,T13,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T116,T113,T117
Phase2St->Phase3St	233	Covered	T2,T13,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T119,T74,T120
Phase3St->TerminalSt	249	Covered	T2,T13,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T15,T55,T61
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T10,T16,T76
TimeoutSt->Phase0St	172	Covered	T15,T16,T95

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T13,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T15,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T95
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T15,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T16,T76
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T35,T113
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T13,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T13,T15,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T43,T114,T115
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T13,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T13,T15,T16
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T116,T117,T118
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T13,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T13,T15,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T119,T74,T120
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T13,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T13,T15,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T55,T61
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T13,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	449895533	237	0	0
CheckAccumTrig0_A	449895533	484	0	0
CheckAccumTrig1_A	449895533	16	0	0
CheckClr_A	449895533	200	0	0
CheckEn_A	449670456	197687820	0	0
CheckPhase0_A	449895533	520	0	0
CheckPhase1_A	449895533	511	0	0
CheckPhase2_A	449895533	501	0	0
CheckPhase3_A	449895533	496	0	0
CheckTimeout0_A	449895533	666	0	0
CheckTimeoutSt1_A	449895533	82418	0	0
CheckTimeoutSt2_A	449895533	597	0	0
CheckTimeoutStTrig_A	449895533	47	0	0
ErrorStAllEscAsserted_A	449895533	1289	0	0
ErrorStIsTerminal_A	449895533	1049	0	0
EscStateOut_A	449668574	449597889	0	0
u_state_regs_A	449895533	449723040	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	237	0	0
T4	46234	54	0	0
T5	71091	0	0	0
T6	33745	57	0	0
T9	20879	22	0	0
T16	6308	0	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T51	0	26	0	0
T52	0	78	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	484	0	0
T2	1371	1	0	0
T3	3898	0	0	0
T4	46234	0	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	1	0	0
T14	1246	0	0	0
T15	31221	0	0	0
T17	32761	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T58	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	16	0	0
T33	0	1	0	0
T34	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T49	151699	0	0	0
T50	0	1	0	0
T64	26889	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T78	78200	0	0	0
T79	43207	0	0	0
T80	11381	0	0	0
T81	25927	0	0	0
T82	15873	0	0	0
T83	3510	0	0	0
T84	135115	0	0	0
T85	10071	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	200	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T15	31221	1	0	0
T16	6308	0	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T40	0	2	0	0
T50	0	4	0	0
T55	0	3	0	0
T61	0	1	0	0
T64	0	3	0	0
T66	0	3	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449670456	197687820	0	0
T1	2682	2618	0	0
T2	1371	602	0	0
T3	3898	3809	0	0
T10	23420	2111	0	0
T11	30367	24315	0	0
T12	41065	41000	0	0
T13	18032	932	0	0
T14	1246	798	0	0
T15	31221	17216	0	0
T17	32761	32696	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	520	0	0
T2	1371	1	0	0
T3	3898	0	0	0
T4	46234	0	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	1	0	0
T14	1246	0	0	0
T15	31221	1	0	0
T16	0	1	0	0
T17	32761	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T58	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	511	0	0
T2	1371	1	0	0
T3	3898	0	0	0
T4	46234	0	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	1	0	0
T14	1246	0	0	0
T15	31221	1	0	0
T16	0	1	0	0
T17	32761	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T58	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	501	0	0
T2	1371	1	0	0
T3	3898	0	0	0
T4	46234	0	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	1	0	0
T14	1246	0	0	0
T15	31221	1	0	0
T16	0	1	0	0
T17	32761	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T58	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	496	0	0
T2	1371	1	0	0
T3	3898	0	0	0
T4	46234	0	0	0
T10	23420	0	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	1	0	0
T14	1246	0	0	0
T15	31221	1	0	0
T16	0	1	0	0
T17	32761	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T58	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	666	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T10	23420	3	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	0	0	0
T14	1246	0	0	0
T15	31221	1	0	0
T16	6308	2	0	0
T17	32761	0	0	0
T57	0	1	0	0
T58	0	2	0	0
T64	0	5	0	0
T76	0	1	0	0
T93	0	1	0	0
T95	0	1	0	0
T96	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	82418	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T10	23420	475	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	0	0	0
T14	1246	0	0	0
T15	31221	37	0	0
T16	6308	160	0	0
T17	32761	0	0	0
T57	0	67	0	0
T58	0	134	0	0
T64	0	1361	0	0
T76	0	128	0	0
T93	0	210	0	0
T95	0	100	0	0
T96	0	235	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	597	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T10	23420	3	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	0	0	0
T14	1246	0	0	0
T15	31221	0	0	0
T16	6308	1	0	0
T17	32761	0	0	0
T49	0	9	0	0
T57	0	1	0	0
T58	0	2	0	0
T64	0	2	0	0
T76	0	1	0	0
T93	0	1	0	0
T96	0	2	0	0
T99	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	47	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T15	31221	1	0	0
T16	6308	1	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T40	0	3	0	0
T64	0	2	0	0
T71	0	1	0	0
T89	0	2	0	0
T95	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T107	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	1289	0	0
T4	46234	300	0	0
T5	71091	0	0	0
T6	33745	339	0	0
T9	20879	155	0	0
T16	6308	0	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T51	0	151	0	0
T52	0	344	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	1049	0	0
T4	46234	240	0	0
T5	71091	0	0	0
T6	33745	279	0	0
T9	20879	125	0	0
T16	6308	0	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T51	0	121	0	0
T52	0	284	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449668574	449597889	0	0
T1	2682	2619	0	0
T2	1371	1306	0	0
T3	3898	3810	0	0
T10	23420	23331	0	0
T11	30367	30317	0	0
T12	41065	41001	0	0
T13	18032	17978	0	0
T14	1246	1170	0	0
T15	31221	31150	0	0
T17	32761	32697	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	449723040	0	0
T1	2682	2619	0	0
T2	1371	1306	0	0
T3	3898	3810	0	0
T10	23420	23331	0	0
T11	30367	30317	0	0
T12	41065	41001	0	0
T13	18032	17978	0	0
T14	1246	1170	0	0
T15	31221	31150	0	0
T17	32761	32697	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T13 T27 T28 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T13 T27 T28 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T13 T27 T28 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T15 T16 T27 
159        1/1                    state_d = TimeoutSt;
           Tests:       T15 T16 T27 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T15 T16 T27 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T15 T16 T27 
172        1/1                    state_d    = Phase0St;
           Tests:       T27 T61 T63 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T27 T61 T63 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T27 T61 T63 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T27 T61 T63 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T15 T16 T27 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T15 T16 T27 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T15 T16 T27 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T16 T27 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T13 T27 T28 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T13 T27 T28 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T13 T27 T28 
190        1/1                  esc_state_o = Phase0;
           Tests:       T13 T27 T28 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T13 T27 T28 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T13 T27 T28 
194        1/1                    state_d = IdleSt;
           Tests:       T35 T74 T124 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T74 T124 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T74 T124 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T13 T27 T28 
198        1/1                    state_d = Phase1St;
           Tests:       T13 T27 T28 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T27 T28 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T27 T28 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T13 T27 T28 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T13 T27 T28 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T13 T27 T28 
207        1/1                  esc_state_o = Phase1;
           Tests:       T13 T27 T28 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T13 T27 T28 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T13 T27 T28 
211        1/1                    state_d = IdleSt;
           Tests:       T125 T126 T127 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T125 T126 T127 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T125 T126 T127 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T13 T27 T28 
215        1/1                    state_d = Phase2St;
           Tests:       T13 T27 T28 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T27 T28 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T27 T28 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T13 T27 T28 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T13 T27 T28 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T13 T27 T28 
224        1/1                  esc_state_o = Phase2;
           Tests:       T13 T27 T28 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T13 T27 T28 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T13 T27 T28 
229        1/1                    state_d = IdleSt;
           Tests:       T40 T128 T129 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T40 T128 T129 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T40 T128 T129 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T13 T27 T28 
233        1/1                    state_d = Phase3St;
           Tests:       T13 T27 T28 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T27 T28 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T13 T27 T28 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T13 T27 T28 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T13 T27 T28 
241        1/1                  esc_state_o = Phase3;
           Tests:       T13 T27 T28 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T13 T27 T28 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T13 T27 T28 
245        1/1                    state_d = IdleSt;
           Tests:       T40 T70 T130 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T40 T70 T130 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T40 T70 T130 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T13 T27 T28 
249        1/1                    state_d = TerminalSt;
           Tests:       T13 T27 T28 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T27 T28 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T13 T27 T28 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T13 T27 T28 
259        1/1                  esc_state_o = Terminal;
           Tests:       T13 T27 T28 
260        1/1                  if (clr_i) begin
           Tests:       T13 T27 T28 
261        1/1                    state_d = IdleSt;
           Tests:       T27 T28 T53 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T9
1	0	Covered	T13,T15,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T15,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T10,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T43
1	1	1	Covered	T13,T27,T28

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T12,T15
1	0	1	Covered	T13,T59,T131
1	1	0	Covered	T10,T17,T16
1	1	1	Covered	T15,T16,T27

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T27
0	1	Covered	T27,T61,T63
1	0	Covered	T66,T37,T132

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T15,T16,T27
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T66,T37,T132

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T27
1	0	Not Covered
1	1	Covered	T27,T61,T63

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T27,T28,T53
1	Covered	T13,T55,T57

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T13,T28,T55
1	Covered	T27,T53,T58

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T27,T53
1	Covered	T28,T58,T49

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T27,T28
1	Covered	T61,T63,T133

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T4,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T28,T53,T55

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T13,T28,T53

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T53,T61,T63

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T13,T27,T28

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T13,T27,T28
Phase1St	198	Covered	T13,T27,T28
Phase2St	215	Covered	T13,T27,T28
Phase3St	233	Covered	T13,T27,T28
TerminalSt	249	Covered	T13,T27,T28
TimeoutSt	159	Covered	T15,T16,T27

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T6,T9
IdleSt->Phase0St	152	Covered	T13,T27,T28
IdleSt->TimeoutSt	159	Covered	T15,T16,T27
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T49,T37,T35
Phase0St->Phase1St	198	Covered	T13,T27,T28
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T40,T125,T126
Phase1St->Phase2St	215	Covered	T13,T27,T28
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T50,T40,T113
Phase2St->Phase3St	233	Covered	T13,T27,T28
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T40,T70,T130
Phase3St->TerminalSt	249	Covered	T13,T27,T28
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T27,T28,T53
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T15,T16,T27
TimeoutSt->Phase0St	172	Covered	T27,T61,T63

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T27,T28
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T27
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T27,T61,T63
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T27
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T27
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T35,T74,T124
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T13,T27,T28
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T13,T27,T28
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T125,T126,T127
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T13,T27,T28
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T13,T27,T28
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T40,T128,T129
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T13,T27,T28
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T13,T27,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T40,T70,T130
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T13,T27,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T13,T27,T28
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T27,T28,T53
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T13,T27,T28
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	449895533	247	0	0
CheckAccumTrig0_A	449895533	476	0	0
CheckAccumTrig1_A	449895533	10	0	0
CheckClr_A	449895533	187	0	0
CheckEn_A	449670456	196001489	0	0
CheckPhase0_A	449895533	527	0	0
CheckPhase1_A	449895533	520	0	0
CheckPhase2_A	449895533	511	0	0
CheckPhase3_A	449895533	502	0	0
CheckTimeout0_A	449895533	713	0	0
CheckTimeoutSt1_A	449895533	96459	0	0
CheckTimeoutSt2_A	449895533	639	0	0
CheckTimeoutStTrig_A	449895533	57	0	0
ErrorStAllEscAsserted_A	449895533	1311	0	0
ErrorStIsTerminal_A	449895533	1071	0	0
EscStateOut_A	449668574	449597889	0	0
u_state_regs_A	449895533	449723040	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	247	0	0
T4	46234	72	0	0
T5	71091	0	0	0
T6	33745	58	0	0
T9	20879	31	0	0
T16	6308	0	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T51	0	20	0	0
T52	0	66	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	476	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T12	41065	0	0	0
T13	18032	1	0	0
T15	31221	0	0	0
T16	6308	0	0	0
T17	32761	0	0	0
T26	1083	0	0	0
T27	54270	2	0	0
T28	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	10	0	0
T37	0	1	0	0
T66	143499	1	0	0
T89	20533	0	0	0
T90	435339	0	0	0
T107	0	1	0	0
T113	0	1	0	0
T132	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	4183	0	0	0
T140	92664	0	0	0
T141	27152	0	0	0
T142	24294	0	0	0
T143	123413	0	0	0
T144	267181	0	0	0
T145	74904	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	187	0	0
T6	33745	0	0	0
T7	78779	0	0	0
T8	41042	0	0	0
T9	20879	0	0	0
T27	54270	2	0	0
T28	17608	2	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T31	42720	0	0	0
T32	15379	0	0	0
T49	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	0	2	0	0
T63	0	2	0	0
T64	0	1	0	0
T78	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449670456	196001489	0	0
T1	2682	2618	0	0
T2	1371	606	0	0
T3	3898	3809	0	0
T10	23420	18352	0	0
T11	30367	30316	0	0
T12	41065	35849	0	0
T13	18032	2127	0	0
T14	1246	802	0	0
T15	31221	3324	0	0
T17	32761	32696	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	527	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T12	41065	0	0	0
T13	18032	1	0	0
T15	31221	0	0	0
T16	6308	0	0	0
T17	32761	0	0	0
T26	1083	0	0	0
T27	54270	3	0	0
T28	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	520	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T12	41065	0	0	0
T13	18032	1	0	0
T15	31221	0	0	0
T16	6308	0	0	0
T17	32761	0	0	0
T26	1083	0	0	0
T27	54270	3	0	0
T28	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	511	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T12	41065	0	0	0
T13	18032	1	0	0
T15	31221	0	0	0
T16	6308	0	0	0
T17	32761	0	0	0
T26	1083	0	0	0
T27	54270	3	0	0
T28	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	502	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T12	41065	0	0	0
T13	18032	1	0	0
T15	31221	0	0	0
T16	6308	0	0	0
T17	32761	0	0	0
T26	1083	0	0	0
T27	54270	3	0	0
T28	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	713	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T15	31221	3	0	0
T16	6308	1	0	0
T26	1083	0	0	0
T27	54270	3	0	0
T28	17608	1	0	0
T29	44933	0	0	0
T55	0	3	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	0	8	0	0
T77	0	1	0	0
T93	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	96459	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T15	31221	579	0	0
T16	6308	116	0	0
T26	1083	0	0	0
T27	54270	761	0	0
T28	17608	7	0	0
T29	44933	0	0	0
T55	0	351	0	0
T57	0	62	0	0
T58	0	96	0	0
T61	0	3064	0	0
T77	0	110	0	0
T93	0	411	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	639	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T15	31221	3	0	0
T16	6308	1	0	0
T26	1083	0	0	0
T27	54270	2	0	0
T28	17608	1	0	0
T29	44933	0	0	0
T55	0	3	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	0	6	0	0
T77	0	1	0	0
T93	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	57	0	0
T6	33745	0	0	0
T7	78779	0	0	0
T8	41042	0	0	0
T9	20879	0	0	0
T27	54270	1	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T31	42720	0	0	0
T32	15379	0	0	0
T61	0	2	0	0
T63	0	2	0	0
T67	0	1	0	0
T81	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	1311	0	0
T4	46234	345	0	0
T5	71091	0	0	0
T6	33745	357	0	0
T9	20879	158	0	0
T16	6308	0	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T51	0	140	0	0
T52	0	311	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	1071	0	0
T4	46234	285	0	0
T5	71091	0	0	0
T6	33745	297	0	0
T9	20879	128	0	0
T16	6308	0	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T51	0	110	0	0
T52	0	251	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449668574	449597889	0	0
T1	2682	2619	0	0
T2	1371	1306	0	0
T3	3898	3810	0	0
T10	23420	23331	0	0
T11	30367	30317	0	0
T12	41065	41001	0	0
T13	18032	17978	0	0
T14	1246	1170	0	0
T15	31221	31150	0	0
T17	32761	32697	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	449723040	0	0
T1	2682	2619	0	0
T2	1371	1306	0	0
T3	3898	3810	0	0
T10	23420	23331	0	0
T11	30367	30317	0	0
T12	41065	41001	0	0
T13	18032	17978	0	0
T14	1246	1170	0	0
T15	31221	31150	0	0
T17	32761	32697	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T17 T26 T28 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T17 T26 T28 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T17 T26 T28 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T16 T55 
159        1/1                    state_d = TimeoutSt;
           Tests:       T10 T16 T55 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T10 T16 T55 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T10 T16 T55 
172        1/1                    state_d    = Phase0St;
           Tests:       T55 T93 T88 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T55 T93 T88 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T55 T93 T88 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T55 T93 T88 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T10 T16 T55 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T16 T55 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T10 T16 T55 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T16 T55 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T17 T26 T28 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T17 T26 T28 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T17 T26 T28 
190        1/1                  esc_state_o = Phase0;
           Tests:       T17 T26 T28 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T17 T26 T28 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T17 T26 T28 
194        1/1                    state_d = IdleSt;
           Tests:       T35 T148 T113 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T148 T113 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T148 T113 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T17 T26 T28 
198        1/1                    state_d = Phase1St;
           Tests:       T17 T26 T28 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T17 T26 T28 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T17 T26 T28 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T17 T26 T28 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T17 T26 T28 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T17 T26 T28 
207        1/1                  esc_state_o = Phase1;
           Tests:       T17 T26 T28 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T17 T26 T28 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T17 T26 T28 
211        1/1                    state_d = IdleSt;
           Tests:       T66 T34 T116 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T66 T34 T116 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T66 T34 T116 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T17 T26 T28 
215        1/1                    state_d = Phase2St;
           Tests:       T17 T26 T28 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T17 T26 T28 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T17 T26 T28 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T17 T26 T28 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T17 T26 T28 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T17 T26 T28 
224        1/1                  esc_state_o = Phase2;
           Tests:       T17 T26 T28 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T17 T26 T28 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T17 T26 T28 
229        1/1                    state_d = IdleSt;
           Tests:       T34 T148 T109 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T148 T109 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T148 T109 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T17 T26 T28 
233        1/1                    state_d = Phase3St;
           Tests:       T17 T26 T28 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T17 T26 T28 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T17 T26 T28 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T17 T26 T28 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T17 T26 T28 
241        1/1                  esc_state_o = Phase3;
           Tests:       T17 T26 T28 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T17 T26 T28 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T17 T26 T28 
245        1/1                    state_d = IdleSt;
           Tests:       T103 T149 T150 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T103 T149 T150 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T103 T149 T150 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T17 T26 T28 
249        1/1                    state_d = TerminalSt;
           Tests:       T17 T26 T28 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T17 T26 T28 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T17 T26 T28 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T17 T26 T28 
259        1/1                  esc_state_o = Terminal;
           Tests:       T17 T26 T28 
260        1/1                  if (clr_i) begin
           Tests:       T17 T26 T28 
261        1/1                    state_d = IdleSt;
           Tests:       T17 T53 T55 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T9
1	0	Covered	T10,T17,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T17,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T17,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T10,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T26,T28

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T17,T15
1	0	1	Covered	T13,T26,T31
1	1	0	Covered	T13,T15,T16
1	1	1	Covered	T10,T16,T55

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T16,T55
0	1	Covered	T93,T88,T46
1	0	Covered	T55,T66,T151

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T10,T16,T55
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T55,T66,T151

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T16,T55
1	0	Covered	T46,T47
1	1	Covered	T93,T88,T46

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T28,T53
1	Covered	T26,T75,T53

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T26,T75
1	Covered	T28,T53,T80

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T26,T28
1	Covered	T55,T60,T61

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T26,T28,T75
1	Covered	T17,T58,T81

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T4,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T26,T75,T53

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T26,T75,T53

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T17,T26,T75

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T26,T28,T75

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T17,T26,T28
Phase1St	198	Covered	T17,T26,T28
Phase2St	215	Covered	T17,T26,T28
Phase3St	233	Covered	T17,T26,T28
TerminalSt	249	Covered	T17,T26,T28
TimeoutSt	159	Covered	T10,T16,T55

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T6,T9
IdleSt->Phase0St	152	Covered	T17,T26,T28
IdleSt->TimeoutSt	159	Covered	T10,T16,T55
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T49,T37,T106
Phase0St->Phase1St	198	Covered	T17,T26,T28
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T66,T119,T34
Phase1St->Phase2St	215	Covered	T17,T26,T28
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T34,T148,T109
Phase2St->Phase3St	233	Covered	T17,T26,T28
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T103,T149,T150
Phase3St->TerminalSt	249	Covered	T17,T26,T28
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T17,T53,T55
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T10,T16,T55
TimeoutSt->Phase0St	172	Covered	T55,T93,T88

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T26,T28
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T16,T55
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T55,T93,T88
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T16,T55
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T16,T55
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T35,T148,T113
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T17,T26,T28
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T17,T28,T53
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T66,T34,T116
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T17,T26,T28
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T17,T28,T53
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T34,T148,T109
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T17,T26,T28
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T17,T28,T53
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T103,T149,T150
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T17,T26,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T17,T28,T53
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T53,T55
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T17,T26,T28
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	449895533	244	0	0
CheckAccumTrig0_A	449895533	478	0	0
CheckAccumTrig1_A	449895533	24	0	0
CheckClr_A	449895533	204	0	0
CheckEn_A	449670456	191278277	0	0
CheckPhase0_A	449895533	527	0	0
CheckPhase1_A	449895533	517	0	0
CheckPhase2_A	449895533	509	0	0
CheckPhase3_A	449895533	504	0	0
CheckTimeout0_A	449895533	762	0	0
CheckTimeoutSt1_A	449895533	89561	0	0
CheckTimeoutSt2_A	449895533	691	0	0
CheckTimeoutStTrig_A	449895533	42	0	0
ErrorStAllEscAsserted_A	449895533	1297	0	0
ErrorStIsTerminal_A	449895533	1057	0	0
EscStateOut_A	449668574	449597889	0	0
u_state_regs_A	449895533	449723040	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	244	0	0
T4	46234	72	0	0
T5	71091	0	0	0
T6	33745	47	0	0
T9	20879	28	0	0
T16	6308	0	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T51	0	22	0	0
T52	0	75	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	478	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T12	41065	0	0	0
T15	31221	0	0	0
T16	6308	0	0	0
T17	32761	3	0	0
T26	1083	1	0	0
T27	54270	0	0	0
T28	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T58	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T75	0	1	0	0
T108	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	24	0	0
T37	0	1	0	0
T40	0	1	0	0
T55	60194	1	0	0
T56	16796	0	0	0
T57	8636	0	0	0
T58	36460	0	0	0
T59	156956	0	0	0
T66	0	3	0	0
T74	0	1	0	0
T92	22585	0	0	0
T108	3328	0	0	0
T131	86619	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	18903	0	0	0
T157	86013	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	204	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T12	41065	0	0	0
T15	31221	0	0	0
T16	6308	0	0	0
T17	32761	2	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T58	0	1	0	0
T63	0	1	0	0
T66	0	6	0	0
T80	0	1	0	0
T88	0	1	0	0
T140	0	1	0	0
T158	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449670456	191278277	0	0
T1	2682	2618	0	0
T2	1371	610	0	0
T3	3898	3809	0	0
T10	23420	2139	0	0
T11	30367	30316	0	0
T12	41065	41000	0	0
T13	18032	15117	0	0
T14	1246	806	0	0
T15	31221	24573	0	0
T17	32761	627	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	527	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T12	41065	0	0	0
T15	31221	0	0	0
T16	6308	0	0	0
T17	32761	3	0	0
T26	1083	1	0	0
T27	54270	0	0	0
T28	0	1	0	0
T53	0	2	0	0
T55	0	2	0	0
T58	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T75	0	1	0	0
T108	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	517	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T12	41065	0	0	0
T15	31221	0	0	0
T16	6308	0	0	0
T17	32761	3	0	0
T26	1083	1	0	0
T27	54270	0	0	0
T28	0	1	0	0
T53	0	2	0	0
T55	0	2	0	0
T58	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T75	0	1	0	0
T108	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	509	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T12	41065	0	0	0
T15	31221	0	0	0
T16	6308	0	0	0
T17	32761	3	0	0
T26	1083	1	0	0
T27	54270	0	0	0
T28	0	1	0	0
T53	0	2	0	0
T55	0	2	0	0
T58	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T75	0	1	0	0
T108	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	504	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T6	33745	0	0	0
T9	20879	0	0	0
T12	41065	0	0	0
T15	31221	0	0	0
T16	6308	0	0	0
T17	32761	3	0	0
T26	1083	1	0	0
T27	54270	0	0	0
T28	0	1	0	0
T53	0	2	0	0
T55	0	2	0	0
T58	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T75	0	1	0	0
T108	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	762	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T10	23420	1	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	0	0	0
T14	1246	0	0	0
T15	31221	0	0	0
T16	6308	2	0	0
T17	32761	0	0	0
T46	0	6	0	0
T49	0	7	0	0
T55	0	4	0	0
T57	0	1	0	0
T88	0	1	0	0
T93	0	2	0	0
T95	0	2	0	0
T159	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	89561	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T10	23420	120	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	0	0	0
T14	1246	0	0	0
T15	31221	0	0	0
T16	6308	142	0	0
T17	32761	0	0	0
T46	0	1481	0	0
T49	0	1072	0	0
T55	0	377	0	0
T57	0	63	0	0
T88	0	218	0	0
T93	0	358	0	0
T95	0	342	0	0
T159	0	761	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	691	0	0
T4	46234	0	0	0
T5	71091	0	0	0
T10	23420	1	0	0
T11	30367	0	0	0
T12	41065	0	0	0
T13	18032	0	0	0
T14	1246	0	0	0
T15	31221	0	0	0
T16	6308	2	0	0
T17	32761	0	0	0
T46	0	5	0	0
T49	0	7	0	0
T55	0	3	0	0
T57	0	1	0	0
T93	0	1	0	0
T95	0	2	0	0
T99	0	1	0	0
T159	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	42	0	0
T24	35843	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T63	69119	0	0	0
T86	33633	0	0	0
T87	63167	0	0	0
T88	0	1	0	0
T93	37360	1	0	0
T94	14100	0	0	0
T95	98791	0	0	0
T101	0	2	0	0
T103	0	1	0	0
T113	0	1	0	0
T121	51499	0	0	0
T144	0	1	0	0
T158	0	1	0	0
T160	0	1	0	0
T161	31807	0	0	0
T162	4652	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	1297	0	0
T4	46234	357	0	0
T5	71091	0	0	0
T6	33745	308	0	0
T9	20879	155	0	0
T16	6308	0	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T51	0	147	0	0
T52	0	330	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	1057	0	0
T4	46234	297	0	0
T5	71091	0	0	0
T6	33745	248	0	0
T9	20879	125	0	0
T16	6308	0	0	0
T26	1083	0	0	0
T27	54270	0	0	0
T28	17608	0	0	0
T29	44933	0	0	0
T30	15305	0	0	0
T51	0	117	0	0
T52	0	270	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449668574	449597889	0	0
T1	2682	2619	0	0
T2	1371	1306	0	0
T3	3898	3810	0	0
T10	23420	23331	0	0
T11	30367	30317	0	0
T12	41065	41001	0	0
T13	18032	17978	0	0
T14	1246	1170	0	0
T15	31221	31150	0	0
T17	32761	32697	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449895533	449723040	0	0
T1	2682	2619	0	0
T2	1371	1306	0	0
T3	3898	3810	0	0
T10	23420	23331	0	0
T11	30367	30317	0	0
T12	41065	41001	0	0
T13	18032	17978	0	0
T14	1246	1170	0	0
T15	31221	31150	0	0
T17	32761	32697	0	0