Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	43624	1			T15	1		T16	221		T17	3
class_i[0x1]	40760	1			T16	6		T54	295		T40	599
class_i[0x2]	49519	1			T16	6		T19	1		T36	106
class_i[0x3]	48475	1			T15	5		T54	18		T17	3

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	44590	1			T15	5		T16	101		T17	1
alert[0x1]	47817	1			T16	1		T54	300		T17	1
alert[0x2]	44151	1			T15	1		T16	5		T54	10
alert[0x3]	45820	1			T16	126		T54	3		T40	352

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

182146

1

T15

6

T16

233

T54

313

esc_ping_fail

232

1

T17

3

T18

2

T19

1

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	44522	1			T15	5		T16	101		T40	203
esc_integrity_fail	alert[0x1]	47759	1			T16	1		T54	300		T40	22
esc_integrity_fail	alert[0x2]	44098	1			T15	1		T16	5		T54	10
esc_integrity_fail	alert[0x3]	45767	1			T16	126		T54	3		T40	352
esc_ping_fail	alert[0x0]	68	1			T17	1		T116	1		T305	1
esc_ping_fail	alert[0x1]	58	1			T17	1		T18	1		T116	1
esc_ping_fail	alert[0x2]	53	1			T17	1		T116	2		T79	2
esc_ping_fail	alert[0x3]	53	1			T18	1		T19	1		T116	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	43571	1			T15	1		T16	221		T57	2
esc_integrity_fail	class_i[0x1]	40688	1			T16	6		T54	295		T40	599
esc_integrity_fail	class_i[0x2]	49458	1			T16	6		T36	106		T110	18
esc_integrity_fail	class_i[0x3]	48429	1			T15	5		T54	18		T17	3
esc_ping_fail	class_i[0x0]	53	1			T17	3		T305	1		T79	1
esc_ping_fail	class_i[0x1]	72	1			T18	2		T116	2		T79	6
esc_ping_fail	class_i[0x2]	61	1			T19	1		T80	1		T31	3
esc_ping_fail	class_i[0x3]	46	1			T116	3		T305	1		T80	1