Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	522575150	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	522575150	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	522575150	522391987	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	522575150	522391987	0	0
tb.dut.EdnKnownO_A	0	0	522575150	522391987	0	0
tb.dut.EscPKnownO_A	0	0	522575150	522391987	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	522575150	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	522575150	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	522575150	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	522575150	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	522575150	90	0	0
tb.dut.IrqAKnownO_A	0	0	522575150	522391987	0	0
tb.dut.IrqBKnownO_A	0	0	522575150	522391987	0	0
tb.dut.IrqCKnownO_A	0	0	522575150	522391987	0	0
tb.dut.IrqDKnownO_A	0	0	522575150	522391987	0	0
tb.dut.TlAReadyKnownO_A	0	0	522575150	522391987	0	0
tb.dut.TlDValidKnownO_A	0	0	522575150	522391987	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	549833936	221715	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	549833936	17454	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	549833936	18728	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	549833936	16533	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	549833936	16480	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	549833936	16492	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	549833936	18187	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	549833936	18615	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	549833936	18862	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	549833936	17811	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	549833936	16380	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	549833936	16428	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	549833936	16340	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	549833936	18685	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	549833936	18376	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	549833936	16745	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	549833936	17590	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	549833936	17619	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	549833936	19956	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	549833936	16395	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	549833936	18497	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	549833936	16465	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	549833936	16578	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	549833936	16195	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	549833936	17483	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	549833936	18644	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	549833936	18696	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	549833936	17506	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	549833936	16258	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	549833936	16446	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	549833936	17492	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	549833936	16326	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	549833936	17754	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	549833936	19801	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	549833936	17166	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	549833936	17438	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	549833936	16872	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	549833936	16274	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	549833936	18788	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	549833936	17593	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	549833936	16303	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	549833936	17436	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	549833936	19186	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	549833936	16313	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	549833936	18885	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	549833936	17477	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	549833936	16372	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	549833936	16628	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	549833936	18156	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	549833936	16544	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	549833936	17439	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	549833936	18665	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	549833936	17629	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	549833936	16524	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	549833936	16408	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	549833936	16406	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	549833936	16419	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	549833936	16628	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	549833936	16281	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	549833936	16408	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	549833936	18598	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	549833936	16440	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	549833936	16449	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	549833936	18655	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	549833936	17634	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	549833936	17716	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	549833936	18895	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	549833936	17717	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	549833936	16521	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	549833936	16629	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	549833936	33580	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	549833936	16487	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	549833936	17645	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	549833936	17940	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	549833936	17250	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	549833936	17787	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	549833936	17316	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	549833936	16631	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	549833936	16774	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	522575150	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	522575150	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	522575150	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	522575150	4716	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	522575150	176281	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	522575150	260715093	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	522575150	311	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	522575150	798	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	522575150	39	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	522575150	383	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	522259646	220880420	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	522575150	876	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	522575150	841	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	522575150	817	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	522575150	801	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	522575150	1590	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	522575150	145565	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	522575150	1482	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	522575150	65	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	522575150	1427	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	522575150	1157	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	522257289	522188435	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	522575150	522391987	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	522575150	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	522575150	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	522575150	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	522575150	4170	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	522575150	140040	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	522575150	303827954	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	522575150	290	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	522575150	474	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	522575150	24	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	522575150	201	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	522259646	228054582	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	522575150	533	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	522575150	523	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	522575150	514	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	522575150	505	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	522575150	926	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	522575150	89038	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	522575150	839	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	522575150	53	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	522575150	1475	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	522575150	1205	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	522257289	522188435	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	522575150	522391987	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	522575150	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	522575150	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	522575150	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	522575150	3211	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	522575150	149071	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	522575150	300327965	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	522575150	273	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	522575150	486	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	522575150	18	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	522575150	202	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	522259646	236059736	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	522575150	525	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	522575150	514	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	522575150	508	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	522575150	499	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	522575150	1198	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	522575150	103150	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	522575150	1143	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	522575150	35	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	522575150	1488	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	522575150	1218	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	522257289	522188435	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	522575150	522391987	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	522575150	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	522575150	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	522575150	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	522575150	2676	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	522575150	149774	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	522575150	300965324	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	522575150	284	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	522575150	458	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	522575150	26	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	522575150	211	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	522259646	239973324	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	522575150	512	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	522575150	500	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	522575150	487	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	522575150	479	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	522575150	1082	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	522575150	112582	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	522575150	1005	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	522575150	45	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	522575150	1472	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	522575150	1202	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	522257289	522188435	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	522575150	522391987	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	549833936	82846089	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	549833936	549126685	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	549833936	549126685	0	0
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