Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	8	32	80.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	8	32	80.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	65	1			T15	1		T38	1		T84	1
class_index[0x1]	53	1			T10	1		T16	1		T75	1
class_index[0x2]	35	1			T40	1		T91	1		T93	1
class_index[0x3]	45	1			T57	1		T75	1		T87	6

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	92	1			T10	1		T84	1		T87	6
intr_timeout_cnt[1]	36	1			T15	1		T38	1		T57	1
intr_timeout_cnt[2]	21	1			T57	1		T63	1		T64	1
intr_timeout_cnt[3]	15	1			T16	1		T89	1		T136	1
intr_timeout_cnt[4]	7	1			T75	1		T72	1		T237	1
intr_timeout_cnt[5]	7	1			T40	1		T238	1		T239	1
intr_timeout_cnt[6]	4	1			T240	1		T241	1		T242	1
intr_timeout_cnt[7]	6	1			T36	1		T137	2		T243	1
intr_timeout_cnt[8]	8	1			T90	1		T131	1		T107	2
intr_timeout_cnt[9]	2	1			T92	1		T244	1		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	8	32	80.00	8

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[4] , intr_timeout_cnt[5]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T84	1		T78	1		T64	1
class_index[0x0]	intr_timeout_cnt[1]	21	1			T15	1		T38	1		T57	1
class_index[0x0]	intr_timeout_cnt[2]	3	1			T63	1		T108	1		T99	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T105	1		T107	1		T245	1
class_index[0x0]	intr_timeout_cnt[4]	1	1			T72	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[5]	3	1			T239	1		T246	1		T247	1
class_index[0x0]	intr_timeout_cnt[6]	1	1			T248	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T131	1		T249	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	18	1			T10	1		T41	1		T65	1
class_index[0x1]	intr_timeout_cnt[1]	6	1			T87	1		T36	1		T91	1
class_index[0x1]	intr_timeout_cnt[2]	9	1			T64	1		T250	1		T105	1
class_index[0x1]	intr_timeout_cnt[3]	7	1			T16	1		T89	1		T137	3
class_index[0x1]	intr_timeout_cnt[4]	4	1			T75	1		T251	1		T252	1
class_index[0x1]	intr_timeout_cnt[5]	1	1			T253	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T241	1		T242	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T254	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	3	1			T255	2		T256	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T92	1		T244	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	20	1			T91	1		T93	1		T71	1
class_index[0x2]	intr_timeout_cnt[1]	2	1			T119	1		T254	1		-	-
class_index[0x2]	intr_timeout_cnt[2]	5	1			T122	1		T257	1		T252	1
class_index[0x2]	intr_timeout_cnt[3]	1	1			T118	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	2	1			T237	1		T258	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	3	1			T40	1		T238	1		T259	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T243	1		T252	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	24	1			T87	6		T37	1		T93	1
class_index[0x3]	intr_timeout_cnt[1]	7	1			T75	1		T41	1		T90	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T57	1		T245	1		T252	1
class_index[0x3]	intr_timeout_cnt[3]	3	1			T136	1		T90	1		T131	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T240	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	3	1			T36	1		T137	2		-	-
class_index[0x3]	intr_timeout_cnt[8]	3	1			T90	1		T107	2		-	-