Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	292747	1			T1	3		T9	17		T15	7
all_values[1]	292747	1			T1	3		T9	17		T15	7
all_values[2]	292747	1			T1	3		T9	17		T15	7
all_values[3]	292747	1			T1	3		T9	17		T15	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

583004

1

T1

6

T9

30

T15

13

auto[1]

587984

1

T1

6

T9

38

T15

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

699938

1

T1

8

T9

37

T15

10

auto[1]

471050

1

T1

4

T9

31

T15

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	85590	1			T9	4		T15	2		T10	6
all_values[0]	auto[0]	auto[1]	60461	1			T9	3		T15	2		T10	5
all_values[0]	auto[1]	auto[0]	86239	1			T1	2		T9	5		T10	7
all_values[0]	auto[1]	auto[1]	60457	1			T1	1		T9	5		T15	3
all_values[1]	auto[0]	auto[0]	88436	1			T1	2		T9	5		T10	8
all_values[1]	auto[0]	auto[1]	57845	1			T1	1		T9	4		T15	2
all_values[1]	auto[1]	auto[0]	89025	1			T9	4		T15	3		T10	5
all_values[1]	auto[1]	auto[1]	57441	1			T9	4		T15	2		T10	5
all_values[2]	auto[0]	auto[0]	86385	1			T9	4		T15	1		T10	8
all_values[2]	auto[0]	auto[1]	59211	1			T9	3		T15	2		T10	7
all_values[2]	auto[1]	auto[0]	87819	1			T1	2		T9	5		T15	2
all_values[2]	auto[1]	auto[1]	59332	1			T1	1		T9	5		T15	2
all_values[3]	auto[0]	auto[0]	87416	1			T1	2		T9	4		T15	1
all_values[3]	auto[0]	auto[1]	57660	1			T1	1		T9	3		T15	3
all_values[3]	auto[1]	auto[0]	89028	1			T9	6		T15	1		T10	7
all_values[3]	auto[1]	auto[1]	58643	1			T9	4		T15	2		T10	6