Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	292747	1			T1	3		T9	17		T15	7
all_pins[1]	292747	1			T1	3		T9	17		T15	7
all_pins[2]	292747	1			T1	3		T9	17		T15	7
all_pins[3]	292747	1			T1	3		T9	17		T15	7

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	935115	1			T1	10		T9	50		T15	19
values[0x1]	235873	1			T1	2		T9	18		T15	9
transitions[0x0=>0x1]	157883	1			T1	1		T9	9		T15	7
transitions[0x1=>0x0]	158127	1			T1	2		T9	10		T15	8

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	232290	1			T1	2		T9	12		T15	4
all_pins[0]	values[0x1]	60457	1			T1	1		T9	5		T15	3
all_pins[0]	transitions[0x0=>0x1]	59938	1			T9	4		T15	2		T10	7
all_pins[0]	transitions[0x1=>0x0]	58368	1			T9	4		T15	2		T10	6
all_pins[1]	values[0x0]	235306	1			T1	3		T9	13		T15	5
all_pins[1]	values[0x1]	57441	1			T9	4		T15	2		T10	5
all_pins[1]	transitions[0x0=>0x1]	32197	1			T9	2		T15	1		T10	1
all_pins[1]	transitions[0x1=>0x0]	35213	1			T1	1		T9	3		T15	2
all_pins[2]	values[0x0]	233415	1			T1	2		T9	12		T15	5
all_pins[2]	values[0x1]	59332	1			T1	1		T9	5		T15	2
all_pins[2]	transitions[0x0=>0x1]	33456	1			T1	1		T9	2		T15	2
all_pins[2]	transitions[0x1=>0x0]	31565	1			T9	1		T15	2		T10	3
all_pins[3]	values[0x0]	234104	1			T1	3		T9	13		T15	5
all_pins[3]	values[0x1]	58643	1			T9	4		T15	2		T10	6
all_pins[3]	transitions[0x0=>0x1]	32292	1			T9	1		T15	2		T10	3
all_pins[3]	transitions[0x1=>0x0]	32981	1			T1	1		T9	2		T15	2