Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	79341	1			T69	71		T268	774		T230	484
accum_cnt_1000	184355	1			T16	7		T54	1		T134	11
accum_cnt_100	22817	1			T54	5		T48	8		T85	4
accum_cnt_50	44751	1			T9	1		T10	8		T25	2
accum_cnt_10	146707	1			T1	4		T9	12		T15	20
accum_cnt_0	356786	1			T1	4		T9	19		T15	16

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	216936	1			T1	2		T9	8		T15	9
class_index[0x1]	216936	1			T1	2		T9	8		T15	9
class_index[0x2]	216936	1			T1	2		T9	8		T15	9
class_index[0x3]	216936	1			T1	2		T9	8		T15	9

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22502	1			T268	355		T94	129		T301	316
class_index[0x0]	accum_cnt_1000	45450	1			T16	7		T113	1		T302	41
class_index[0x0]	accum_cnt_100	5229	1			T48	8		T85	4		T215	8
class_index[0x0]	accum_cnt_50	12149	1			T9	1		T25	2		T26	10
class_index[0x0]	accum_cnt_10	34475	1			T1	2		T9	3		T15	8
class_index[0x0]	accum_cnt_0	85434	1			T9	4		T15	1		T10	4
class_index[0x1]	accum_cnt_2000	19011	1			T268	419		T124	92		T102	548
class_index[0x1]	accum_cnt_1000	43790	1			T113	2		T29	35		T260	51
class_index[0x1]	accum_cnt_100	6002	1			T134	14		T303	9		T113	22
class_index[0x1]	accum_cnt_50	12213	1			T10	8		T16	4		T83	2
class_index[0x1]	accum_cnt_10	42071	1			T9	5		T15	9		T10	12
class_index[0x1]	accum_cnt_0	85844	1			T1	2		T9	3		T10	4
class_index[0x2]	accum_cnt_2000	19061	1			T69	71		T230	484		T94	180
class_index[0x2]	accum_cnt_1000	47342	1			T54	1		T302	43		T260	29
class_index[0x2]	accum_cnt_100	6351	1			T54	5		T36	1		T302	22
class_index[0x2]	accum_cnt_50	9659	1			T16	9		T54	3		T49	9
class_index[0x2]	accum_cnt_10	36006	1			T9	3		T15	3		T10	24
class_index[0x2]	accum_cnt_0	91985	1			T1	2		T9	5		T15	6
class_index[0x3]	accum_cnt_2000	18767	1			T94	28		T124	264		T97	610
class_index[0x3]	accum_cnt_1000	47773	1			T134	11		T104	1		T200	33
class_index[0x3]	accum_cnt_100	5235	1			T134	19		T303	5		T200	19
class_index[0x3]	accum_cnt_50	10730	1			T38	3		T14	4		T54	10
class_index[0x3]	accum_cnt_10	34155	1			T1	2		T9	1		T10	14
class_index[0x3]	accum_cnt_0	93523	1			T9	7		T15	9		T10	10