Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3223	1			T54	2		T61	1		T305	1
alert[0x1]	5739	1			T306	1		T307	11		T127	210
alert[0x2]	2773	1			T75	34		T116	1		T90	1
alert[0x3]	4642	1			T79	1		T41	3		T63	1
alert[0x4]	6123	1			T110	2		T29	5		T79	1
alert[0x5]	4524	1			T15	7		T54	1		T57	2
alert[0x6]	4930	1			T16	8		T116	1		T136	1
alert[0x7]	3470	1			T31	1		T266	1		T136	19
alert[0x8]	5923	1			T54	7		T36	2		T305	2
alert[0x9]	7565	1			T54	13		T116	1		T305	1
alert[0xa]	1545	1			T308	1		T67	2		T309	1
alert[0xb]	4659	1			T61	3		T116	1		T41	4
alert[0xc]	2637	1			T29	3		T41	5		T67	1
alert[0xd]	3221	1			T57	12		T36	2		T110	6
alert[0xe]	3395	1			T54	3		T29	1		T79	1
alert[0xf]	5926	1			T231	3		T96	1		T69	17
alert[0x10]	5956	1			T18	1		T80	1		T63	6
alert[0x11]	2534	1			T54	1		T110	2		T266	1
alert[0x12]	3677	1			T19	1		T79	1		T308	1
alert[0x13]	6012	1			T57	12		T75	3		T116	1
alert[0x14]	2957	1			T31	1		T69	13		T306	1
alert[0x15]	4579	1			T19	1		T61	1		T64	2
alert[0x16]	2593	1			T308	1		T90	3		T69	22
alert[0x17]	3874	1			T116	1		T29	72		T41	17
alert[0x18]	5993	1			T54	1		T29	2		T69	151
alert[0x19]	8451	1			T75	10		T104	2		T70	2
alert[0x1a]	1603	1			T61	1		T309	1		T310	1
alert[0x1b]	2661	1			T54	88		T41	1		T90	3
alert[0x1c]	1275	1			T57	2		T266	1		T64	8
alert[0x1d]	3103	1			T308	1		T90	15		T307	124
alert[0x1e]	2152	1			T15	46		T61	8		T41	1
alert[0x1f]	3308	1			T41	3		T69	33		T70	20
alert[0x20]	9616	1			T18	1		T69	11		T306	1
alert[0x21]	3065	1			T130	11		T311	2		T70	1
alert[0x22]	9999	1			T64	2		T136	1		T130	19
alert[0x23]	1985	1			T15	1		T17	1		T75	3
alert[0x24]	6344	1			T15	1		T16	3		T266	1
alert[0x25]	8353	1			T18	1		T19	1		T64	35
alert[0x26]	10556	1			T309	1		T96	1		T306	1
alert[0x27]	7572	1			T63	8		T266	1		T69	62
alert[0x28]	6464	1			T36	2		T41	5		T266	1
alert[0x29]	4509	1			T36	43		T80	1		T309	2
alert[0x2a]	4446	1			T90	111		T67	45		T96	1
alert[0x2b]	2688	1			T75	2		T18	1		T231	27
alert[0x2c]	1913	1			T116	1		T308	1		T67	2
alert[0x2d]	2736	1			T17	1		T80	1		T96	1
alert[0x2e]	5009	1			T61	1		T310	1		T70	4
alert[0x2f]	4199	1			T54	12		T61	4		T231	2
alert[0x30]	2577	1			T266	1		T69	19		T70	2
alert[0x31]	3366	1			T19	1		T308	1		T69	272
alert[0x32]	914	1			T231	6		T136	4		T90	2
alert[0x33]	2819	1			T29	3		T41	4		T63	1
alert[0x34]	6488	1			T231	1		T31	1		T69	459
alert[0x35]	1631	1			T19	1		T110	3		T312	1
alert[0x36]	2057	1			T110	1		T29	3		T80	1
alert[0x37]	987	1			T18	1		T19	1		T116	1
alert[0x38]	5256	1			T17	1		T110	3		T231	2
alert[0x39]	5074	1			T75	7		T61	36		T41	84
alert[0x3a]	823	1			T57	29		T61	4		T64	11
alert[0x3b]	4957	1			T61	1		T29	1		T79	1
alert[0x3c]	4806	1			T79	1		T69	26		T310	2
alert[0x3d]	5165	1			T231	41		T266	1		T69	71
alert[0x3e]	2198	1			T29	1		T41	8		T310	2
alert[0x3f]	4800	1			T15	22		T31	1		T313	1
alert[0x40]	2928	1			T305	1		T63	5		T308	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	54672	1			T104	2		T110	12		T116	1
class_i[0x1]	55140	1			T54	16		T17	2		T75	59
class_i[0x2]	89516	1			T16	11		T54	112		T57	31
class_i[0x3]	77995	1			T15	77		T17	1		T57	26

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

276695

1

T15

77

T16

11

T54

128

alert_ping_fail

628

1

T17

3

T18

5

T19

6

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3216	1			T54	2		T61	1		T231	12
alert_integrity_fail	alert[0x1]	5735	1			T307	11		T127	210		T121	5
alert_integrity_fail	alert[0x2]	2768	1			T75	34		T90	1		T127	27
alert_integrity_fail	alert[0x3]	4628	1			T41	3		T63	1		T69	717
alert_integrity_fail	alert[0x4]	6113	1			T110	2		T29	5		T67	2
alert_integrity_fail	alert[0x5]	4510	1			T15	7		T54	1		T57	2
alert_integrity_fail	alert[0x6]	4914	1			T16	8		T136	1		T139	277
alert_integrity_fail	alert[0x7]	3455	1			T136	19		T70	4		T139	129
alert_integrity_fail	alert[0x8]	5912	1			T54	7		T36	2		T41	8
alert_integrity_fail	alert[0x9]	7555	1			T54	13		T69	68		T70	2
alert_integrity_fail	alert[0xa]	1531	1			T67	2		T69	267		T70	25
alert_integrity_fail	alert[0xb]	4649	1			T61	3		T41	4		T130	3
alert_integrity_fail	alert[0xc]	2633	1			T29	3		T41	5		T67	1
alert_integrity_fail	alert[0xd]	3213	1			T57	12		T36	2		T110	6
alert_integrity_fail	alert[0xe]	3391	1			T54	3		T29	1		T130	1
alert_integrity_fail	alert[0xf]	5921	1			T231	3		T69	17		T307	17
alert_integrity_fail	alert[0x10]	5950	1			T63	6		T69	58		T230	1
alert_integrity_fail	alert[0x11]	2523	1			T54	1		T110	2		T314	13
alert_integrity_fail	alert[0x12]	3660	1			T92	23		T307	22		T119	260
alert_integrity_fail	alert[0x13]	6001	1			T57	12		T75	3		T90	20
alert_integrity_fail	alert[0x14]	2950	1			T69	13		T307	35		T132	696
alert_integrity_fail	alert[0x15]	4571	1			T61	1		T64	2		T130	11
alert_integrity_fail	alert[0x16]	2586	1			T90	3		T69	22		T70	1
alert_integrity_fail	alert[0x17]	3865	1			T29	72		T41	17		T90	2
alert_integrity_fail	alert[0x18]	5983	1			T54	1		T29	2		T69	151
alert_integrity_fail	alert[0x19]	8441	1			T75	10		T104	2		T70	2
alert_integrity_fail	alert[0x1a]	1594	1			T61	1		T130	19		T70	1
alert_integrity_fail	alert[0x1b]	2654	1			T54	88		T41	1		T90	3
alert_integrity_fail	alert[0x1c]	1260	1			T57	2		T64	8		T130	15
alert_integrity_fail	alert[0x1d]	3094	1			T90	15		T307	124		T119	9
alert_integrity_fail	alert[0x1e]	2141	1			T15	46		T61	8		T41	1
alert_integrity_fail	alert[0x1f]	3299	1			T41	3		T69	33		T70	20
alert_integrity_fail	alert[0x20]	9604	1			T69	11		T70	1		T139	173
alert_integrity_fail	alert[0x21]	3055	1			T130	11		T70	1		T93	1014
alert_integrity_fail	alert[0x22]	9991	1			T64	2		T136	1		T130	19
alert_integrity_fail	alert[0x23]	1976	1			T15	1		T75	3		T69	33
alert_integrity_fail	alert[0x24]	6334	1			T15	1		T16	3		T90	4
alert_integrity_fail	alert[0x25]	8345	1			T64	35		T69	66		T130	4
alert_integrity_fail	alert[0x26]	10547	1			T70	1		T93	285		T139	516
alert_integrity_fail	alert[0x27]	7566	1			T63	8		T69	62		T139	887
alert_integrity_fail	alert[0x28]	6450	1			T36	2		T41	5		T315	5
alert_integrity_fail	alert[0x29]	4501	1			T36	43		T139	44		T121	32
alert_integrity_fail	alert[0x2a]	4437	1			T90	111		T67	45		T139	142
alert_integrity_fail	alert[0x2b]	2675	1			T75	2		T231	27		T67	2
alert_integrity_fail	alert[0x2c]	1898	1			T67	2		T69	10		T70	8
alert_integrity_fail	alert[0x2d]	2727	1			T132	1144		T127	29		T72	11
alert_integrity_fail	alert[0x2e]	5001	1			T61	1		T70	4		T240	9
alert_integrity_fail	alert[0x2f]	4185	1			T54	12		T61	4		T231	2
alert_integrity_fail	alert[0x30]	2567	1			T69	19		T70	2		T93	80
alert_integrity_fail	alert[0x31]	3351	1			T69	272		T93	15		T139	53
alert_integrity_fail	alert[0x32]	907	1			T231	6		T136	4		T90	2
alert_integrity_fail	alert[0x33]	2811	1			T29	3		T41	4		T63	1
alert_integrity_fail	alert[0x34]	6482	1			T231	1		T69	459		T230	2
alert_integrity_fail	alert[0x35]	1620	1			T110	3		T71	1		T307	60
alert_integrity_fail	alert[0x36]	2046	1			T110	1		T29	3		T130	12
alert_integrity_fail	alert[0x37]	968	1			T63	6		T90	1		T70	2
alert_integrity_fail	alert[0x38]	5246	1			T110	3		T231	2		T90	1
alert_integrity_fail	alert[0x39]	5069	1			T75	7		T61	36		T41	84
alert_integrity_fail	alert[0x3a]	816	1			T57	29		T61	4		T64	11
alert_integrity_fail	alert[0x3b]	4950	1			T61	1		T29	1		T41	1
alert_integrity_fail	alert[0x3c]	4793	1			T69	26		T70	2		T139	1348
alert_integrity_fail	alert[0x3d]	5155	1			T231	41		T69	71		T70	19
alert_integrity_fail	alert[0x3e]	2188	1			T29	1		T41	8		T139	383
alert_integrity_fail	alert[0x3f]	4795	1			T15	22		T139	4		T315	3
alert_integrity_fail	alert[0x40]	2923	1			T63	5		T130	2		T70	1
alert_ping_fail	alert[0x0]	7	1			T305	1		T266	1		T316	1
alert_ping_fail	alert[0x1]	4	1			T306	1		T317	1		T318	1
alert_ping_fail	alert[0x2]	5	1			T116	1		T310	1		T317	1
alert_ping_fail	alert[0x3]	14	1			T79	1		T266	1		T309	1
alert_ping_fail	alert[0x4]	10	1			T79	1		T266	1		T311	1
alert_ping_fail	alert[0x5]	14	1			T266	2		T309	1		T311	1
alert_ping_fail	alert[0x6]	16	1			T116	1		T306	1		T310	1
alert_ping_fail	alert[0x7]	15	1			T31	1		T266	1		T312	1
alert_ping_fail	alert[0x8]	11	1			T305	2		T311	3		T312	1
alert_ping_fail	alert[0x9]	10	1			T116	1		T305	1		T31	1
alert_ping_fail	alert[0xa]	14	1			T308	1		T309	1		T294	1
alert_ping_fail	alert[0xb]	10	1			T116	1		T96	1		T319	1
alert_ping_fail	alert[0xc]	4	1			T320	1		T321	1		T322	1
alert_ping_fail	alert[0xd]	8	1			T305	1		T266	1		T312	1
alert_ping_fail	alert[0xe]	4	1			T79	1		T323	1		T322	1
alert_ping_fail	alert[0xf]	5	1			T96	1		T324	1		T319	1
alert_ping_fail	alert[0x10]	6	1			T18	1		T80	1		T31	1
alert_ping_fail	alert[0x11]	11	1			T266	1		T306	1		T310	1
alert_ping_fail	alert[0x12]	17	1			T19	1		T79	1		T308	1
alert_ping_fail	alert[0x13]	11	1			T116	1		T320	1		T321	1
alert_ping_fail	alert[0x14]	7	1			T31	1		T306	1		T320	1
alert_ping_fail	alert[0x15]	8	1			T19	1		T311	1		T325	1
alert_ping_fail	alert[0x16]	7	1			T308	1		T326	1		T317	1
alert_ping_fail	alert[0x17]	9	1			T116	1		T266	1		T327	1
alert_ping_fail	alert[0x18]	10	1			T313	1		T328	1		T329	1
alert_ping_fail	alert[0x19]	10	1			T312	1		T316	1		T319	1
alert_ping_fail	alert[0x1a]	9	1			T309	1		T310	1		T316	1
alert_ping_fail	alert[0x1b]	7	1			T311	1		T312	2		T316	1
alert_ping_fail	alert[0x1c]	15	1			T266	1		T306	1		T310	1
alert_ping_fail	alert[0x1d]	9	1			T308	1		T321	1		T319	1
alert_ping_fail	alert[0x1e]	11	1			T308	2		T312	1		T324	1
alert_ping_fail	alert[0x1f]	9	1			T320	1		T327	1		T330	1
alert_ping_fail	alert[0x20]	12	1			T18	1		T306	1		T331	1
alert_ping_fail	alert[0x21]	10	1			T311	2		T316	1		T331	1
alert_ping_fail	alert[0x22]	8	1			T297	1		T300	1		T332	1
alert_ping_fail	alert[0x23]	9	1			T17	1		T308	1		T310	1
alert_ping_fail	alert[0x24]	10	1			T266	1		T306	1		T321	1
alert_ping_fail	alert[0x25]	8	1			T18	1		T19	1		T311	1
alert_ping_fail	alert[0x26]	9	1			T309	1		T96	1		T306	1
alert_ping_fail	alert[0x27]	6	1			T266	1		T325	1		T333	1
alert_ping_fail	alert[0x28]	14	1			T266	1		T96	1		T306	1
alert_ping_fail	alert[0x29]	8	1			T80	1		T309	2		T311	3
alert_ping_fail	alert[0x2a]	9	1			T96	1		T312	1		T296	2
alert_ping_fail	alert[0x2b]	13	1			T18	1		T308	1		T311	1
alert_ping_fail	alert[0x2c]	15	1			T116	1		T308	1		T309	1
alert_ping_fail	alert[0x2d]	9	1			T17	1		T80	1		T96	1
alert_ping_fail	alert[0x2e]	8	1			T310	1		T312	1		T313	1
alert_ping_fail	alert[0x2f]	14	1			T80	1		T306	1		T310	1
alert_ping_fail	alert[0x30]	10	1			T266	1		T321	2		T334	1
alert_ping_fail	alert[0x31]	15	1			T19	1		T308	1		T306	2
alert_ping_fail	alert[0x32]	7	1			T96	1		T306	1		T310	1
alert_ping_fail	alert[0x33]	8	1			T266	1		T306	1		T324	1
alert_ping_fail	alert[0x34]	6	1			T31	1		T319	2		T323	1
alert_ping_fail	alert[0x35]	11	1			T19	1		T312	1		T313	1
alert_ping_fail	alert[0x36]	11	1			T80	1		T308	1		T96	1
alert_ping_fail	alert[0x37]	19	1			T18	1		T19	1		T116	1
alert_ping_fail	alert[0x38]	10	1			T17	1		T31	1		T306	1
alert_ping_fail	alert[0x39]	5	1			T310	1		T311	1		T312	1
alert_ping_fail	alert[0x3a]	7	1			T309	1		T96	1		T306	1
alert_ping_fail	alert[0x3b]	7	1			T79	1		T306	1		T328	1
alert_ping_fail	alert[0x3c]	13	1			T79	1		T310	2		T321	1
alert_ping_fail	alert[0x3d]	10	1			T266	1		T311	1		T321	1
alert_ping_fail	alert[0x3e]	10	1			T310	2		T311	1		T325	1
alert_ping_fail	alert[0x3f]	5	1			T31	1		T313	1		T335	1
alert_ping_fail	alert[0x40]	5	1			T305	1		T308	1		T306	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	54527	1			T104	2		T110	12		T29	96
alert_integrity_fail	class_i[0x1]	55040	1			T54	16		T75	59		T36	20
alert_integrity_fail	class_i[0x2]	89308	1			T16	11		T54	112		T57	31
alert_integrity_fail	class_i[0x3]	77820	1			T15	77		T57	26		T36	29
alert_ping_fail	class_i[0x0]	145	1			T116	1		T305	1		T80	1
alert_ping_fail	class_i[0x1]	100	1			T17	2		T116	7		T308	2
alert_ping_fail	class_i[0x2]	208	1			T19	6		T305	5		T80	1
alert_ping_fail	class_i[0x3]	175	1			T17	1		T18	5		T79	8