| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.21 | 99.99 | 98.69 | 97.09 | 100.00 | 100.00 | 99.38 | 99.32 |
| T783 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.4162328596 | Aug 27 04:49:09 PM UTC 24 | Aug 27 04:50:24 PM UTC 24 | 2729791496 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2833681966 | Aug 27 04:50:02 PM UTC 24 | Aug 27 04:50:25 PM UTC 24 | 803656722 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.4022466898 | Aug 27 04:42:11 PM UTC 24 | Aug 27 04:50:27 PM UTC 24 | 3135602275 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.2036295145 | Aug 27 04:50:24 PM UTC 24 | Aug 27 04:50:28 PM UTC 24 | 15078687 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1093266889 | Aug 27 04:46:24 PM UTC 24 | Aug 27 04:50:31 PM UTC 24 | 4849841276 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.3453706219 | Aug 27 04:50:27 PM UTC 24 | Aug 27 04:50:35 PM UTC 24 | 32770254 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1162327741 | Aug 27 04:50:28 PM UTC 24 | Aug 27 04:50:43 PM UTC 24 | 63658966 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1032689108 | Aug 27 04:50:28 PM UTC 24 | Aug 27 04:50:47 PM UTC 24 | 368067354 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.2334493977 | Aug 27 04:50:47 PM UTC 24 | Aug 27 04:50:51 PM UTC 24 | 10242921 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3457944944 | Aug 27 04:50:21 PM UTC 24 | Aug 27 04:50:57 PM UTC 24 | 2194995777 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.1382404385 | Aug 27 04:50:20 PM UTC 24 | Aug 27 04:51:02 PM UTC 24 | 381467664 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.442404961 | Aug 27 04:50:52 PM UTC 24 | Aug 27 04:51:05 PM UTC 24 | 97632995 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.1600678768 | Aug 27 04:50:41 PM UTC 24 | Aug 27 04:51:09 PM UTC 24 | 132272149 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2847639918 | Aug 27 04:49:58 PM UTC 24 | Aug 27 04:51:14 PM UTC 24 | 1335915246 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3068282606 | Aug 27 04:51:03 PM UTC 24 | Aug 27 04:51:17 PM UTC 24 | 59428082 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3557564856 | Aug 27 04:43:55 PM UTC 24 | Aug 27 04:51:19 PM UTC 24 | 18449386679 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.4181704850 | Aug 27 04:50:58 PM UTC 24 | Aug 27 04:51:20 PM UTC 24 | 86262778 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.1651604088 | Aug 27 04:51:17 PM UTC 24 | Aug 27 04:51:21 PM UTC 24 | 6218320 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.549867325 | Aug 27 04:44:42 PM UTC 24 | Aug 27 04:51:21 PM UTC 24 | 3997829895 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.2271352507 | Aug 27 04:51:22 PM UTC 24 | Aug 27 04:51:25 PM UTC 24 | 6243488 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.601372941 | Aug 27 04:51:26 PM UTC 24 | Aug 27 04:51:29 PM UTC 24 | 9077879 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.2724884326 | Aug 27 04:51:20 PM UTC 24 | Aug 27 04:51:30 PM UTC 24 | 33975836 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3125725882 | Aug 27 04:51:17 PM UTC 24 | Aug 27 04:51:32 PM UTC 24 | 195392490 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.866397116 | Aug 27 04:51:31 PM UTC 24 | Aug 27 04:51:34 PM UTC 24 | 11844090 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.1910903066 | Aug 27 04:51:31 PM UTC 24 | Aug 27 04:51:34 PM UTC 24 | 15273305 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.526930805 | Aug 27 04:51:33 PM UTC 24 | Aug 27 04:51:36 PM UTC 24 | 12767534 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.1316238230 | Aug 27 04:51:35 PM UTC 24 | Aug 27 04:51:39 PM UTC 24 | 8302361 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.2281971052 | Aug 27 04:51:35 PM UTC 24 | Aug 27 04:51:39 PM UTC 24 | 8213149 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3927258541 | Aug 27 04:51:22 PM UTC 24 | Aug 27 04:51:41 PM UTC 24 | 242264080 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.3166420033 | Aug 27 04:51:37 PM UTC 24 | Aug 27 04:51:41 PM UTC 24 | 9535404 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.606043148 | Aug 27 04:51:17 PM UTC 24 | Aug 27 04:51:42 PM UTC 24 | 1054752711 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.699361275 | Aug 27 04:51:40 PM UTC 24 | Aug 27 04:51:43 PM UTC 24 | 10708904 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2647229725 | Aug 27 04:51:40 PM UTC 24 | Aug 27 04:51:43 PM UTC 24 | 13440979 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.1255473801 | Aug 27 04:51:42 PM UTC 24 | Aug 27 04:51:46 PM UTC 24 | 7032280 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.1104539456 | Aug 27 04:51:42 PM UTC 24 | Aug 27 04:51:46 PM UTC 24 | 12460676 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1046198468 | Aug 27 04:51:44 PM UTC 24 | Aug 27 04:51:47 PM UTC 24 | 11694040 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.1412543917 | Aug 27 04:51:44 PM UTC 24 | Aug 27 04:51:47 PM UTC 24 | 10719283 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.4209368858 | Aug 27 04:51:44 PM UTC 24 | Aug 27 04:51:47 PM UTC 24 | 8247721 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.2156101262 | Aug 27 04:51:46 PM UTC 24 | Aug 27 04:51:49 PM UTC 24 | 11050345 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.3123640423 | Aug 27 04:51:46 PM UTC 24 | Aug 27 04:51:50 PM UTC 24 | 8603879 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.1961707522 | Aug 27 04:51:49 PM UTC 24 | Aug 27 04:51:52 PM UTC 24 | 6772580 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.3804907134 | Aug 27 04:51:49 PM UTC 24 | Aug 27 04:51:52 PM UTC 24 | 10087328 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.4032967410 | Aug 27 04:51:49 PM UTC 24 | Aug 27 04:51:52 PM UTC 24 | 8828157 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.3609509868 | Aug 27 04:51:49 PM UTC 24 | Aug 27 04:51:53 PM UTC 24 | 12821105 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.449749746 | Aug 27 04:51:50 PM UTC 24 | Aug 27 04:51:53 PM UTC 24 | 14599195 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.2090075035 | Aug 27 04:51:50 PM UTC 24 | Aug 27 04:51:54 PM UTC 24 | 8815535 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.836192298 | Aug 27 04:45:55 PM UTC 24 | Aug 27 04:51:55 PM UTC 24 | 7617934915 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3284128731 | Aug 27 04:44:42 PM UTC 24 | Aug 27 04:51:55 PM UTC 24 | 4665639219 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.3165420842 | Aug 27 04:51:54 PM UTC 24 | Aug 27 04:51:57 PM UTC 24 | 9353994 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.3251744416 | Aug 27 04:51:54 PM UTC 24 | Aug 27 04:51:57 PM UTC 24 | 26232112 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.1149692826 | Aug 27 04:51:54 PM UTC 24 | Aug 27 04:51:57 PM UTC 24 | 6690281 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1539138196 | Aug 27 04:51:21 PM UTC 24 | Aug 27 04:51:57 PM UTC 24 | 746284175 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.3962735912 | Aug 27 04:51:54 PM UTC 24 | Aug 27 04:51:57 PM UTC 24 | 10927451 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.2472012523 | Aug 27 04:51:54 PM UTC 24 | Aug 27 04:51:57 PM UTC 24 | 8292764 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.2596884485 | Aug 27 04:51:55 PM UTC 24 | Aug 27 04:51:58 PM UTC 24 | 13774127 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3757582648 | Aug 27 04:45:28 PM UTC 24 | Aug 27 04:51:59 PM UTC 24 | 9942083838 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.3952765579 | Aug 27 04:51:57 PM UTC 24 | Aug 27 04:52:00 PM UTC 24 | 6860038 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1861955316 | Aug 27 04:48:49 PM UTC 24 | Aug 27 04:52:22 PM UTC 24 | 2050242832 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3507856214 | Aug 27 04:46:38 PM UTC 24 | Aug 27 04:52:27 PM UTC 24 | 34945631954 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3829072386 | Aug 27 04:48:22 PM UTC 24 | Aug 27 04:52:31 PM UTC 24 | 2604216812 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2250337736 | Aug 27 04:50:44 PM UTC 24 | Aug 27 04:52:46 PM UTC 24 | 15562597479 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.61918694 | Aug 27 04:49:25 PM UTC 24 | Aug 27 04:53:07 PM UTC 24 | 11027871867 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3711908810 | Aug 27 04:47:44 PM UTC 24 | Aug 27 04:54:07 PM UTC 24 | 21640311361 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.496167934 | Aug 27 04:50:37 PM UTC 24 | Aug 27 04:54:39 PM UTC 24 | 8529624295 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.497561764 | Aug 27 04:45:00 PM UTC 24 | Aug 27 04:54:46 PM UTC 24 | 6521436918 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.508125065 | Aug 27 04:51:10 PM UTC 24 | Aug 27 04:54:46 PM UTC 24 | 10171452796 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3647021060 | Aug 27 04:46:21 PM UTC 24 | Aug 27 04:55:00 PM UTC 24 | 12497830328 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.18180966 | Aug 27 04:50:17 PM UTC 24 | Aug 27 04:56:01 PM UTC 24 | 19855538626 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.639229324 | Aug 27 04:39:40 PM UTC 24 | Aug 27 04:57:58 PM UTC 24 | 50817233219 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.731018082 | Aug 27 04:48:20 PM UTC 24 | Aug 27 04:59:15 PM UTC 24 | 8054854206 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.712230201 | Aug 27 04:50:31 PM UTC 24 | Aug 27 04:59:50 PM UTC 24 | 6131880395 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1756782075 | Aug 27 04:50:16 PM UTC 24 | Aug 27 04:59:55 PM UTC 24 | 27327823113 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1192522161 | Aug 27 04:46:01 PM UTC 24 | Aug 27 04:59:57 PM UTC 24 | 4487129333 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1036570857 | Aug 27 04:51:05 PM UTC 24 | Aug 27 05:01:08 PM UTC 24 | 28552972432 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.151480638 | Aug 27 04:45:50 PM UTC 24 | Aug 27 05:03:58 PM UTC 24 | 13415601304 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3203137817 | Aug 27 04:40:36 PM UTC 24 | Aug 27 05:04:20 PM UTC 24 | 63214630191 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.708580672 | Aug 27 04:48:47 PM UTC 24 | Aug 27 05:05:46 PM UTC 24 | 13942190260 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2313105648 | Aug 27 04:49:18 PM UTC 24 | Aug 27 05:05:59 PM UTC 24 | 56625232421 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.20535078 | Aug 27 04:43:53 PM UTC 24 | Aug 27 05:06:35 PM UTC 24 | 32691539221 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2880119089 | Aug 27 04:42:59 PM UTC 24 | Aug 27 05:06:49 PM UTC 24 | 66360848653 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.662359219 | Aug 27 04:47:43 PM UTC 24 | Aug 27 05:10:43 PM UTC 24 | 108833266677 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.295353082 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1467638107 ps |
| CPU time | 9.82 seconds |
| Started | Aug 27 03:12:28 PM UTC 24 |
| Finished | Aug 27 03:12:52 PM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295353082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.295353082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.2760024222 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1329548773 ps |
| CPU time | 17.58 seconds |
| Started | Aug 27 03:12:24 PM UTC 24 |
| Finished | Aug 27 03:13:03 PM UTC 24 |
| Peak memory | 262916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760024222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2760024222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all_with_rand_reset.1467576331 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13645499478 ps |
| CPU time | 127.49 seconds |
| Started | Aug 27 03:13:01 PM UTC 24 |
| Finished | Aug 27 03:15:10 PM UTC 24 |
| Peak memory | 279804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1467576331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.al ert_handler_stress_all_with_rand_reset.1467576331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.1278543002 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1460976506 ps |
| CPU time | 24.86 seconds |
| Started | Aug 27 03:12:24 PM UTC 24 |
| Finished | Aug 27 03:13:18 PM UTC 24 |
| Peak memory | 295412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278543002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1278543002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.3119872594 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 832285887 ps |
| CPU time | 14.77 seconds |
| Started | Aug 27 03:12:27 PM UTC 24 |
| Finished | Aug 27 03:12:50 PM UTC 24 |
| Peak memory | 269080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119872594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3119872594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.4143912307 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 612108853 ps |
| CPU time | 35.66 seconds |
| Started | Aug 27 04:40:58 PM UTC 24 |
| Finished | Aug 27 04:41:35 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143912307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.4143912307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.2212677386 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 124204389885 ps |
| CPU time | 1497.99 seconds |
| Started | Aug 27 03:12:56 PM UTC 24 |
| Finished | Aug 27 03:38:11 PM UTC 24 |
| Peak memory | 288616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212677386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2212677386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.836192298 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 7617934915 ps |
| CPU time | 355.32 seconds |
| Started | Aug 27 04:45:55 PM UTC 24 |
| Finished | Aug 27 04:51:55 PM UTC 24 |
| Peak memory | 285604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836192298 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.836192298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.2322126049 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1264366778 ps |
| CPU time | 15.67 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:12:48 PM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322126049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2322126049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy.2874320516 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27567231553 ps |
| CPU time | 914.59 seconds |
| Started | Aug 27 03:13:54 PM UTC 24 |
| Finished | Aug 27 03:29:20 PM UTC 24 |
| Peak memory | 285828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874320516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2874320516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.1780700957 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 41267802564 ps |
| CPU time | 2207.39 seconds |
| Started | Aug 27 03:13:32 PM UTC 24 |
| Finished | Aug 27 03:50:43 PM UTC 24 |
| Peak memory | 300512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780700957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1780700957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all_with_rand_reset.4209583172 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4554194808 ps |
| CPU time | 334.18 seconds |
| Started | Aug 27 03:12:37 PM UTC 24 |
| Finished | Aug 27 03:18:19 PM UTC 24 |
| Peak memory | 279476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4209583172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.al ert_handler_stress_all_with_rand_reset.4209583172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.228299568 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 45054447154 ps |
| CPU time | 2188 seconds |
| Started | Aug 27 03:12:51 PM UTC 24 |
| Finished | Aug 27 03:49:41 PM UTC 24 |
| Peak memory | 300840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228299568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.228299568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2525486353 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 3466344655 ps |
| CPU time | 242.43 seconds |
| Started | Aug 27 04:42:18 PM UTC 24 |
| Finished | Aug 27 04:46:25 PM UTC 24 |
| Peak memory | 279592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525486353 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.2525486353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.1347190539 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 125248841595 ps |
| CPU time | 2553.16 seconds |
| Started | Aug 27 03:13:09 PM UTC 24 |
| Finished | Aug 27 03:56:13 PM UTC 24 |
| Peak memory | 302632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347190539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1347190539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.3969777378 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 26598546116 ps |
| CPU time | 269.53 seconds |
| Started | Aug 27 03:12:53 PM UTC 24 |
| Finished | Aug 27 03:17:27 PM UTC 24 |
| Peak memory | 269196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969777378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3969777378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.3465251804 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 18529400509 ps |
| CPU time | 1612.02 seconds |
| Started | Aug 27 03:24:05 PM UTC 24 |
| Finished | Aug 27 03:51:15 PM UTC 24 |
| Peak memory | 318592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465251804 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.3465251804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.1000581182 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2075780830 ps |
| CPU time | 45.47 seconds |
| Started | Aug 27 03:13:24 PM UTC 24 |
| Finished | Aug 27 03:14:11 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000581182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1000581182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.2862251709 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 123597529 ps |
| CPU time | 10.17 seconds |
| Started | Aug 27 04:38:21 PM UTC 24 |
| Finished | Aug 27 04:38:32 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862251709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2862251709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3256892018 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 4391049663 ps |
| CPU time | 771.37 seconds |
| Started | Aug 27 04:37:17 PM UTC 24 |
| Finished | Aug 27 04:50:18 PM UTC 24 |
| Peak memory | 279592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256892018 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shado w_reg_errors_with_csr_rw.3256892018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all_with_rand_reset.1344757351 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 7849062210 ps |
| CPU time | 110.23 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:14:44 PM UTC 24 |
| Peak memory | 279812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1344757351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.al ert_handler_stress_all_with_rand_reset.1344757351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3203137817 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 63214630191 ps |
| CPU time | 1406.3 seconds |
| Started | Aug 27 04:40:36 PM UTC 24 |
| Finished | Aug 27 05:04:20 PM UTC 24 |
| Peak memory | 279460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203137817 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shado w_reg_errors_with_csr_rw.3203137817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.2073792974 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 15235480 ps |
| CPU time | 1.95 seconds |
| Started | Aug 27 04:41:04 PM UTC 24 |
| Finished | Aug 27 04:41:07 PM UTC 24 |
| Peak memory | 248780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073792974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2073792974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3711908810 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 21640311361 ps |
| CPU time | 377.87 seconds |
| Started | Aug 27 04:47:44 PM UTC 24 |
| Finished | Aug 27 04:54:07 PM UTC 24 |
| Peak memory | 279528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711908810 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.3711908810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.3286274207 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 262016119335 ps |
| CPU time | 985.14 seconds |
| Started | Aug 27 03:13:09 PM UTC 24 |
| Finished | Aug 27 03:29:46 PM UTC 24 |
| Peak memory | 269508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286274207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3286274207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.3445581071 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1858408265 ps |
| CPU time | 19.98 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:13:05 PM UTC 24 |
| Peak memory | 269124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445581071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3445581071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1571874642 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 39485502149 ps |
| CPU time | 519.51 seconds |
| Started | Aug 27 04:39:44 PM UTC 24 |
| Finished | Aug 27 04:48:30 PM UTC 24 |
| Peak memory | 279452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571874642 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.1571874642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.4091058400 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 75358393575 ps |
| CPU time | 2539.34 seconds |
| Started | Aug 27 03:28:30 PM UTC 24 |
| Finished | Aug 27 04:11:17 PM UTC 24 |
| Peak memory | 304680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091058400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.4091058400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.2823218488 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 8138529565 ps |
| CPU time | 443.75 seconds |
| Started | Aug 27 03:28:29 PM UTC 24 |
| Finished | Aug 27 03:35:59 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823218488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2823218488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.1901147622 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 734922278 ps |
| CPU time | 48.89 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:13:42 PM UTC 24 |
| Peak memory | 262936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901147622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1901147622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.945365134 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 107156547699 ps |
| CPU time | 1337.09 seconds |
| Started | Aug 27 03:16:50 PM UTC 24 |
| Finished | Aug 27 03:39:21 PM UTC 24 |
| Peak memory | 285492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945365134 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.945365134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.20535078 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 32691539221 ps |
| CPU time | 1344.5 seconds |
| Started | Aug 27 04:43:53 PM UTC 24 |
| Finished | Aug 27 05:06:35 PM UTC 24 |
| Peak memory | 279596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20535078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_ reg_errors_with_csr_rw.20535078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.4198312803 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 39290911376 ps |
| CPU time | 2246.28 seconds |
| Started | Aug 27 03:15:11 PM UTC 24 |
| Finished | Aug 27 03:53:01 PM UTC 24 |
| Peak memory | 299832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198312803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.4198312803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.1261934018 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 50029415 ps |
| CPU time | 8.5 seconds |
| Started | Aug 27 04:42:45 PM UTC 24 |
| Finished | Aug 27 04:42:54 PM UTC 24 |
| Peak memory | 250328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261934018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1261934018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.3401114492 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 152936287739 ps |
| CPU time | 651.3 seconds |
| Started | Aug 27 03:23:38 PM UTC 24 |
| Finished | Aug 27 03:34:36 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401114492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3401114492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.1667797126 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1731684059 ps |
| CPU time | 49.5 seconds |
| Started | Aug 27 03:12:27 PM UTC 24 |
| Finished | Aug 27 03:13:25 PM UTC 24 |
| Peak memory | 269316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667797126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1667797126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.708580672 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 13942190260 ps |
| CPU time | 1006.35 seconds |
| Started | Aug 27 04:48:47 PM UTC 24 |
| Finished | Aug 27 05:05:46 PM UTC 24 |
| Peak memory | 279452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708580672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shado w_reg_errors_with_csr_rw.708580672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.841074759 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 191915281927 ps |
| CPU time | 2630.39 seconds |
| Started | Aug 27 04:11:07 PM UTC 24 |
| Finished | Aug 27 04:55:26 PM UTC 24 |
| Peak memory | 304596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841074759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.841074759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/34.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.2551974948 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 23272430016 ps |
| CPU time | 172.06 seconds |
| Started | Aug 27 03:18:05 PM UTC 24 |
| Finished | Aug 27 03:21:00 PM UTC 24 |
| Peak memory | 269376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551974948 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.2551974948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.1372713683 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 7325431 ps |
| CPU time | 2.07 seconds |
| Started | Aug 27 04:48:36 PM UTC 24 |
| Finished | Aug 27 04:48:39 PM UTC 24 |
| Peak memory | 248288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372713683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1372713683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.1974289896 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 9974732699 ps |
| CPU time | 246.8 seconds |
| Started | Aug 27 03:50:32 PM UTC 24 |
| Finished | Aug 27 03:54:42 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974289896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1974289896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.3807151967 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 10759568866 ps |
| CPU time | 405.38 seconds |
| Started | Aug 27 03:31:14 PM UTC 24 |
| Finished | Aug 27 03:38:04 PM UTC 24 |
| Peak memory | 263368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807151967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3807151967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all_with_rand_reset.133326639 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 34217418798 ps |
| CPU time | 652 seconds |
| Started | Aug 27 04:05:52 PM UTC 24 |
| Finished | Aug 27 04:16:52 PM UTC 24 |
| Peak memory | 285696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=133326639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.al ert_handler_stress_all_with_rand_reset.133326639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.1121367635 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 557501423037 ps |
| CPU time | 2063.91 seconds |
| Started | Aug 27 03:14:06 PM UTC 24 |
| Finished | Aug 27 03:48:52 PM UTC 24 |
| Peak memory | 302552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121367635 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.1121367635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.1221837271 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2060048090 ps |
| CPU time | 44.74 seconds |
| Started | Aug 27 03:42:02 PM UTC 24 |
| Finished | Aug 27 03:42:48 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221837271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1221837271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.731018082 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 8054854206 ps |
| CPU time | 645.55 seconds |
| Started | Aug 27 04:48:20 PM UTC 24 |
| Finished | Aug 27 04:59:15 PM UTC 24 |
| Peak memory | 283548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731018082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shado w_reg_errors_with_csr_rw.731018082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.1641889842 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 41579740757 ps |
| CPU time | 1522.87 seconds |
| Started | Aug 27 03:23:44 PM UTC 24 |
| Finished | Aug 27 03:49:24 PM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641889842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1641889842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.3907499434 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1789773066 ps |
| CPU time | 22.89 seconds |
| Started | Aug 27 03:12:27 PM UTC 24 |
| Finished | Aug 27 03:12:58 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907499434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3907499434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.2451181955 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 337237978164 ps |
| CPU time | 1470.44 seconds |
| Started | Aug 27 03:21:32 PM UTC 24 |
| Finished | Aug 27 03:46:20 PM UTC 24 |
| Peak memory | 285568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451181955 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.2451181955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all_with_rand_reset.3688219014 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 21874723830 ps |
| CPU time | 436.22 seconds |
| Started | Aug 27 04:11:17 PM UTC 24 |
| Finished | Aug 27 04:18:40 PM UTC 24 |
| Peak memory | 281732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3688219014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.a lert_handler_stress_all_with_rand_reset.3688219014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.2087407983 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 20687289508 ps |
| CPU time | 687.69 seconds |
| Started | Aug 27 04:24:52 PM UTC 24 |
| Finished | Aug 27 04:36:27 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087407983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2087407983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/43.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.1331176965 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 9784980665 ps |
| CPU time | 394.4 seconds |
| Started | Aug 27 03:13:55 PM UTC 24 |
| Finished | Aug 27 03:20:35 PM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331176965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1331176965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.3796113882 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 130358918780 ps |
| CPU time | 1027.9 seconds |
| Started | Aug 27 03:29:22 PM UTC 24 |
| Finished | Aug 27 03:46:42 PM UTC 24 |
| Peak memory | 295808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796113882 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.3796113882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.496167934 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 8529624295 ps |
| CPU time | 237.95 seconds |
| Started | Aug 27 04:50:37 PM UTC 24 |
| Finished | Aug 27 04:54:39 PM UTC 24 |
| Peak memory | 279532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496167934 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.496167934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.2134905872 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 46091244810 ps |
| CPU time | 1240.44 seconds |
| Started | Aug 27 03:40:19 PM UTC 24 |
| Finished | Aug 27 04:01:14 PM UTC 24 |
| Peak memory | 301880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134905872 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.2134905872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.1414010223 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 19575872513 ps |
| CPU time | 1156.07 seconds |
| Started | Aug 27 04:03:05 PM UTC 24 |
| Finished | Aug 27 04:22:34 PM UTC 24 |
| Peak memory | 285700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414010223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1414010223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/30.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.3718828839 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 46367220189 ps |
| CPU time | 2186.67 seconds |
| Started | Aug 27 03:13:57 PM UTC 24 |
| Finished | Aug 27 03:50:47 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718828839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3718828839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.911346978 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 36083406457 ps |
| CPU time | 184.96 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:15:56 PM UTC 24 |
| Peak memory | 269092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911346978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.911346978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1234201723 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 90375906 ps |
| CPU time | 8.83 seconds |
| Started | Aug 27 04:42:34 PM UTC 24 |
| Finished | Aug 27 04:42:44 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234201723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1234201723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3507856214 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 34945631954 ps |
| CPU time | 344.4 seconds |
| Started | Aug 27 04:46:38 PM UTC 24 |
| Finished | Aug 27 04:52:27 PM UTC 24 |
| Peak memory | 279452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507856214 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shad ow_reg_errors_with_csr_rw.3507856214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.1107438261 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1257445759 ps |
| CPU time | 58.25 seconds |
| Started | Aug 27 03:12:24 PM UTC 24 |
| Finished | Aug 27 03:13:44 PM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107438261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1107438261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.661318596 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 46737688 ps |
| CPU time | 5.66 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:12:58 PM UTC 24 |
| Peak memory | 263176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661318596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.661318596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.4158587043 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 42372256 ps |
| CPU time | 4.71 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:12:57 PM UTC 24 |
| Peak memory | 263112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158587043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.4158587043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.651342221 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 29468380 ps |
| CPU time | 4.72 seconds |
| Started | Aug 27 03:16:50 PM UTC 24 |
| Finished | Aug 27 03:16:56 PM UTC 24 |
| Peak memory | 263244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651342221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.651342221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.2269794499 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 17728994 ps |
| CPU time | 3.9 seconds |
| Started | Aug 27 03:24:23 PM UTC 24 |
| Finished | Aug 27 03:24:28 PM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269794499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2269794499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2225929957 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 453969368 ps |
| CPU time | 12.83 seconds |
| Started | Aug 27 04:47:29 PM UTC 24 |
| Finished | Aug 27 04:47:43 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225929957 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem _rw_with_rand_reset.2225929957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.2813524679 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 1344054372 ps |
| CPU time | 54.89 seconds |
| Started | Aug 27 03:16:17 PM UTC 24 |
| Finished | Aug 27 03:17:13 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813524679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2813524679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.3422395554 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 37970862985 ps |
| CPU time | 781.72 seconds |
| Started | Aug 27 04:12:14 PM UTC 24 |
| Finished | Aug 27 04:25:25 PM UTC 24 |
| Peak memory | 285828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422395554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3422395554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/35.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.88567784 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1917669952 ps |
| CPU time | 47.23 seconds |
| Started | Aug 27 04:31:28 PM UTC 24 |
| Finished | Aug 27 04:32:16 PM UTC 24 |
| Peak memory | 269124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88567784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig _int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.88567784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.1130014030 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 825434606 ps |
| CPU time | 49.79 seconds |
| Started | Aug 27 04:36:10 PM UTC 24 |
| Finished | Aug 27 04:37:02 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130014030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1130014030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all_with_rand_reset.1545404885 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 6788553793 ps |
| CPU time | 278.12 seconds |
| Started | Aug 27 03:13:42 PM UTC 24 |
| Finished | Aug 27 03:18:25 PM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1545404885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.al ert_handler_stress_all_with_rand_reset.1545404885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all_with_rand_reset.962696887 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2916479074 ps |
| CPU time | 394.28 seconds |
| Started | Aug 27 03:14:51 PM UTC 24 |
| Finished | Aug 27 03:21:30 PM UTC 24 |
| Peak memory | 279552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=962696887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.ale rt_handler_stress_all_with_rand_reset.962696887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3647021060 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 12497830328 ps |
| CPU time | 512.7 seconds |
| Started | Aug 27 04:46:21 PM UTC 24 |
| Finished | Aug 27 04:55:00 PM UTC 24 |
| Peak memory | 279592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647021060 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shad ow_reg_errors_with_csr_rw.3647021060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1829596711 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 2004948355 ps |
| CPU time | 165.64 seconds |
| Started | Aug 27 04:40:36 PM UTC 24 |
| Finished | Aug 27 04:43:24 PM UTC 24 |
| Peak memory | 281376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829596711 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.1829596711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.2506223281 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 7936392 ps |
| CPU time | 2.18 seconds |
| Started | Aug 27 04:40:17 PM UTC 24 |
| Finished | Aug 27 04:40:20 PM UTC 24 |
| Peak memory | 248360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506223281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2506223281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.620665114 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 140466571455 ps |
| CPU time | 712.63 seconds |
| Started | Aug 27 03:17:49 PM UTC 24 |
| Finished | Aug 27 03:29:50 PM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620665114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.620665114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.3861543909 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 4870659573 ps |
| CPU time | 192.58 seconds |
| Started | Aug 27 03:38:05 PM UTC 24 |
| Finished | Aug 27 03:41:20 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861543909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3861543909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.880325508 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 258550241 ps |
| CPU time | 41.52 seconds |
| Started | Aug 27 03:39:35 PM UTC 24 |
| Finished | Aug 27 03:40:18 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880325508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.880325508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all_with_rand_reset.3544878465 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2534909536 ps |
| CPU time | 386.88 seconds |
| Started | Aug 27 03:40:29 PM UTC 24 |
| Finished | Aug 27 03:47:02 PM UTC 24 |
| Peak memory | 281604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3544878465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.a lert_handler_stress_all_with_rand_reset.3544878465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all.858356109 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 18123175348 ps |
| CPU time | 1181.45 seconds |
| Started | Aug 27 03:43:05 PM UTC 24 |
| Finished | Aug 27 04:03:01 PM UTC 24 |
| Peak memory | 279348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858356109 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all.858356109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/20.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.1823821874 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 154901722821 ps |
| CPU time | 1642.31 seconds |
| Started | Aug 27 03:44:41 PM UTC 24 |
| Finished | Aug 27 04:12:22 PM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823821874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1823821874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/21.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.1718260227 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 101528248191 ps |
| CPU time | 3461.4 seconds |
| Started | Aug 27 03:51:51 PM UTC 24 |
| Finished | Aug 27 04:50:13 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718260227 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.1718260227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/24.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all_with_rand_reset.3715672419 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 11906770526 ps |
| CPU time | 355.96 seconds |
| Started | Aug 27 03:58:04 PM UTC 24 |
| Finished | Aug 27 04:04:05 PM UTC 24 |
| Peak memory | 283652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3715672419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.a lert_handler_stress_all_with_rand_reset.3715672419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.1104134569 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 53939955128 ps |
| CPU time | 1083.4 seconds |
| Started | Aug 27 04:03:23 PM UTC 24 |
| Finished | Aug 27 04:21:39 PM UTC 24 |
| Peak memory | 302208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104134569 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.1104134569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/30.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.3517062036 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1190649097 ps |
| CPU time | 30.07 seconds |
| Started | Aug 27 04:04:43 PM UTC 24 |
| Finished | Aug 27 04:05:14 PM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517062036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3517062036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.3621685378 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 113507610365 ps |
| CPU time | 3095.19 seconds |
| Started | Aug 27 04:12:21 PM UTC 24 |
| Finished | Aug 27 05:04:30 PM UTC 24 |
| Peak memory | 304676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621685378 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.3621685378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/35.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.824487838 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 179306952 ps |
| CPU time | 14.26 seconds |
| Started | Aug 27 04:24:35 PM UTC 24 |
| Finished | Aug 27 04:24:51 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824487838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.824487838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.1966420478 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 174775013446 ps |
| CPU time | 2193.71 seconds |
| Started | Aug 27 04:28:25 PM UTC 24 |
| Finished | Aug 27 05:05:25 PM UTC 24 |
| Peak memory | 288292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966420478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1966420478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/46.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all_with_rand_reset.689166995 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 14305995362 ps |
| CPU time | 226.32 seconds |
| Started | Aug 27 04:37:07 PM UTC 24 |
| Finished | Aug 27 04:40:57 PM UTC 24 |
| Peak memory | 279480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=689166995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.al ert_handler_stress_all_with_rand_reset.689166995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.3621727581 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 33281547 ps |
| CPU time | 7.59 seconds |
| Started | Aug 27 03:13:04 PM UTC 24 |
| Finished | Aug 27 03:13:12 PM UTC 24 |
| Peak memory | 265308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621727581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3621727581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.18180966 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 19855538626 ps |
| CPU time | 339.27 seconds |
| Started | Aug 27 04:50:17 PM UTC 24 |
| Finished | Aug 27 04:56:01 PM UTC 24 |
| Peak memory | 285600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18180966 -assert nopostproc +UVM_TESTNAME=alert_handler_ba se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.18180966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2250337736 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 15562597479 ps |
| CPU time | 119.51 seconds |
| Started | Aug 27 04:50:44 PM UTC 24 |
| Finished | Aug 27 04:52:46 PM UTC 24 |
| Peak memory | 252568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250337736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2250337736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.549867325 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 3997829895 ps |
| CPU time | 393.81 seconds |
| Started | Aug 27 04:44:42 PM UTC 24 |
| Finished | Aug 27 04:51:21 PM UTC 24 |
| Peak memory | 279596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549867325 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.549867325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1961287438 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 446759879 ps |
| CPU time | 36.87 seconds |
| Started | Aug 27 04:47:50 PM UTC 24 |
| Finished | Aug 27 04:48:28 PM UTC 24 |
| Peak memory | 250528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961287438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1961287438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2935118597 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1787110356 ps |
| CPU time | 51.55 seconds |
| Started | Aug 27 04:44:11 PM UTC 24 |
| Finished | Aug 27 04:45:04 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935118597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2935118597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3176607422 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 33199354 ps |
| CPU time | 2.63 seconds |
| Started | Aug 27 04:45:56 PM UTC 24 |
| Finished | Aug 27 04:45:59 PM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176607422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3176607422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1301693509 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 87980361 ps |
| CPU time | 5.63 seconds |
| Started | Aug 27 04:46:13 PM UTC 24 |
| Finished | Aug 27 04:46:19 PM UTC 24 |
| Peak memory | 250388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301693509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1301693509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.88418336 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 159748562 ps |
| CPU time | 3.32 seconds |
| Started | Aug 27 04:48:31 PM UTC 24 |
| Finished | Aug 27 04:48:35 PM UTC 24 |
| Peak memory | 250392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88418336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.88418336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1861955316 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2050242832 ps |
| CPU time | 210.57 seconds |
| Started | Aug 27 04:48:49 PM UTC 24 |
| Finished | Aug 27 04:52:22 PM UTC 24 |
| Peak memory | 279464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861955316 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.1861955316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.338248998 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 37205836 ps |
| CPU time | 5.23 seconds |
| Started | Aug 27 04:49:50 PM UTC 24 |
| Finished | Aug 27 04:49:57 PM UTC 24 |
| Peak memory | 249852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338248998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.338248998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3680487944 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 590782077 ps |
| CPU time | 37.19 seconds |
| Started | Aug 27 04:43:17 PM UTC 24 |
| Finished | Aug 27 04:43:55 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680487944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3680487944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3051397488 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 37355684 ps |
| CPU time | 5.02 seconds |
| Started | Aug 27 04:44:49 PM UTC 24 |
| Finished | Aug 27 04:44:55 PM UTC 24 |
| Peak memory | 250396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051397488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3051397488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3865232092 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 79109714 ps |
| CPU time | 3.62 seconds |
| Started | Aug 27 04:45:09 PM UTC 24 |
| Finished | Aug 27 04:45:14 PM UTC 24 |
| Peak memory | 250524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865232092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3865232092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2698094733 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 23143195 ps |
| CPU time | 4.2 seconds |
| Started | Aug 27 04:38:00 PM UTC 24 |
| Finished | Aug 27 04:38:05 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698094733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2698094733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.11642687 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 37729497 ps |
| CPU time | 5.7 seconds |
| Started | Aug 27 04:40:13 PM UTC 24 |
| Finished | Aug 27 04:40:20 PM UTC 24 |
| Peak memory | 250392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11642687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.11642687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.802754694 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 149895146 ps |
| CPU time | 6.19 seconds |
| Started | Aug 27 04:46:27 PM UTC 24 |
| Finished | Aug 27 04:46:35 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802754694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.802754694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1240026051 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 54997027 ps |
| CPU time | 3.33 seconds |
| Started | Aug 27 04:49:00 PM UTC 24 |
| Finished | Aug 27 04:49:04 PM UTC 24 |
| Peak memory | 250528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240026051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1240026051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3125725882 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 195392490 ps |
| CPU time | 13.24 seconds |
| Started | Aug 27 04:51:17 PM UTC 24 |
| Finished | Aug 27 04:51:32 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125725882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3125725882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1532816195 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 53259822 ps |
| CPU time | 5.47 seconds |
| Started | Aug 27 04:45:37 PM UTC 24 |
| Finished | Aug 27 04:45:44 PM UTC 24 |
| Peak memory | 250396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532816195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1532816195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.3161641236 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1567633200 ps |
| CPU time | 47.51 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:13:23 PM UTC 24 |
| Peak memory | 269004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161641236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3161641236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all_with_rand_reset.3244377926 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 14543995125 ps |
| CPU time | 209.3 seconds |
| Started | Aug 27 04:23:45 PM UTC 24 |
| Finished | Aug 27 04:27:18 PM UTC 24 |
| Peak memory | 279812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3244377926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.a lert_handler_stress_all_with_rand_reset.3244377926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2332819206 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3339510993 ps |
| CPU time | 247.9 seconds |
| Started | Aug 27 04:39:11 PM UTC 24 |
| Finished | Aug 27 04:43:23 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332819206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2332819206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1576357458 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 838181667 ps |
| CPU time | 208.5 seconds |
| Started | Aug 27 04:38:33 PM UTC 24 |
| Finished | Aug 27 04:42:05 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576357458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1576357458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1257232937 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 201363100 ps |
| CPU time | 9 seconds |
| Started | Aug 27 04:38:10 PM UTC 24 |
| Finished | Aug 27 04:38:20 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257232937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1257232937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3312309856 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 56590705 ps |
| CPU time | 12.82 seconds |
| Started | Aug 27 04:39:25 PM UTC 24 |
| Finished | Aug 27 04:39:39 PM UTC 24 |
| Peak memory | 254552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312309856 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_ rw_with_rand_reset.3312309856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.2831485762 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 12588748 ps |
| CPU time | 2.1 seconds |
| Started | Aug 27 04:38:06 PM UTC 24 |
| Finished | Aug 27 04:38:09 PM UTC 24 |
| Peak memory | 250408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831485762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2831485762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3731062968 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 181993254 ps |
| CPU time | 47.15 seconds |
| Started | Aug 27 04:39:16 PM UTC 24 |
| Finished | Aug 27 04:40:05 PM UTC 24 |
| Peak memory | 260632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731062968 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.3731062968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2002828078 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 10984770594 ps |
| CPU time | 177.7 seconds |
| Started | Aug 27 04:37:32 PM UTC 24 |
| Finished | Aug 27 04:40:33 PM UTC 24 |
| Peak memory | 281504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002828078 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.2002828078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.2989841709 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 195689671 ps |
| CPU time | 21.25 seconds |
| Started | Aug 27 04:37:37 PM UTC 24 |
| Finished | Aug 27 04:37:59 PM UTC 24 |
| Peak memory | 262812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989841709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2989841709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.386845855 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 18427500316 ps |
| CPU time | 328.23 seconds |
| Started | Aug 27 04:40:25 PM UTC 24 |
| Finished | Aug 27 04:45:59 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386845855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.386845855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1352462641 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 3722723091 ps |
| CPU time | 238.88 seconds |
| Started | Aug 27 04:40:22 PM UTC 24 |
| Finished | Aug 27 04:44:24 PM UTC 24 |
| Peak memory | 250460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352462641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1352462641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.617298508 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 130080554 ps |
| CPU time | 8.99 seconds |
| Started | Aug 27 04:40:17 PM UTC 24 |
| Finished | Aug 27 04:40:27 PM UTC 24 |
| Peak memory | 262616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617298508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.617298508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4095585117 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 56495323 ps |
| CPU time | 8.17 seconds |
| Started | Aug 27 04:40:34 PM UTC 24 |
| Finished | Aug 27 04:40:44 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095585117 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_ rw_with_rand_reset.4095585117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.1115689181 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 96431367 ps |
| CPU time | 11.47 seconds |
| Started | Aug 27 04:40:20 PM UTC 24 |
| Finished | Aug 27 04:40:33 PM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115689181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1115689181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3549859827 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 673622712 ps |
| CPU time | 38.68 seconds |
| Started | Aug 27 04:40:28 PM UTC 24 |
| Finished | Aug 27 04:41:09 PM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549859827 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.3549859827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.639229324 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 50817233219 ps |
| CPU time | 1083.78 seconds |
| Started | Aug 27 04:39:40 PM UTC 24 |
| Finished | Aug 27 04:57:58 PM UTC 24 |
| Peak memory | 279468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639229324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow _reg_errors_with_csr_rw.639229324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.3189006863 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 47107029 ps |
| CPU time | 8.73 seconds |
| Started | Aug 27 04:40:06 PM UTC 24 |
| Finished | Aug 27 04:40:16 PM UTC 24 |
| Peak memory | 262888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189006863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3189006863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.438187255 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 140454899 ps |
| CPU time | 16.08 seconds |
| Started | Aug 27 04:46:20 PM UTC 24 |
| Finished | Aug 27 04:46:37 PM UTC 24 |
| Peak memory | 264792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438187255 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem_ rw_with_rand_reset.438187255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.1884117680 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 370258317 ps |
| CPU time | 11.87 seconds |
| Started | Aug 27 04:46:17 PM UTC 24 |
| Finished | Aug 27 04:46:30 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884117680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1884117680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.2105636606 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 14276395 ps |
| CPU time | 2.85 seconds |
| Started | Aug 27 04:46:16 PM UTC 24 |
| Finished | Aug 27 04:46:20 PM UTC 24 |
| Peak memory | 250540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105636606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2105636606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.579209526 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 335558869 ps |
| CPU time | 14.43 seconds |
| Started | Aug 27 04:46:19 PM UTC 24 |
| Finished | Aug 27 04:46:34 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579209526 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.579209526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.914704952 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1456059713 ps |
| CPU time | 222.48 seconds |
| Started | Aug 27 04:46:03 PM UTC 24 |
| Finished | Aug 27 04:49:49 PM UTC 24 |
| Peak memory | 279332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914704952 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.914704952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1192522161 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4487129333 ps |
| CPU time | 825.07 seconds |
| Started | Aug 27 04:46:01 PM UTC 24 |
| Finished | Aug 27 04:59:57 PM UTC 24 |
| Peak memory | 279656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192522161 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shad ow_reg_errors_with_csr_rw.1192522161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.503199489 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 467701792 ps |
| CPU time | 18.85 seconds |
| Started | Aug 27 04:46:07 PM UTC 24 |
| Finished | Aug 27 04:46:27 PM UTC 24 |
| Peak memory | 262752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503199489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.503199489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1206727277 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 313319948 ps |
| CPU time | 10.19 seconds |
| Started | Aug 27 04:46:36 PM UTC 24 |
| Finished | Aug 27 04:46:47 PM UTC 24 |
| Peak memory | 268884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206727277 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem _rw_with_rand_reset.1206727277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.2183288475 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 226235615 ps |
| CPU time | 7.11 seconds |
| Started | Aug 27 04:46:35 PM UTC 24 |
| Finished | Aug 27 04:46:43 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183288475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2183288475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.1166317956 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 37152179 ps |
| CPU time | 2.06 seconds |
| Started | Aug 27 04:46:31 PM UTC 24 |
| Finished | Aug 27 04:46:34 PM UTC 24 |
| Peak memory | 248552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166317956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1166317956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.622383828 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 984668217 ps |
| CPU time | 50.81 seconds |
| Started | Aug 27 04:46:36 PM UTC 24 |
| Finished | Aug 27 04:47:28 PM UTC 24 |
| Peak memory | 260768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622383828 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.622383828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1093266889 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 4849841276 ps |
| CPU time | 243.26 seconds |
| Started | Aug 27 04:46:24 PM UTC 24 |
| Finished | Aug 27 04:50:31 PM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093266889 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.1093266889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.2896828496 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 614346450 ps |
| CPU time | 10.54 seconds |
| Started | Aug 27 04:46:25 PM UTC 24 |
| Finished | Aug 27 04:46:37 PM UTC 24 |
| Peak memory | 266848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896828496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2896828496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.1853797149 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 134011963 ps |
| CPU time | 8.24 seconds |
| Started | Aug 27 04:46:55 PM UTC 24 |
| Finished | Aug 27 04:47:05 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853797149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1853797149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.1500244002 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 8839658 ps |
| CPU time | 2.06 seconds |
| Started | Aug 27 04:46:51 PM UTC 24 |
| Finished | Aug 27 04:46:54 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500244002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1500244002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.520248947 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1944150637 ps |
| CPU time | 41.94 seconds |
| Started | Aug 27 04:47:06 PM UTC 24 |
| Finished | Aug 27 04:47:49 PM UTC 24 |
| Peak memory | 260628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520248947 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.520248947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.859182834 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 5028784134 ps |
| CPU time | 219.25 seconds |
| Started | Aug 27 04:46:38 PM UTC 24 |
| Finished | Aug 27 04:50:21 PM UTC 24 |
| Peak memory | 279464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859182834 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.859182834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.3234934223 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 72388761 ps |
| CPU time | 5.47 seconds |
| Started | Aug 27 04:46:44 PM UTC 24 |
| Finished | Aug 27 04:46:51 PM UTC 24 |
| Peak memory | 262752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234934223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3234934223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1620435803 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 1780077267 ps |
| CPU time | 52.88 seconds |
| Started | Aug 27 04:46:48 PM UTC 24 |
| Finished | Aug 27 04:47:43 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620435803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1620435803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1083101958 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 123835168 ps |
| CPU time | 16.1 seconds |
| Started | Aug 27 04:48:20 PM UTC 24 |
| Finished | Aug 27 04:48:38 PM UTC 24 |
| Peak memory | 264864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083101958 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem _rw_with_rand_reset.1083101958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.2574748276 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 104361928 ps |
| CPU time | 12.27 seconds |
| Started | Aug 27 04:48:05 PM UTC 24 |
| Finished | Aug 27 04:48:19 PM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574748276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2574748276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.1382811023 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 19009419 ps |
| CPU time | 2.15 seconds |
| Started | Aug 27 04:48:04 PM UTC 24 |
| Finished | Aug 27 04:48:07 PM UTC 24 |
| Peak memory | 250336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382811023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1382811023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2279332576 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 3322722445 ps |
| CPU time | 36.43 seconds |
| Started | Aug 27 04:48:08 PM UTC 24 |
| Finished | Aug 27 04:48:46 PM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279332576 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.2279332576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.662359219 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 108833266677 ps |
| CPU time | 1363.62 seconds |
| Started | Aug 27 04:47:43 PM UTC 24 |
| Finished | Aug 27 05:10:43 PM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662359219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shado w_reg_errors_with_csr_rw.662359219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.1476964773 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 371478228 ps |
| CPU time | 18.87 seconds |
| Started | Aug 27 04:47:44 PM UTC 24 |
| Finished | Aug 27 04:48:04 PM UTC 24 |
| Peak memory | 262888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476964773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1476964773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.824950702 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 97699284 ps |
| CPU time | 13.98 seconds |
| Started | Aug 27 04:48:40 PM UTC 24 |
| Finished | Aug 27 04:48:55 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824950702 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem_ rw_with_rand_reset.824950702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.4287040346 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 35292800 ps |
| CPU time | 8.19 seconds |
| Started | Aug 27 04:48:38 PM UTC 24 |
| Finished | Aug 27 04:48:47 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287040346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.4287040346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1977421639 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 96964313 ps |
| CPU time | 19.82 seconds |
| Started | Aug 27 04:48:38 PM UTC 24 |
| Finished | Aug 27 04:48:59 PM UTC 24 |
| Peak memory | 260808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977421639 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.1977421639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3829072386 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2604216812 ps |
| CPU time | 245.26 seconds |
| Started | Aug 27 04:48:22 PM UTC 24 |
| Finished | Aug 27 04:52:31 PM UTC 24 |
| Peak memory | 285672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829072386 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.3829072386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.326381876 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 1510799869 ps |
| CPU time | 36.93 seconds |
| Started | Aug 27 04:48:29 PM UTC 24 |
| Finished | Aug 27 04:49:07 PM UTC 24 |
| Peak memory | 262760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326381876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.326381876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4029275145 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 378365040 ps |
| CPU time | 7.97 seconds |
| Started | Aug 27 04:49:14 PM UTC 24 |
| Finished | Aug 27 04:49:23 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029275145 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem _rw_with_rand_reset.4029275145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.2131933439 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 67304395 ps |
| CPU time | 8.22 seconds |
| Started | Aug 27 04:49:08 PM UTC 24 |
| Finished | Aug 27 04:49:17 PM UTC 24 |
| Peak memory | 250528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131933439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2131933439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.923926958 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 11362588 ps |
| CPU time | 2.1 seconds |
| Started | Aug 27 04:49:05 PM UTC 24 |
| Finished | Aug 27 04:49:08 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923926958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.923926958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.4162328596 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 2729791496 ps |
| CPU time | 72.44 seconds |
| Started | Aug 27 04:49:09 PM UTC 24 |
| Finished | Aug 27 04:50:24 PM UTC 24 |
| Peak memory | 262816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162328596 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.4162328596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.3755698205 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 168861928 ps |
| CPU time | 15.64 seconds |
| Started | Aug 27 04:48:57 PM UTC 24 |
| Finished | Aug 27 04:49:13 PM UTC 24 |
| Peak memory | 262756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755698205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3755698205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2833681966 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 803656722 ps |
| CPU time | 22.31 seconds |
| Started | Aug 27 04:50:02 PM UTC 24 |
| Finished | Aug 27 04:50:25 PM UTC 24 |
| Peak memory | 264852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833681966 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem _rw_with_rand_reset.2833681966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.1332787627 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 36733118 ps |
| CPU time | 4.88 seconds |
| Started | Aug 27 04:49:56 PM UTC 24 |
| Finished | Aug 27 04:50:01 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332787627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1332787627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.2682487882 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 13284396 ps |
| CPU time | 2.62 seconds |
| Started | Aug 27 04:49:50 PM UTC 24 |
| Finished | Aug 27 04:49:54 PM UTC 24 |
| Peak memory | 247840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682487882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2682487882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2847639918 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 1335915246 ps |
| CPU time | 74.84 seconds |
| Started | Aug 27 04:49:58 PM UTC 24 |
| Finished | Aug 27 04:51:14 PM UTC 24 |
| Peak memory | 260768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847639918 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.2847639918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.61918694 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 11027871867 ps |
| CPU time | 218.51 seconds |
| Started | Aug 27 04:49:25 PM UTC 24 |
| Finished | Aug 27 04:53:07 PM UTC 24 |
| Peak memory | 279528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61918694 -assert nopostproc +UVM_TESTNAME=alert_handler_ba se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.61918694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2313105648 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 56625232421 ps |
| CPU time | 988.23 seconds |
| Started | Aug 27 04:49:18 PM UTC 24 |
| Finished | Aug 27 05:05:59 PM UTC 24 |
| Peak memory | 279528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313105648 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shad ow_reg_errors_with_csr_rw.2313105648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.270962166 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 410002007 ps |
| CPU time | 12.44 seconds |
| Started | Aug 27 04:49:35 PM UTC 24 |
| Finished | Aug 27 04:49:49 PM UTC 24 |
| Peak memory | 262816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270962166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.270962166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1162327741 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 63658966 ps |
| CPU time | 13.86 seconds |
| Started | Aug 27 04:50:28 PM UTC 24 |
| Finished | Aug 27 04:50:43 PM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162327741 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem _rw_with_rand_reset.1162327741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.3453706219 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 32770254 ps |
| CPU time | 7.75 seconds |
| Started | Aug 27 04:50:27 PM UTC 24 |
| Finished | Aug 27 04:50:35 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453706219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3453706219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.2036295145 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 15078687 ps |
| CPU time | 2.23 seconds |
| Started | Aug 27 04:50:24 PM UTC 24 |
| Finished | Aug 27 04:50:28 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036295145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2036295145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1032689108 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 368067354 ps |
| CPU time | 17.06 seconds |
| Started | Aug 27 04:50:28 PM UTC 24 |
| Finished | Aug 27 04:50:47 PM UTC 24 |
| Peak memory | 260656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032689108 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.1032689108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1756782075 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 27327823113 ps |
| CPU time | 571.17 seconds |
| Started | Aug 27 04:50:16 PM UTC 24 |
| Finished | Aug 27 04:59:55 PM UTC 24 |
| Peak memory | 279528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756782075 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shad ow_reg_errors_with_csr_rw.1756782075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.1382404385 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 381467664 ps |
| CPU time | 40.18 seconds |
| Started | Aug 27 04:50:20 PM UTC 24 |
| Finished | Aug 27 04:51:02 PM UTC 24 |
| Peak memory | 262752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382404385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1382404385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3457944944 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 2194995777 ps |
| CPU time | 34.12 seconds |
| Started | Aug 27 04:50:21 PM UTC 24 |
| Finished | Aug 27 04:50:57 PM UTC 24 |
| Peak memory | 252500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457944944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3457944944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3068282606 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 59428082 ps |
| CPU time | 12.57 seconds |
| Started | Aug 27 04:51:03 PM UTC 24 |
| Finished | Aug 27 04:51:17 PM UTC 24 |
| Peak memory | 262744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068282606 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem _rw_with_rand_reset.3068282606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.442404961 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 97632995 ps |
| CPU time | 11.84 seconds |
| Started | Aug 27 04:50:52 PM UTC 24 |
| Finished | Aug 27 04:51:05 PM UTC 24 |
| Peak memory | 250528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442404961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.442404961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.2334493977 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 10242921 ps |
| CPU time | 2.47 seconds |
| Started | Aug 27 04:50:47 PM UTC 24 |
| Finished | Aug 27 04:50:51 PM UTC 24 |
| Peak memory | 250412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334493977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2334493977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.4181704850 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 86262778 ps |
| CPU time | 20.53 seconds |
| Started | Aug 27 04:50:58 PM UTC 24 |
| Finished | Aug 27 04:51:20 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181704850 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.4181704850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.712230201 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 6131880395 ps |
| CPU time | 550.92 seconds |
| Started | Aug 27 04:50:31 PM UTC 24 |
| Finished | Aug 27 04:59:50 PM UTC 24 |
| Peak memory | 279592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712230201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shado w_reg_errors_with_csr_rw.712230201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.1600678768 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 132272149 ps |
| CPU time | 26.76 seconds |
| Started | Aug 27 04:50:41 PM UTC 24 |
| Finished | Aug 27 04:51:09 PM UTC 24 |
| Peak memory | 268900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600678768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1600678768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3927258541 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 242264080 ps |
| CPU time | 17.42 seconds |
| Started | Aug 27 04:51:22 PM UTC 24 |
| Finished | Aug 27 04:51:41 PM UTC 24 |
| Peak memory | 264792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927258541 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem _rw_with_rand_reset.3927258541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.2724884326 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 33975836 ps |
| CPU time | 8.79 seconds |
| Started | Aug 27 04:51:20 PM UTC 24 |
| Finished | Aug 27 04:51:30 PM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724884326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2724884326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.1651604088 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 6218320 ps |
| CPU time | 2.2 seconds |
| Started | Aug 27 04:51:17 PM UTC 24 |
| Finished | Aug 27 04:51:21 PM UTC 24 |
| Peak memory | 248488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651604088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1651604088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1539138196 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 746284175 ps |
| CPU time | 34.99 seconds |
| Started | Aug 27 04:51:21 PM UTC 24 |
| Finished | Aug 27 04:51:57 PM UTC 24 |
| Peak memory | 260632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539138196 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.1539138196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.508125065 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 10171452796 ps |
| CPU time | 212.01 seconds |
| Started | Aug 27 04:51:10 PM UTC 24 |
| Finished | Aug 27 04:54:46 PM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508125065 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.508125065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1036570857 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 28552972432 ps |
| CPU time | 594.98 seconds |
| Started | Aug 27 04:51:05 PM UTC 24 |
| Finished | Aug 27 05:01:08 PM UTC 24 |
| Peak memory | 285600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036570857 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shad ow_reg_errors_with_csr_rw.1036570857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.606043148 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1054752711 ps |
| CPU time | 23.45 seconds |
| Started | Aug 27 04:51:17 PM UTC 24 |
| Finished | Aug 27 04:51:42 PM UTC 24 |
| Peak memory | 266988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606043148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.606043148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3906279288 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 14856210700 ps |
| CPU time | 239.45 seconds |
| Started | Aug 27 04:41:22 PM UTC 24 |
| Finished | Aug 27 04:45:25 PM UTC 24 |
| Peak memory | 250460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906279288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3906279288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2079700560 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 10222634844 ps |
| CPU time | 199.3 seconds |
| Started | Aug 27 04:41:18 PM UTC 24 |
| Finished | Aug 27 04:44:41 PM UTC 24 |
| Peak memory | 250532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079700560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2079700560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2987966368 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 67445021 ps |
| CPU time | 8.27 seconds |
| Started | Aug 27 04:41:08 PM UTC 24 |
| Finished | Aug 27 04:41:17 PM UTC 24 |
| Peak memory | 262620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987966368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2987966368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.4059881508 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 40826783 ps |
| CPU time | 9.97 seconds |
| Started | Aug 27 04:42:06 PM UTC 24 |
| Finished | Aug 27 04:42:17 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059881508 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_ rw_with_rand_reset.4059881508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.977859028 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 35721985 ps |
| CPU time | 9.27 seconds |
| Started | Aug 27 04:41:10 PM UTC 24 |
| Finished | Aug 27 04:41:21 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977859028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.977859028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3155481318 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 3308025541 ps |
| CPU time | 31.9 seconds |
| Started | Aug 27 04:41:36 PM UTC 24 |
| Finished | Aug 27 04:42:10 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155481318 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.3155481318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.1148786996 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 587188200 ps |
| CPU time | 17.43 seconds |
| Started | Aug 27 04:40:45 PM UTC 24 |
| Finished | Aug 27 04:41:03 PM UTC 24 |
| Peak memory | 262752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148786996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1148786996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.2271352507 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 6243488 ps |
| CPU time | 2.19 seconds |
| Started | Aug 27 04:51:22 PM UTC 24 |
| Finished | Aug 27 04:51:25 PM UTC 24 |
| Peak memory | 248288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271352507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2271352507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/20.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.601372941 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 9077879 ps |
| CPU time | 2.05 seconds |
| Started | Aug 27 04:51:26 PM UTC 24 |
| Finished | Aug 27 04:51:29 PM UTC 24 |
| Peak memory | 248360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601372941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.601372941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/21.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.1910903066 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 15273305 ps |
| CPU time | 2.32 seconds |
| Started | Aug 27 04:51:31 PM UTC 24 |
| Finished | Aug 27 04:51:34 PM UTC 24 |
| Peak memory | 250412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910903066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1910903066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/22.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.866397116 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 11844090 ps |
| CPU time | 1.96 seconds |
| Started | Aug 27 04:51:31 PM UTC 24 |
| Finished | Aug 27 04:51:34 PM UTC 24 |
| Peak memory | 248780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866397116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.866397116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/23.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.526930805 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 12767534 ps |
| CPU time | 2.14 seconds |
| Started | Aug 27 04:51:33 PM UTC 24 |
| Finished | Aug 27 04:51:36 PM UTC 24 |
| Peak memory | 250336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526930805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.526930805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/24.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.1316238230 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 8302361 ps |
| CPU time | 2.23 seconds |
| Started | Aug 27 04:51:35 PM UTC 24 |
| Finished | Aug 27 04:51:39 PM UTC 24 |
| Peak memory | 250540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316238230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1316238230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/25.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.2281971052 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 8213149 ps |
| CPU time | 2.3 seconds |
| Started | Aug 27 04:51:35 PM UTC 24 |
| Finished | Aug 27 04:51:39 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281971052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2281971052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/26.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.3166420033 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 9535404 ps |
| CPU time | 2.39 seconds |
| Started | Aug 27 04:51:37 PM UTC 24 |
| Finished | Aug 27 04:51:41 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166420033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3166420033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/27.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2647229725 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 13440979 ps |
| CPU time | 2.35 seconds |
| Started | Aug 27 04:51:40 PM UTC 24 |
| Finished | Aug 27 04:51:43 PM UTC 24 |
| Peak memory | 250336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647229725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2647229725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/28.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.699361275 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 10708904 ps |
| CPU time | 1.96 seconds |
| Started | Aug 27 04:51:40 PM UTC 24 |
| Finished | Aug 27 04:51:43 PM UTC 24 |
| Peak memory | 248780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699361275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.699361275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/29.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3600292381 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 11049759354 ps |
| CPU time | 342.75 seconds |
| Started | Aug 27 04:42:49 PM UTC 24 |
| Finished | Aug 27 04:48:37 PM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600292381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3600292381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1873381026 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1639556360 ps |
| CPU time | 180.07 seconds |
| Started | Aug 27 04:42:45 PM UTC 24 |
| Finished | Aug 27 04:45:48 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873381026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1873381026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3562425140 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 195810198 ps |
| CPU time | 14.09 seconds |
| Started | Aug 27 04:42:45 PM UTC 24 |
| Finished | Aug 27 04:43:00 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562425140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3562425140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3207968532 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 192802088 ps |
| CPU time | 19.54 seconds |
| Started | Aug 27 04:42:55 PM UTC 24 |
| Finished | Aug 27 04:43:16 PM UTC 24 |
| Peak memory | 254548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207968532 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_ rw_with_rand_reset.3207968532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.465735935 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 10144023 ps |
| CPU time | 2.21 seconds |
| Started | Aug 27 04:42:41 PM UTC 24 |
| Finished | Aug 27 04:42:44 PM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465735935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.465735935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.224535996 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1480065465 ps |
| CPU time | 61.67 seconds |
| Started | Aug 27 04:42:49 PM UTC 24 |
| Finished | Aug 27 04:43:52 PM UTC 24 |
| Peak memory | 260628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224535996 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.224535996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.4022466898 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3135602275 ps |
| CPU time | 489.05 seconds |
| Started | Aug 27 04:42:11 PM UTC 24 |
| Finished | Aug 27 04:50:27 PM UTC 24 |
| Peak memory | 285736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022466898 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shado w_reg_errors_with_csr_rw.4022466898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.1778628158 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 224624720 ps |
| CPU time | 11 seconds |
| Started | Aug 27 04:42:28 PM UTC 24 |
| Finished | Aug 27 04:42:40 PM UTC 24 |
| Peak memory | 262752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778628158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1778628158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.1255473801 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 7032280 ps |
| CPU time | 2.19 seconds |
| Started | Aug 27 04:51:42 PM UTC 24 |
| Finished | Aug 27 04:51:46 PM UTC 24 |
| Peak memory | 248288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255473801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1255473801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/30.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.1104539456 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 12460676 ps |
| CPU time | 2.22 seconds |
| Started | Aug 27 04:51:42 PM UTC 24 |
| Finished | Aug 27 04:51:46 PM UTC 24 |
| Peak memory | 250336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104539456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1104539456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/31.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1046198468 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 11694040 ps |
| CPU time | 2.06 seconds |
| Started | Aug 27 04:51:44 PM UTC 24 |
| Finished | Aug 27 04:51:47 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046198468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1046198468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/32.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.1412543917 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 10719283 ps |
| CPU time | 2.37 seconds |
| Started | Aug 27 04:51:44 PM UTC 24 |
| Finished | Aug 27 04:51:47 PM UTC 24 |
| Peak memory | 250336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412543917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1412543917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/33.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.4209368858 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 8247721 ps |
| CPU time | 2.36 seconds |
| Started | Aug 27 04:51:44 PM UTC 24 |
| Finished | Aug 27 04:51:47 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209368858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.4209368858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/34.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.3123640423 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 8603879 ps |
| CPU time | 2.35 seconds |
| Started | Aug 27 04:51:46 PM UTC 24 |
| Finished | Aug 27 04:51:50 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123640423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3123640423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/35.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.2156101262 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 11050345 ps |
| CPU time | 2.04 seconds |
| Started | Aug 27 04:51:46 PM UTC 24 |
| Finished | Aug 27 04:51:49 PM UTC 24 |
| Peak memory | 250412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156101262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2156101262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/36.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.3804907134 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 10087328 ps |
| CPU time | 2.44 seconds |
| Started | Aug 27 04:51:49 PM UTC 24 |
| Finished | Aug 27 04:51:52 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804907134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3804907134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/37.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.3609509868 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 12821105 ps |
| CPU time | 2.63 seconds |
| Started | Aug 27 04:51:49 PM UTC 24 |
| Finished | Aug 27 04:51:53 PM UTC 24 |
| Peak memory | 250344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609509868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3609509868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/38.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.1961707522 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 6772580 ps |
| CPU time | 2.28 seconds |
| Started | Aug 27 04:51:49 PM UTC 24 |
| Finished | Aug 27 04:51:52 PM UTC 24 |
| Peak memory | 249316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961707522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1961707522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/39.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.511596050 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 76557014820 ps |
| CPU time | 394.67 seconds |
| Started | Aug 27 04:43:34 PM UTC 24 |
| Finished | Aug 27 04:50:15 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511596050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.511596050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1934096206 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 846502172 ps |
| CPU time | 122.76 seconds |
| Started | Aug 27 04:43:29 PM UTC 24 |
| Finished | Aug 27 04:45:34 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934096206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1934096206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2903698668 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 143095197 ps |
| CPU time | 8.61 seconds |
| Started | Aug 27 04:43:25 PM UTC 24 |
| Finished | Aug 27 04:43:35 PM UTC 24 |
| Peak memory | 262616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903698668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2903698668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3213352119 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 37192623 ps |
| CPU time | 8.69 seconds |
| Started | Aug 27 04:43:43 PM UTC 24 |
| Finished | Aug 27 04:43:53 PM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213352119 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_ rw_with_rand_reset.3213352119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.91415733 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 184053965 ps |
| CPU time | 13.33 seconds |
| Started | Aug 27 04:43:28 PM UTC 24 |
| Finished | Aug 27 04:43:43 PM UTC 24 |
| Peak memory | 250400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91415733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_han dler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.91415733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.662227873 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 10330418 ps |
| CPU time | 2.19 seconds |
| Started | Aug 27 04:43:24 PM UTC 24 |
| Finished | Aug 27 04:43:27 PM UTC 24 |
| Peak memory | 250328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662227873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.662227873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1633910392 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2080402437 ps |
| CPU time | 67.99 seconds |
| Started | Aug 27 04:43:36 PM UTC 24 |
| Finished | Aug 27 04:44:46 PM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633910392 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.1633910392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.465570964 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 2927960573 ps |
| CPU time | 133.19 seconds |
| Started | Aug 27 04:43:00 PM UTC 24 |
| Finished | Aug 27 04:45:16 PM UTC 24 |
| Peak memory | 279660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465570964 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.465570964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2880119089 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 66360848653 ps |
| CPU time | 1412.74 seconds |
| Started | Aug 27 04:42:59 PM UTC 24 |
| Finished | Aug 27 05:06:49 PM UTC 24 |
| Peak memory | 279460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880119089 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shado w_reg_errors_with_csr_rw.2880119089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.2434298407 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 335305642 ps |
| CPU time | 17.85 seconds |
| Started | Aug 27 04:43:09 PM UTC 24 |
| Finished | Aug 27 04:43:29 PM UTC 24 |
| Peak memory | 268900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434298407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2434298407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.4032967410 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 8828157 ps |
| CPU time | 2.42 seconds |
| Started | Aug 27 04:51:49 PM UTC 24 |
| Finished | Aug 27 04:51:52 PM UTC 24 |
| Peak memory | 249540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032967410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.4032967410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/40.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.2090075035 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 8815535 ps |
| CPU time | 2.26 seconds |
| Started | Aug 27 04:51:50 PM UTC 24 |
| Finished | Aug 27 04:51:54 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090075035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2090075035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/41.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.449749746 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 14599195 ps |
| CPU time | 2.06 seconds |
| Started | Aug 27 04:51:50 PM UTC 24 |
| Finished | Aug 27 04:51:53 PM UTC 24 |
| Peak memory | 248288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449749746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.449749746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/42.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.3165420842 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 9353994 ps |
| CPU time | 2.1 seconds |
| Started | Aug 27 04:51:54 PM UTC 24 |
| Finished | Aug 27 04:51:57 PM UTC 24 |
| Peak memory | 248304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165420842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3165420842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/43.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.1149692826 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 6690281 ps |
| CPU time | 2.28 seconds |
| Started | Aug 27 04:51:54 PM UTC 24 |
| Finished | Aug 27 04:51:57 PM UTC 24 |
| Peak memory | 250404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149692826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1149692826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/44.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.3251744416 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 26232112 ps |
| CPU time | 2.23 seconds |
| Started | Aug 27 04:51:54 PM UTC 24 |
| Finished | Aug 27 04:51:57 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251744416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3251744416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/45.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.3962735912 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 10927451 ps |
| CPU time | 2.23 seconds |
| Started | Aug 27 04:51:54 PM UTC 24 |
| Finished | Aug 27 04:51:57 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962735912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3962735912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/46.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.2472012523 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 8292764 ps |
| CPU time | 2.29 seconds |
| Started | Aug 27 04:51:54 PM UTC 24 |
| Finished | Aug 27 04:51:57 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472012523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2472012523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/47.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.2596884485 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 13774127 ps |
| CPU time | 1.75 seconds |
| Started | Aug 27 04:51:55 PM UTC 24 |
| Finished | Aug 27 04:51:58 PM UTC 24 |
| Peak memory | 248780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596884485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2596884485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/48.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.3952765579 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 6860038 ps |
| CPU time | 2.34 seconds |
| Started | Aug 27 04:51:57 PM UTC 24 |
| Finished | Aug 27 04:52:00 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952765579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3952765579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/49.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.116725181 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 148869227 ps |
| CPU time | 16.1 seconds |
| Started | Aug 27 04:44:30 PM UTC 24 |
| Finished | Aug 27 04:44:48 PM UTC 24 |
| Peak memory | 264928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116725181 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_r w_with_rand_reset.116725181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.2125740941 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 263424861 ps |
| CPU time | 11.56 seconds |
| Started | Aug 27 04:44:17 PM UTC 24 |
| Finished | Aug 27 04:44:30 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125740941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2125740941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.2812232070 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 9179983 ps |
| CPU time | 2.09 seconds |
| Started | Aug 27 04:44:13 PM UTC 24 |
| Finished | Aug 27 04:44:16 PM UTC 24 |
| Peak memory | 250340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812232070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2812232070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2013628773 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 185145544 ps |
| CPU time | 31.01 seconds |
| Started | Aug 27 04:44:25 PM UTC 24 |
| Finished | Aug 27 04:44:58 PM UTC 24 |
| Peak memory | 260632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013628773 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.2013628773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3557564856 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 18449386679 ps |
| CPU time | 437.64 seconds |
| Started | Aug 27 04:43:55 PM UTC 24 |
| Finished | Aug 27 04:51:19 PM UTC 24 |
| Peak memory | 279452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557564856 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.3557564856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.2736734323 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 64801981 ps |
| CPU time | 15.24 seconds |
| Started | Aug 27 04:43:56 PM UTC 24 |
| Finished | Aug 27 04:44:12 PM UTC 24 |
| Peak memory | 266852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736734323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2736734323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2651911620 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 165983864 ps |
| CPU time | 8.04 seconds |
| Started | Aug 27 04:44:59 PM UTC 24 |
| Finished | Aug 27 04:45:08 PM UTC 24 |
| Peak memory | 250592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651911620 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_ rw_with_rand_reset.2651911620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.9913672 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 410153133 ps |
| CPU time | 10.45 seconds |
| Started | Aug 27 04:44:56 PM UTC 24 |
| Finished | Aug 27 04:45:08 PM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9913672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.9913672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.3394772739 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 8956325 ps |
| CPU time | 2.38 seconds |
| Started | Aug 27 04:44:55 PM UTC 24 |
| Finished | Aug 27 04:44:59 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394772739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3394772739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2896323497 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 191013524 ps |
| CPU time | 33.32 seconds |
| Started | Aug 27 04:44:57 PM UTC 24 |
| Finished | Aug 27 04:45:32 PM UTC 24 |
| Peak memory | 260632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896323497 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.2896323497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3284128731 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 4665639219 ps |
| CPU time | 427.66 seconds |
| Started | Aug 27 04:44:42 PM UTC 24 |
| Finished | Aug 27 04:51:55 PM UTC 24 |
| Peak memory | 279528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284128731 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shado w_reg_errors_with_csr_rw.3284128731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.3297620089 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 104050765 ps |
| CPU time | 8.64 seconds |
| Started | Aug 27 04:44:47 PM UTC 24 |
| Finished | Aug 27 04:44:57 PM UTC 24 |
| Peak memory | 266852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297620089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3297620089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.684191980 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 128679218 ps |
| CPU time | 9.57 seconds |
| Started | Aug 27 04:45:26 PM UTC 24 |
| Finished | Aug 27 04:45:36 PM UTC 24 |
| Peak memory | 252500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684191980 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_r w_with_rand_reset.684191980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.3424624543 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 101790298 ps |
| CPU time | 8.08 seconds |
| Started | Aug 27 04:45:17 PM UTC 24 |
| Finished | Aug 27 04:45:27 PM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424624543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3424624543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.361441093 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 9270451 ps |
| CPU time | 2.33 seconds |
| Started | Aug 27 04:45:15 PM UTC 24 |
| Finished | Aug 27 04:45:19 PM UTC 24 |
| Peak memory | 250528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361441093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.361441093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2317638314 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 646546198 ps |
| CPU time | 37.69 seconds |
| Started | Aug 27 04:45:19 PM UTC 24 |
| Finished | Aug 27 04:45:59 PM UTC 24 |
| Peak memory | 260632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317638314 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.2317638314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.861141166 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 13845692155 ps |
| CPU time | 174.19 seconds |
| Started | Aug 27 04:45:05 PM UTC 24 |
| Finished | Aug 27 04:48:03 PM UTC 24 |
| Peak memory | 279596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861141166 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.861141166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.497561764 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 6521436918 ps |
| CPU time | 577.66 seconds |
| Started | Aug 27 04:45:00 PM UTC 24 |
| Finished | Aug 27 04:54:46 PM UTC 24 |
| Peak memory | 279536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497561764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow _reg_errors_with_csr_rw.497561764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.4024869508 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 945776823 ps |
| CPU time | 27.47 seconds |
| Started | Aug 27 04:45:09 PM UTC 24 |
| Finished | Aug 27 04:45:38 PM UTC 24 |
| Peak memory | 262748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024869508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.4024869508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2683702771 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 468839496 ps |
| CPU time | 9.19 seconds |
| Started | Aug 27 04:45:50 PM UTC 24 |
| Finished | Aug 27 04:46:01 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683702771 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_ rw_with_rand_reset.2683702771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.1711809513 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 377599659 ps |
| CPU time | 9.7 seconds |
| Started | Aug 27 04:45:43 PM UTC 24 |
| Finished | Aug 27 04:45:54 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711809513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1711809513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.1609490254 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 10290960 ps |
| CPU time | 2.52 seconds |
| Started | Aug 27 04:45:39 PM UTC 24 |
| Finished | Aug 27 04:45:43 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609490254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1609490254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1833678110 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 168903229 ps |
| CPU time | 14.28 seconds |
| Started | Aug 27 04:45:44 PM UTC 24 |
| Finished | Aug 27 04:46:00 PM UTC 24 |
| Peak memory | 260632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833678110 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.1833678110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1182308113 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 2140228400 ps |
| CPU time | 165.38 seconds |
| Started | Aug 27 04:45:33 PM UTC 24 |
| Finished | Aug 27 04:48:21 PM UTC 24 |
| Peak memory | 279464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182308113 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.1182308113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3757582648 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 9942083838 ps |
| CPU time | 385.88 seconds |
| Started | Aug 27 04:45:28 PM UTC 24 |
| Finished | Aug 27 04:51:59 PM UTC 24 |
| Peak memory | 279592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757582648 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shado w_reg_errors_with_csr_rw.3757582648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.3736312101 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 860679736 ps |
| CPU time | 17.38 seconds |
| Started | Aug 27 04:45:35 PM UTC 24 |
| Finished | Aug 27 04:45:54 PM UTC 24 |
| Peak memory | 262816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736312101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3736312101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2398007543 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 122864323 ps |
| CPU time | 13.67 seconds |
| Started | Aug 27 04:46:01 PM UTC 24 |
| Finished | Aug 27 04:46:16 PM UTC 24 |
| Peak memory | 268884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398007543 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_ rw_with_rand_reset.2398007543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.817895869 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 586224534 ps |
| CPU time | 11.18 seconds |
| Started | Aug 27 04:46:00 PM UTC 24 |
| Finished | Aug 27 04:46:12 PM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817895869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.817895869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.820952331 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 8356175 ps |
| CPU time | 1.55 seconds |
| Started | Aug 27 04:46:00 PM UTC 24 |
| Finished | Aug 27 04:46:02 PM UTC 24 |
| Peak memory | 248832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820952331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.820952331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1244526574 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 873351610 ps |
| CPU time | 22.18 seconds |
| Started | Aug 27 04:46:00 PM UTC 24 |
| Finished | Aug 27 04:46:23 PM UTC 24 |
| Peak memory | 260632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244526574 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.1244526574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.151480638 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 13415601304 ps |
| CPU time | 1074.15 seconds |
| Started | Aug 27 04:45:50 PM UTC 24 |
| Finished | Aug 27 05:03:58 PM UTC 24 |
| Peak memory | 285740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151480638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow _reg_errors_with_csr_rw.151480638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.3955800374 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 332636810 ps |
| CPU time | 19.1 seconds |
| Started | Aug 27 04:45:55 PM UTC 24 |
| Finished | Aug 27 04:46:15 PM UTC 24 |
| Peak memory | 262756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955800374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3955800374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.87783172 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 75312087362 ps |
| CPU time | 865.49 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:27:07 PM UTC 24 |
| Peak memory | 288428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87783172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/a lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.87783172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.2083372294 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2649495716 ps |
| CPU time | 23.48 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:13:09 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083372294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2083372294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.3350212080 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 33596539 ps |
| CPU time | 2.32 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:12:37 PM UTC 24 |
| Peak memory | 264976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350212080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3350212080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.2437128356 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 15561834379 ps |
| CPU time | 1306.91 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:34:46 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437128356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2437128356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.3105389830 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3522475788 ps |
| CPU time | 137.58 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:15:04 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105389830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3105389830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.815027444 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1072374453 ps |
| CPU time | 19.41 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:12:54 PM UTC 24 |
| Peak memory | 262868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815027444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.815027444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.1869746272 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 584635446 ps |
| CPU time | 27.35 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:13:02 PM UTC 24 |
| Peak memory | 269440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869746272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1869746272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.2466338703 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1342680520 ps |
| CPU time | 38.99 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:13:32 PM UTC 24 |
| Peak memory | 297456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466338703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2466338703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.622493516 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 19022088043 ps |
| CPU time | 1816.93 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:43:29 PM UTC 24 |
| Peak memory | 316964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622493516 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.622493516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.1365764313 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 44889571089 ps |
| CPU time | 1300.72 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:34:45 PM UTC 24 |
| Peak memory | 298452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365764313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1365764313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.3356870661 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 628697727 ps |
| CPU time | 20.39 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:13:13 PM UTC 24 |
| Peak memory | 263104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356870661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3356870661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.2552989892 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 36969365427 ps |
| CPU time | 287.55 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:17:43 PM UTC 24 |
| Peak memory | 269104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552989892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2552989892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg.2525579133 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 22657889029 ps |
| CPU time | 1846.84 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:43:58 PM UTC 24 |
| Peak memory | 288200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525579133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2525579133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.4058653093 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 87931032187 ps |
| CPU time | 1246.1 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:33:48 PM UTC 24 |
| Peak memory | 288224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058653093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.4058653093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.129405600 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 880621534 ps |
| CPU time | 14.77 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:13:07 PM UTC 24 |
| Peak memory | 262936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129405600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.129405600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.3471740059 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 158728126 ps |
| CPU time | 16.17 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:13:09 PM UTC 24 |
| Peak memory | 269152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471740059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3471740059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.1589412726 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 841756337 ps |
| CPU time | 32.61 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:13:26 PM UTC 24 |
| Peak memory | 295268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589412726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1589412726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.22195568 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 226527331 ps |
| CPU time | 10.17 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:12:50 PM UTC 24 |
| Peak memory | 269380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22195568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig _int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.22195568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.2505636560 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 6426795543 ps |
| CPU time | 38.51 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:13:31 PM UTC 24 |
| Peak memory | 269444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505636560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2505636560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.1393457990 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 55545857801 ps |
| CPU time | 3298.19 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 04:08:25 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393457990 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.1393457990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.4042883313 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 64865495274 ps |
| CPU time | 2222.9 seconds |
| Started | Aug 27 03:16:17 PM UTC 24 |
| Finished | Aug 27 03:53:47 PM UTC 24 |
| Peak memory | 285824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042883313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.4042883313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.586320849 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1557090948 ps |
| CPU time | 51.89 seconds |
| Started | Aug 27 03:16:48 PM UTC 24 |
| Finished | Aug 27 03:17:41 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586320849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.586320849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.575922245 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 8628949401 ps |
| CPU time | 240.35 seconds |
| Started | Aug 27 03:16:16 PM UTC 24 |
| Finished | Aug 27 03:20:20 PM UTC 24 |
| Peak memory | 269468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575922245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.575922245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.439596283 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 417549293 ps |
| CPU time | 33.55 seconds |
| Started | Aug 27 03:16:13 PM UTC 24 |
| Finished | Aug 27 03:16:48 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439596283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.439596283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.2946474641 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 30588961330 ps |
| CPU time | 2091.41 seconds |
| Started | Aug 27 03:16:40 PM UTC 24 |
| Finished | Aug 27 03:51:56 PM UTC 24 |
| Peak memory | 298116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946474641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2946474641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.2094339377 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 98702607722 ps |
| CPU time | 1597.11 seconds |
| Started | Aug 27 03:16:41 PM UTC 24 |
| Finished | Aug 27 03:43:37 PM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094339377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2094339377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.3226216272 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4096461719 ps |
| CPU time | 240.44 seconds |
| Started | Aug 27 03:16:29 PM UTC 24 |
| Finished | Aug 27 03:20:34 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226216272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3226216272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.3626638614 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 815373390 ps |
| CPU time | 32.56 seconds |
| Started | Aug 27 03:15:54 PM UTC 24 |
| Finished | Aug 27 03:16:28 PM UTC 24 |
| Peak memory | 269060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626638614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3626638614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.2921255277 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1646753475 ps |
| CPU time | 48.68 seconds |
| Started | Aug 27 03:15:58 PM UTC 24 |
| Finished | Aug 27 03:16:49 PM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921255277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2921255277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.1354224409 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 457739310 ps |
| CPU time | 19.27 seconds |
| Started | Aug 27 03:15:54 PM UTC 24 |
| Finished | Aug 27 03:16:15 PM UTC 24 |
| Peak memory | 263240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354224409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1354224409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.2749733184 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 75908767 ps |
| CPU time | 6.11 seconds |
| Started | Aug 27 03:18:13 PM UTC 24 |
| Finished | Aug 27 03:18:21 PM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749733184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2749733184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.582386983 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 33809391032 ps |
| CPU time | 2193.13 seconds |
| Started | Aug 27 03:17:44 PM UTC 24 |
| Finished | Aug 27 03:54:43 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582386983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.582386983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.1871129317 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 150359566 ps |
| CPU time | 14.2 seconds |
| Started | Aug 27 03:18:01 PM UTC 24 |
| Finished | Aug 27 03:18:16 PM UTC 24 |
| Peak memory | 263240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871129317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1871129317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.536194008 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1700600899 ps |
| CPU time | 98.81 seconds |
| Started | Aug 27 03:17:40 PM UTC 24 |
| Finished | Aug 27 03:19:21 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536194008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.536194008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.1936985568 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1418422676 ps |
| CPU time | 34.82 seconds |
| Started | Aug 27 03:17:28 PM UTC 24 |
| Finished | Aug 27 03:18:04 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936985568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1936985568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.212104424 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 48141719489 ps |
| CPU time | 974.56 seconds |
| Started | Aug 27 03:17:52 PM UTC 24 |
| Finished | Aug 27 03:34:18 PM UTC 24 |
| Peak memory | 285492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212104424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.212104424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.4132005877 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 10989624571 ps |
| CPU time | 966.25 seconds |
| Started | Aug 27 03:17:57 PM UTC 24 |
| Finished | Aug 27 03:34:14 PM UTC 24 |
| Peak memory | 295816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132005877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.4132005877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.1312281749 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 9066593012 ps |
| CPU time | 44.12 seconds |
| Started | Aug 27 03:17:15 PM UTC 24 |
| Finished | Aug 27 03:18:00 PM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312281749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1312281749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.1032686661 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2502973328 ps |
| CPU time | 49.3 seconds |
| Started | Aug 27 03:17:25 PM UTC 24 |
| Finished | Aug 27 03:18:15 PM UTC 24 |
| Peak memory | 263324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032686661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1032686661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.3815317659 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 36931220 ps |
| CPU time | 7.25 seconds |
| Started | Aug 27 03:17:42 PM UTC 24 |
| Finished | Aug 27 03:17:50 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815317659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3815317659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.2091099484 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 184306273 ps |
| CPU time | 7.84 seconds |
| Started | Aug 27 03:17:14 PM UTC 24 |
| Finished | Aug 27 03:17:23 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091099484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2091099484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/11.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.2598139070 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 76663795 ps |
| CPU time | 3.56 seconds |
| Started | Aug 27 03:19:44 PM UTC 24 |
| Finished | Aug 27 03:19:49 PM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598139070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2598139070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.2754252558 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 13607902837 ps |
| CPU time | 1525.07 seconds |
| Started | Aug 27 03:18:51 PM UTC 24 |
| Finished | Aug 27 03:44:34 PM UTC 24 |
| Peak memory | 301952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754252558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2754252558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.2374523104 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 378356163 ps |
| CPU time | 9.47 seconds |
| Started | Aug 27 03:19:22 PM UTC 24 |
| Finished | Aug 27 03:19:33 PM UTC 24 |
| Peak memory | 263240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374523104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2374523104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.1933729761 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 830560091 ps |
| CPU time | 27.41 seconds |
| Started | Aug 27 03:18:25 PM UTC 24 |
| Finished | Aug 27 03:18:54 PM UTC 24 |
| Peak memory | 269436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933729761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1933729761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.603501665 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 583805256 ps |
| CPU time | 25.96 seconds |
| Started | Aug 27 03:18:22 PM UTC 24 |
| Finished | Aug 27 03:18:49 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603501665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.603501665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.2939018428 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 19567322878 ps |
| CPU time | 1192.42 seconds |
| Started | Aug 27 03:18:52 PM UTC 24 |
| Finished | Aug 27 03:38:57 PM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939018428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2939018428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.2189936932 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 71380677200 ps |
| CPU time | 2537.46 seconds |
| Started | Aug 27 03:18:55 PM UTC 24 |
| Finished | Aug 27 04:01:41 PM UTC 24 |
| Peak memory | 288300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189936932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2189936932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.1302286395 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 17879989496 ps |
| CPU time | 308.47 seconds |
| Started | Aug 27 03:18:52 PM UTC 24 |
| Finished | Aug 27 03:24:04 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302286395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1302286395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.2232292517 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 475534557 ps |
| CPU time | 30.33 seconds |
| Started | Aug 27 03:18:18 PM UTC 24 |
| Finished | Aug 27 03:18:49 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232292517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2232292517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.2156644127 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 315070342 ps |
| CPU time | 29.99 seconds |
| Started | Aug 27 03:18:20 PM UTC 24 |
| Finished | Aug 27 03:18:51 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156644127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2156644127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.602393410 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3021937791 ps |
| CPU time | 75.74 seconds |
| Started | Aug 27 03:18:51 PM UTC 24 |
| Finished | Aug 27 03:20:08 PM UTC 24 |
| Peak memory | 263328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602393410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.602393410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.1932497469 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 527572220 ps |
| CPU time | 32.24 seconds |
| Started | Aug 27 03:18:17 PM UTC 24 |
| Finished | Aug 27 03:18:51 PM UTC 24 |
| Peak memory | 263240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932497469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1932497469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all_with_rand_reset.3617753805 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 4609674222 ps |
| CPU time | 220.79 seconds |
| Started | Aug 27 03:19:49 PM UTC 24 |
| Finished | Aug 27 03:23:34 PM UTC 24 |
| Peak memory | 285636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3617753805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.a lert_handler_stress_all_with_rand_reset.3617753805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.168467287 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 118749335 ps |
| CPU time | 4.99 seconds |
| Started | Aug 27 03:21:58 PM UTC 24 |
| Finished | Aug 27 03:22:04 PM UTC 24 |
| Peak memory | 263568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168467287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.168467287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.778726275 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 104757555769 ps |
| CPU time | 1845.97 seconds |
| Started | Aug 27 03:20:57 PM UTC 24 |
| Finished | Aug 27 03:52:05 PM UTC 24 |
| Peak memory | 297788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778726275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.778726275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.333654551 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1694255961 ps |
| CPU time | 54.43 seconds |
| Started | Aug 27 03:21:18 PM UTC 24 |
| Finished | Aug 27 03:22:14 PM UTC 24 |
| Peak memory | 262920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333654551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.333654551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.3242985861 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1839531173 ps |
| CPU time | 139.78 seconds |
| Started | Aug 27 03:20:35 PM UTC 24 |
| Finished | Aug 27 03:22:58 PM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242985861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3242985861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.2922202635 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 437900283 ps |
| CPU time | 41.81 seconds |
| Started | Aug 27 03:20:34 PM UTC 24 |
| Finished | Aug 27 03:21:17 PM UTC 24 |
| Peak memory | 269080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922202635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2922202635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.213781486 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 55555290653 ps |
| CPU time | 1334.63 seconds |
| Started | Aug 27 03:21:01 PM UTC 24 |
| Finished | Aug 27 03:43:30 PM UTC 24 |
| Peak memory | 285692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213781486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.213781486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.801218186 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 18444616478 ps |
| CPU time | 953.36 seconds |
| Started | Aug 27 03:21:18 PM UTC 24 |
| Finished | Aug 27 03:37:23 PM UTC 24 |
| Peak memory | 283524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801218186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.801218186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.3057647088 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 5960421967 ps |
| CPU time | 181.35 seconds |
| Started | Aug 27 03:20:59 PM UTC 24 |
| Finished | Aug 27 03:24:03 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057647088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3057647088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.3608884606 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 154693800 ps |
| CPU time | 9.89 seconds |
| Started | Aug 27 03:20:21 PM UTC 24 |
| Finished | Aug 27 03:20:32 PM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608884606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3608884606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.3207837907 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 987427040 ps |
| CPU time | 21.61 seconds |
| Started | Aug 27 03:20:33 PM UTC 24 |
| Finished | Aug 27 03:20:56 PM UTC 24 |
| Peak memory | 262928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207837907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3207837907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.2236052643 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 744799246 ps |
| CPU time | 64.07 seconds |
| Started | Aug 27 03:20:50 PM UTC 24 |
| Finished | Aug 27 03:21:56 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236052643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2236052643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.1801307402 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 3864389060 ps |
| CPU time | 46.35 seconds |
| Started | Aug 27 03:20:10 PM UTC 24 |
| Finished | Aug 27 03:20:58 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801307402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1801307402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/13.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.1092342618 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 183325241032 ps |
| CPU time | 2702.06 seconds |
| Started | Aug 27 03:23:35 PM UTC 24 |
| Finished | Aug 27 04:09:07 PM UTC 24 |
| Peak memory | 300580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092342618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1092342618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.2448839150 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 194883586 ps |
| CPU time | 17.19 seconds |
| Started | Aug 27 03:24:04 PM UTC 24 |
| Finished | Aug 27 03:24:22 PM UTC 24 |
| Peak memory | 263240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448839150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2448839150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.712882663 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 5367720466 ps |
| CPU time | 341.09 seconds |
| Started | Aug 27 03:23:25 PM UTC 24 |
| Finished | Aug 27 03:29:10 PM UTC 24 |
| Peak memory | 269468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712882663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.712882663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.1279828608 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 318889729 ps |
| CPU time | 24.13 seconds |
| Started | Aug 27 03:23:05 PM UTC 24 |
| Finished | Aug 27 03:23:30 PM UTC 24 |
| Peak memory | 269472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279828608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1279828608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.2231628888 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 28041812950 ps |
| CPU time | 1700 seconds |
| Started | Aug 27 03:23:57 PM UTC 24 |
| Finished | Aug 27 03:52:35 PM UTC 24 |
| Peak memory | 295740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231628888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2231628888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.2621689701 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 516191359 ps |
| CPU time | 23.36 seconds |
| Started | Aug 27 03:22:39 PM UTC 24 |
| Finished | Aug 27 03:23:04 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621689701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2621689701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.3321850577 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 417384305 ps |
| CPU time | 37.41 seconds |
| Started | Aug 27 03:22:58 PM UTC 24 |
| Finished | Aug 27 03:23:37 PM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321850577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3321850577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.851552738 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 235300871 ps |
| CPU time | 11.01 seconds |
| Started | Aug 27 03:23:31 PM UTC 24 |
| Finished | Aug 27 03:23:43 PM UTC 24 |
| Peak memory | 265312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851552738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.851552738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.2266688176 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 987799099 ps |
| CPU time | 21.7 seconds |
| Started | Aug 27 03:22:15 PM UTC 24 |
| Finished | Aug 27 03:22:39 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266688176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2266688176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all_with_rand_reset.1634641589 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 2570428760 ps |
| CPU time | 398.31 seconds |
| Started | Aug 27 03:24:29 PM UTC 24 |
| Finished | Aug 27 03:31:13 PM UTC 24 |
| Peak memory | 286020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1634641589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.a lert_handler_stress_all_with_rand_reset.1634641589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.3983395327 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 136956712 ps |
| CPU time | 3.72 seconds |
| Started | Aug 27 03:29:27 PM UTC 24 |
| Finished | Aug 27 03:29:32 PM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983395327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3983395327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy.2215681379 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 255999737975 ps |
| CPU time | 3329.22 seconds |
| Started | Aug 27 03:28:28 PM UTC 24 |
| Finished | Aug 27 04:24:32 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215681379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2215681379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.4121415139 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 195791425 ps |
| CPU time | 13.73 seconds |
| Started | Aug 27 03:29:11 PM UTC 24 |
| Finished | Aug 27 03:29:26 PM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121415139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4121415139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.1114169495 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 1711510465 ps |
| CPU time | 130.36 seconds |
| Started | Aug 27 03:27:45 PM UTC 24 |
| Finished | Aug 27 03:29:58 PM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114169495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1114169495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.105437519 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 986651892 ps |
| CPU time | 32.81 seconds |
| Started | Aug 27 03:27:43 PM UTC 24 |
| Finished | Aug 27 03:28:17 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105437519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.105437519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.2327247010 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 28074981773 ps |
| CPU time | 1370.63 seconds |
| Started | Aug 27 03:28:30 PM UTC 24 |
| Finished | Aug 27 03:51:37 PM UTC 24 |
| Peak memory | 301960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327247010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2327247010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.1252121847 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1240415583 ps |
| CPU time | 36.74 seconds |
| Started | Aug 27 03:27:20 PM UTC 24 |
| Finished | Aug 27 03:27:58 PM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252121847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1252121847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.444452734 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 346318377 ps |
| CPU time | 27.93 seconds |
| Started | Aug 27 03:27:42 PM UTC 24 |
| Finished | Aug 27 03:28:11 PM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444452734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.444452734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.599676408 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 618386775 ps |
| CPU time | 13.45 seconds |
| Started | Aug 27 03:27:59 PM UTC 24 |
| Finished | Aug 27 03:28:14 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599676408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.599676408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.246578075 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1674601029 ps |
| CPU time | 31.58 seconds |
| Started | Aug 27 03:27:09 PM UTC 24 |
| Finished | Aug 27 03:27:42 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246578075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.246578075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all_with_rand_reset.2725096812 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 3804723285 ps |
| CPU time | 367.6 seconds |
| Started | Aug 27 03:29:33 PM UTC 24 |
| Finished | Aug 27 03:35:46 PM UTC 24 |
| Peak memory | 279812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2725096812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.a lert_handler_stress_all_with_rand_reset.2725096812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/15.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.617220652 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 248619474 ps |
| CPU time | 4.34 seconds |
| Started | Aug 27 03:34:16 PM UTC 24 |
| Finished | Aug 27 03:34:21 PM UTC 24 |
| Peak memory | 263176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617220652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.617220652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.1985508509 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 101015647398 ps |
| CPU time | 1753.19 seconds |
| Started | Aug 27 03:31:03 PM UTC 24 |
| Finished | Aug 27 04:00:36 PM UTC 24 |
| Peak memory | 285824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985508509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1985508509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.3212957739 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 244163186 ps |
| CPU time | 19.08 seconds |
| Started | Aug 27 03:33:50 PM UTC 24 |
| Finished | Aug 27 03:34:10 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212957739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3212957739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.1548768687 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 7647566624 ps |
| CPU time | 209.92 seconds |
| Started | Aug 27 03:30:10 PM UTC 24 |
| Finished | Aug 27 03:33:44 PM UTC 24 |
| Peak memory | 269104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548768687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1548768687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.3234954935 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 883615025 ps |
| CPU time | 42.51 seconds |
| Started | Aug 27 03:30:01 PM UTC 24 |
| Finished | Aug 27 03:30:45 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234954935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3234954935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.3007821242 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 225768206375 ps |
| CPU time | 3191.6 seconds |
| Started | Aug 27 03:31:21 PM UTC 24 |
| Finished | Aug 27 04:25:07 PM UTC 24 |
| Peak memory | 304936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007821242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3007821242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.1572929164 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 31589241122 ps |
| CPU time | 2381.55 seconds |
| Started | Aug 27 03:33:46 PM UTC 24 |
| Finished | Aug 27 04:13:56 PM UTC 24 |
| Peak memory | 298464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572929164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1572929164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.3877168537 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 112993218 ps |
| CPU time | 7.39 seconds |
| Started | Aug 27 03:29:52 PM UTC 24 |
| Finished | Aug 27 03:30:00 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877168537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3877168537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.929758951 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1016773580 ps |
| CPU time | 79.36 seconds |
| Started | Aug 27 03:29:59 PM UTC 24 |
| Finished | Aug 27 03:31:20 PM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929758951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.929758951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.2040037025 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 235406839 ps |
| CPU time | 14.38 seconds |
| Started | Aug 27 03:30:47 PM UTC 24 |
| Finished | Aug 27 03:31:02 PM UTC 24 |
| Peak memory | 266996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040037025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2040037025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.2814272292 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1277864330 ps |
| CPU time | 20.12 seconds |
| Started | Aug 27 03:29:47 PM UTC 24 |
| Finished | Aug 27 03:30:09 PM UTC 24 |
| Peak memory | 267080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814272292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2814272292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.3810839864 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 32302520625 ps |
| CPU time | 2119.51 seconds |
| Started | Aug 27 03:34:11 PM UTC 24 |
| Finished | Aug 27 04:09:55 PM UTC 24 |
| Peak memory | 302628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810839864 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.3810839864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/16.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.205906133 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 20373153 ps |
| CPU time | 3.5 seconds |
| Started | Aug 27 03:36:13 PM UTC 24 |
| Finished | Aug 27 03:36:18 PM UTC 24 |
| Peak memory | 263376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205906133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.205906133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.2056993381 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 101584322412 ps |
| CPU time | 1793.11 seconds |
| Started | Aug 27 03:35:35 PM UTC 24 |
| Finished | Aug 27 04:05:50 PM UTC 24 |
| Peak memory | 285824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056993381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2056993381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.1064536559 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 271765006 ps |
| CPU time | 11.33 seconds |
| Started | Aug 27 03:36:00 PM UTC 24 |
| Finished | Aug 27 03:36:13 PM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064536559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1064536559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.1879489940 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 6712754364 ps |
| CPU time | 137.66 seconds |
| Started | Aug 27 03:34:50 PM UTC 24 |
| Finished | Aug 27 03:37:10 PM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879489940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1879489940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.2518638801 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2154769110 ps |
| CPU time | 75.93 seconds |
| Started | Aug 27 03:34:48 PM UTC 24 |
| Finished | Aug 27 03:36:05 PM UTC 24 |
| Peak memory | 269144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518638801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2518638801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.3049978432 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 34344993856 ps |
| CPU time | 1244 seconds |
| Started | Aug 27 03:35:47 PM UTC 24 |
| Finished | Aug 27 03:56:44 PM UTC 24 |
| Peak memory | 295808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049978432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3049978432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.1003843212 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 294318455607 ps |
| CPU time | 1921.75 seconds |
| Started | Aug 27 03:35:53 PM UTC 24 |
| Finished | Aug 27 04:08:16 PM UTC 24 |
| Peak memory | 288620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003843212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1003843212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.554104829 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 12499758233 ps |
| CPU time | 270.57 seconds |
| Started | Aug 27 03:35:41 PM UTC 24 |
| Finished | Aug 27 03:40:16 PM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554104829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.554104829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.2229165944 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 597611342 ps |
| CPU time | 55.43 seconds |
| Started | Aug 27 03:34:37 PM UTC 24 |
| Finished | Aug 27 03:35:34 PM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229165944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2229165944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.152004743 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 2432908680 ps |
| CPU time | 51.23 seconds |
| Started | Aug 27 03:34:48 PM UTC 24 |
| Finished | Aug 27 03:35:40 PM UTC 24 |
| Peak memory | 263324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152004743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.152004743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.284652989 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 2568670599 ps |
| CPU time | 43.82 seconds |
| Started | Aug 27 03:35:07 PM UTC 24 |
| Finished | Aug 27 03:35:52 PM UTC 24 |
| Peak memory | 263000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284652989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.284652989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.134838726 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 514932732 ps |
| CPU time | 22.38 seconds |
| Started | Aug 27 03:34:22 PM UTC 24 |
| Finished | Aug 27 03:34:45 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134838726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.134838726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.1369885544 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 22195984688 ps |
| CPU time | 1094.76 seconds |
| Started | Aug 27 03:36:06 PM UTC 24 |
| Finished | Aug 27 03:54:34 PM UTC 24 |
| Peak memory | 302208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369885544 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.1369885544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all_with_rand_reset.81425316 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 15230137701 ps |
| CPU time | 583.98 seconds |
| Started | Aug 27 03:36:18 PM UTC 24 |
| Finished | Aug 27 03:46:10 PM UTC 24 |
| Peak memory | 285628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=81425316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.ale rt_handler_stress_all_with_rand_reset.81425316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.1690017877 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 39560557 ps |
| CPU time | 5.31 seconds |
| Started | Aug 27 03:38:43 PM UTC 24 |
| Finished | Aug 27 03:38:49 PM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690017877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1690017877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.3746573999 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 14677712933 ps |
| CPU time | 1362.81 seconds |
| Started | Aug 27 03:37:58 PM UTC 24 |
| Finished | Aug 27 04:00:57 PM UTC 24 |
| Peak memory | 297784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746573999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3746573999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.368699833 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 202092275 ps |
| CPU time | 18.22 seconds |
| Started | Aug 27 03:38:35 PM UTC 24 |
| Finished | Aug 27 03:38:54 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368699833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.368699833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.457243954 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 18233205291 ps |
| CPU time | 172.58 seconds |
| Started | Aug 27 03:37:33 PM UTC 24 |
| Finished | Aug 27 03:40:29 PM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457243954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.457243954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.2896748702 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1070093465 ps |
| CPU time | 24.21 seconds |
| Started | Aug 27 03:37:31 PM UTC 24 |
| Finished | Aug 27 03:37:57 PM UTC 24 |
| Peak memory | 269408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896748702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2896748702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.124075712 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 60889857331 ps |
| CPU time | 1673.62 seconds |
| Started | Aug 27 03:38:13 PM UTC 24 |
| Finished | Aug 27 04:06:25 PM UTC 24 |
| Peak memory | 295804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124075712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.124075712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.1358275234 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 41615972032 ps |
| CPU time | 2665.78 seconds |
| Started | Aug 27 03:38:19 PM UTC 24 |
| Finished | Aug 27 04:23:14 PM UTC 24 |
| Peak memory | 298540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358275234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1358275234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.3153963654 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1395792932 ps |
| CPU time | 64.45 seconds |
| Started | Aug 27 03:37:12 PM UTC 24 |
| Finished | Aug 27 03:38:18 PM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153963654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3153963654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.113276848 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 43631942 ps |
| CPU time | 5.85 seconds |
| Started | Aug 27 03:37:25 PM UTC 24 |
| Finished | Aug 27 03:37:32 PM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113276848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.113276848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.3111114584 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1323742429 ps |
| CPU time | 42.16 seconds |
| Started | Aug 27 03:37:53 PM UTC 24 |
| Finished | Aug 27 03:38:37 PM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111114584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3111114584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.2504204703 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1431682605 ps |
| CPU time | 79.05 seconds |
| Started | Aug 27 03:36:31 PM UTC 24 |
| Finished | Aug 27 03:37:53 PM UTC 24 |
| Peak memory | 269384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504204703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2504204703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.1309624191 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 78980056358 ps |
| CPU time | 2280.34 seconds |
| Started | Aug 27 03:38:38 PM UTC 24 |
| Finished | Aug 27 04:17:06 PM UTC 24 |
| Peak memory | 320988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309624191 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.1309624191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all_with_rand_reset.861866285 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 9926389106 ps |
| CPU time | 469.16 seconds |
| Started | Aug 27 03:38:50 PM UTC 24 |
| Finished | Aug 27 03:46:45 PM UTC 24 |
| Peak memory | 285952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=861866285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.al ert_handler_stress_all_with_rand_reset.861866285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.1421536962 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 46426180 ps |
| CPU time | 5.51 seconds |
| Started | Aug 27 03:40:29 PM UTC 24 |
| Finished | Aug 27 03:40:36 PM UTC 24 |
| Peak memory | 263440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421536962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1421536962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.1366412801 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 83146220911 ps |
| CPU time | 1860.98 seconds |
| Started | Aug 27 03:39:38 PM UTC 24 |
| Finished | Aug 27 04:11:00 PM UTC 24 |
| Peak memory | 301876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366412801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1366412801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.3208346170 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 803920898 ps |
| CPU time | 15.97 seconds |
| Started | Aug 27 03:40:17 PM UTC 24 |
| Finished | Aug 27 03:40:34 PM UTC 24 |
| Peak memory | 263240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208346170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3208346170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.1834789930 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1986760621 ps |
| CPU time | 153.69 seconds |
| Started | Aug 27 03:39:24 PM UTC 24 |
| Finished | Aug 27 03:42:00 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834789930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1834789930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.3797957390 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1383902281 ps |
| CPU time | 31.71 seconds |
| Started | Aug 27 03:39:23 PM UTC 24 |
| Finished | Aug 27 03:39:56 PM UTC 24 |
| Peak memory | 269152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797957390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3797957390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.475350394 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 10817353374 ps |
| CPU time | 727.67 seconds |
| Started | Aug 27 03:39:57 PM UTC 24 |
| Finished | Aug 27 03:52:13 PM UTC 24 |
| Peak memory | 285628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475350394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.475350394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.3247091502 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 110458000007 ps |
| CPU time | 1873.76 seconds |
| Started | Aug 27 03:40:08 PM UTC 24 |
| Finished | Aug 27 04:11:43 PM UTC 24 |
| Peak memory | 285504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247091502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3247091502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.1587087563 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 3072023633 ps |
| CPU time | 189.24 seconds |
| Started | Aug 27 03:39:53 PM UTC 24 |
| Finished | Aug 27 03:43:05 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587087563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1587087563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.3623597602 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 8858703757 ps |
| CPU time | 55.02 seconds |
| Started | Aug 27 03:39:10 PM UTC 24 |
| Finished | Aug 27 03:40:07 PM UTC 24 |
| Peak memory | 263068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623597602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3623597602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.1127857824 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 457102284 ps |
| CPU time | 39.9 seconds |
| Started | Aug 27 03:39:11 PM UTC 24 |
| Finished | Aug 27 03:39:52 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127857824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1127857824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.2030526682 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1940598640 ps |
| CPU time | 76.07 seconds |
| Started | Aug 27 03:39:10 PM UTC 24 |
| Finished | Aug 27 03:40:29 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030526682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2030526682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/19.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.2088476974 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 44595385 ps |
| CPU time | 2.66 seconds |
| Started | Aug 27 03:12:24 PM UTC 24 |
| Finished | Aug 27 03:12:55 PM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088476974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2088476974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.161030578 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 50809179546 ps |
| CPU time | 2745.93 seconds |
| Started | Aug 27 03:12:24 PM UTC 24 |
| Finished | Aug 27 03:58:49 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161030578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.161030578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.3397606391 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 81267147 ps |
| CPU time | 5.12 seconds |
| Started | Aug 27 03:12:24 PM UTC 24 |
| Finished | Aug 27 03:12:50 PM UTC 24 |
| Peak memory | 263136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397606391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3397606391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.2003271800 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 25820059552 ps |
| CPU time | 1420.3 seconds |
| Started | Aug 27 03:12:24 PM UTC 24 |
| Finished | Aug 27 03:36:30 PM UTC 24 |
| Peak memory | 288220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003271800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2003271800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.786808396 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 31262521322 ps |
| CPU time | 884.7 seconds |
| Started | Aug 27 03:12:24 PM UTC 24 |
| Finished | Aug 27 03:27:40 PM UTC 24 |
| Peak memory | 295824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786808396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.786808396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.3746912582 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6153308980 ps |
| CPU time | 73.04 seconds |
| Started | Aug 27 03:12:24 PM UTC 24 |
| Finished | Aug 27 03:13:48 PM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746912582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3746912582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.2889007860 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 13282265935 ps |
| CPU time | 56.52 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:13:50 PM UTC 24 |
| Peak memory | 269220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889007860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2889007860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.2906759467 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 850654167 ps |
| CPU time | 54.98 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:13:48 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906759467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2906759467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.2292409187 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 285449076 ps |
| CPU time | 7.95 seconds |
| Started | Aug 27 03:12:24 PM UTC 24 |
| Finished | Aug 27 03:12:50 PM UTC 24 |
| Peak memory | 267016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292409187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2292409187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.2898509192 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 990389319 ps |
| CPU time | 25.48 seconds |
| Started | Aug 27 03:12:21 PM UTC 24 |
| Finished | Aug 27 03:13:18 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898509192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2898509192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.1572870372 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 246596321633 ps |
| CPU time | 2790.7 seconds |
| Started | Aug 27 03:12:24 PM UTC 24 |
| Finished | Aug 27 03:59:54 PM UTC 24 |
| Peak memory | 314840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572870372 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.1572870372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all_with_rand_reset.3037374487 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8506894713 ps |
| CPU time | 315.59 seconds |
| Started | Aug 27 03:12:24 PM UTC 24 |
| Finished | Aug 27 03:18:12 PM UTC 24 |
| Peak memory | 279616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3037374487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.al ert_handler_stress_all_with_rand_reset.3037374487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.1553140762 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 21406731632 ps |
| CPU time | 997.71 seconds |
| Started | Aug 27 03:42:08 PM UTC 24 |
| Finished | Aug 27 03:58:57 PM UTC 24 |
| Peak memory | 285492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553140762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1553140762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/20.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.1932649468 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 718900756 ps |
| CPU time | 59.47 seconds |
| Started | Aug 27 03:41:40 PM UTC 24 |
| Finished | Aug 27 03:42:41 PM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932649468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1932649468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.1370803874 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1472478449 ps |
| CPU time | 44.4 seconds |
| Started | Aug 27 03:41:21 PM UTC 24 |
| Finished | Aug 27 03:42:07 PM UTC 24 |
| Peak memory | 269152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370803874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1370803874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.514838422 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 58243952120 ps |
| CPU time | 1748.6 seconds |
| Started | Aug 27 03:42:42 PM UTC 24 |
| Finished | Aug 27 04:12:11 PM UTC 24 |
| Peak memory | 285824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514838422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.514838422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/20.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.3445810308 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 25138987757 ps |
| CPU time | 1117.05 seconds |
| Started | Aug 27 03:42:49 PM UTC 24 |
| Finished | Aug 27 04:01:39 PM UTC 24 |
| Peak memory | 302280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445810308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3445810308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.810784781 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 3464301126 ps |
| CPU time | 215.46 seconds |
| Started | Aug 27 03:42:24 PM UTC 24 |
| Finished | Aug 27 03:46:03 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810784781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.810784781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.3536321357 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1234370451 ps |
| CPU time | 40.65 seconds |
| Started | Aug 27 03:40:38 PM UTC 24 |
| Finished | Aug 27 03:41:20 PM UTC 24 |
| Peak memory | 269468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536321357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3536321357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.1579310086 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 1603384729 ps |
| CPU time | 60.68 seconds |
| Started | Aug 27 03:41:21 PM UTC 24 |
| Finished | Aug 27 03:42:23 PM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579310086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1579310086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/20.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.1001178042 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2451451562 ps |
| CPU time | 62.13 seconds |
| Started | Aug 27 03:40:36 PM UTC 24 |
| Finished | Aug 27 03:41:39 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001178042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1001178042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/20.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.2135698944 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 22504689480 ps |
| CPU time | 506.86 seconds |
| Started | Aug 27 03:43:32 PM UTC 24 |
| Finished | Aug 27 03:52:06 PM UTC 24 |
| Peak memory | 283652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2135698944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.a lert_handler_stress_all_with_rand_reset.2135698944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.2917307539 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 724273870 ps |
| CPU time | 71.54 seconds |
| Started | Aug 27 03:44:20 PM UTC 24 |
| Finished | Aug 27 03:45:34 PM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917307539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2917307539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.63009925 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 943576249 ps |
| CPU time | 23.77 seconds |
| Started | Aug 27 03:44:15 PM UTC 24 |
| Finished | Aug 27 03:44:40 PM UTC 24 |
| Peak memory | 267324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63009925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc _intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.63009925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.1529690881 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 38323395561 ps |
| CPU time | 2025.77 seconds |
| Started | Aug 27 03:45:03 PM UTC 24 |
| Finished | Aug 27 04:19:11 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529690881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1529690881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/21.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.971756711 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 55413950738 ps |
| CPU time | 3184.44 seconds |
| Started | Aug 27 03:45:35 PM UTC 24 |
| Finished | Aug 27 04:39:13 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971756711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.971756711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.1431448984 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 114070259227 ps |
| CPU time | 348.75 seconds |
| Started | Aug 27 03:45:02 PM UTC 24 |
| Finished | Aug 27 03:50:56 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431448984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1431448984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.4109033962 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 298911703 ps |
| CPU time | 34.29 seconds |
| Started | Aug 27 03:43:39 PM UTC 24 |
| Finished | Aug 27 03:44:15 PM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109033962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.4109033962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.2918436992 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 333542933 ps |
| CPU time | 18.72 seconds |
| Started | Aug 27 03:44:00 PM UTC 24 |
| Finished | Aug 27 03:44:20 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918436992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2918436992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/21.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.1457186791 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1642986916 ps |
| CPU time | 23.91 seconds |
| Started | Aug 27 03:44:36 PM UTC 24 |
| Finished | Aug 27 03:45:01 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457186791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1457186791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.2495752024 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 8849905749 ps |
| CPU time | 85.55 seconds |
| Started | Aug 27 03:43:34 PM UTC 24 |
| Finished | Aug 27 03:45:02 PM UTC 24 |
| Peak memory | 269320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495752024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2495752024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/21.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.3906056887 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 83876657125 ps |
| CPU time | 1884.53 seconds |
| Started | Aug 27 03:46:04 PM UTC 24 |
| Finished | Aug 27 04:17:50 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906056887 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.3906056887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/21.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.2764339495 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 120073274310 ps |
| CPU time | 1746.87 seconds |
| Started | Aug 27 03:47:04 PM UTC 24 |
| Finished | Aug 27 04:16:32 PM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764339495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2764339495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/22.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.3675399151 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 10452418451 ps |
| CPU time | 214.24 seconds |
| Started | Aug 27 03:46:47 PM UTC 24 |
| Finished | Aug 27 03:50:25 PM UTC 24 |
| Peak memory | 269500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675399151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3675399151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.1621706380 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 192164766 ps |
| CPU time | 19.26 seconds |
| Started | Aug 27 03:46:46 PM UTC 24 |
| Finished | Aug 27 03:47:07 PM UTC 24 |
| Peak memory | 263240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621706380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1621706380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.3967302719 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 33393254410 ps |
| CPU time | 1362.43 seconds |
| Started | Aug 27 03:47:15 PM UTC 24 |
| Finished | Aug 27 04:10:13 PM UTC 24 |
| Peak memory | 301956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967302719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3967302719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/22.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.1151030566 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 45357683784 ps |
| CPU time | 1152.76 seconds |
| Started | Aug 27 03:47:26 PM UTC 24 |
| Finished | Aug 27 04:06:52 PM UTC 24 |
| Peak memory | 301888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151030566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1151030566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.396930838 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 17948117390 ps |
| CPU time | 270.97 seconds |
| Started | Aug 27 03:47:07 PM UTC 24 |
| Finished | Aug 27 03:51:42 PM UTC 24 |
| Peak memory | 263108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396930838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.396930838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.2070746346 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 412406861 ps |
| CPU time | 53.45 seconds |
| Started | Aug 27 03:46:32 PM UTC 24 |
| Finished | Aug 27 03:47:27 PM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070746346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2070746346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.1927806726 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1143994082 ps |
| CPU time | 37.61 seconds |
| Started | Aug 27 03:46:46 PM UTC 24 |
| Finished | Aug 27 03:47:25 PM UTC 24 |
| Peak memory | 269096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927806726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1927806726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/22.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.3551243165 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 168476771 ps |
| CPU time | 9.77 seconds |
| Started | Aug 27 03:47:04 PM UTC 24 |
| Finished | Aug 27 03:47:15 PM UTC 24 |
| Peak memory | 267068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551243165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3551243165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.2193826838 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1249356952 ps |
| CPU time | 40.46 seconds |
| Started | Aug 27 03:46:22 PM UTC 24 |
| Finished | Aug 27 03:47:04 PM UTC 24 |
| Peak memory | 269056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193826838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2193826838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/22.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.663577591 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 6920942630 ps |
| CPU time | 135.04 seconds |
| Started | Aug 27 03:47:28 PM UTC 24 |
| Finished | Aug 27 03:49:45 PM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663577591 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.663577591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/22.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all_with_rand_reset.2010470904 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 10660983927 ps |
| CPU time | 173.4 seconds |
| Started | Aug 27 03:48:54 PM UTC 24 |
| Finished | Aug 27 03:51:51 PM UTC 24 |
| Peak memory | 279480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2010470904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.a lert_handler_stress_all_with_rand_reset.2010470904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.2703070776 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 66267149382 ps |
| CPU time | 1877.94 seconds |
| Started | Aug 27 03:50:27 PM UTC 24 |
| Finished | Aug 27 04:22:06 PM UTC 24 |
| Peak memory | 304676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703070776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2703070776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/23.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.828091218 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 382921447 ps |
| CPU time | 42.94 seconds |
| Started | Aug 27 03:50:16 PM UTC 24 |
| Finished | Aug 27 03:51:01 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828091218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.828091218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.900870567 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 787609323 ps |
| CPU time | 18.49 seconds |
| Started | Aug 27 03:49:57 PM UTC 24 |
| Finished | Aug 27 03:50:17 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900870567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.900870567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.116005769 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 99247367142 ps |
| CPU time | 1098.5 seconds |
| Started | Aug 27 03:50:33 PM UTC 24 |
| Finished | Aug 27 04:09:04 PM UTC 24 |
| Peak memory | 279348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116005769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.116005769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/23.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.2464327392 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 27095334620 ps |
| CPU time | 1736.19 seconds |
| Started | Aug 27 03:50:40 PM UTC 24 |
| Finished | Aug 27 04:19:57 PM UTC 24 |
| Peak memory | 286976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464327392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2464327392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.133822280 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 136550616 ps |
| CPU time | 12.47 seconds |
| Started | Aug 27 03:49:43 PM UTC 24 |
| Finished | Aug 27 03:49:57 PM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133822280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.133822280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.4164511836 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 1437203350 ps |
| CPU time | 43.5 seconds |
| Started | Aug 27 03:49:46 PM UTC 24 |
| Finished | Aug 27 03:50:31 PM UTC 24 |
| Peak memory | 263324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164511836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.4164511836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/23.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.710546773 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 529235708 ps |
| CPU time | 13.66 seconds |
| Started | Aug 27 03:50:17 PM UTC 24 |
| Finished | Aug 27 03:50:32 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710546773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.710546773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.1387183912 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 4679067836 ps |
| CPU time | 99.28 seconds |
| Started | Aug 27 03:49:26 PM UTC 24 |
| Finished | Aug 27 03:51:07 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387183912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1387183912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/23.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.860475322 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 24973426537 ps |
| CPU time | 1204.82 seconds |
| Started | Aug 27 03:50:45 PM UTC 24 |
| Finished | Aug 27 04:11:04 PM UTC 24 |
| Peak memory | 301876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860475322 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.860475322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/23.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all_with_rand_reset.2298294287 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 6154564589 ps |
| CPU time | 341.74 seconds |
| Started | Aug 27 03:50:49 PM UTC 24 |
| Finished | Aug 27 03:56:35 PM UTC 24 |
| Peak memory | 279480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2298294287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.a lert_handler_stress_all_with_rand_reset.2298294287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.2101915813 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 28622065770 ps |
| CPU time | 1761.58 seconds |
| Started | Aug 27 03:51:34 PM UTC 24 |
| Finished | Aug 27 04:21:18 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101915813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2101915813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/24.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.2805784066 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 3402477583 ps |
| CPU time | 245.43 seconds |
| Started | Aug 27 03:51:19 PM UTC 24 |
| Finished | Aug 27 03:55:28 PM UTC 24 |
| Peak memory | 269432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805784066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2805784066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.1702119561 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 89761295 ps |
| CPU time | 14.35 seconds |
| Started | Aug 27 03:51:08 PM UTC 24 |
| Finished | Aug 27 03:51:24 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702119561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1702119561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.1786841480 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 134851096216 ps |
| CPU time | 1373.39 seconds |
| Started | Aug 27 03:51:40 PM UTC 24 |
| Finished | Aug 27 04:14:50 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786841480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1786841480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/24.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.2684110075 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 24116213946 ps |
| CPU time | 1540.38 seconds |
| Started | Aug 27 03:51:43 PM UTC 24 |
| Finished | Aug 27 04:17:41 PM UTC 24 |
| Peak memory | 279432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684110075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2684110075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.2766561470 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 16882230431 ps |
| CPU time | 690.57 seconds |
| Started | Aug 27 03:51:40 PM UTC 24 |
| Finished | Aug 27 04:03:19 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766561470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2766561470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.169117529 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2444806368 ps |
| CPU time | 51.69 seconds |
| Started | Aug 27 03:50:57 PM UTC 24 |
| Finished | Aug 27 03:51:50 PM UTC 24 |
| Peak memory | 269476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169117529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.169117529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.2408943711 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 319629626 ps |
| CPU time | 34.25 seconds |
| Started | Aug 27 03:51:01 PM UTC 24 |
| Finished | Aug 27 03:51:37 PM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408943711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2408943711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/24.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.2407790212 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 126593209 ps |
| CPU time | 6.97 seconds |
| Started | Aug 27 03:51:25 PM UTC 24 |
| Finished | Aug 27 03:51:33 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407790212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2407790212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.2490301016 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 3115577625 ps |
| CPU time | 61.12 seconds |
| Started | Aug 27 03:50:49 PM UTC 24 |
| Finished | Aug 27 03:51:52 PM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490301016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2490301016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/24.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all_with_rand_reset.2064147352 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1258673562 ps |
| CPU time | 135.84 seconds |
| Started | Aug 27 03:51:51 PM UTC 24 |
| Finished | Aug 27 03:54:10 PM UTC 24 |
| Peak memory | 279428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2064147352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.a lert_handler_stress_all_with_rand_reset.2064147352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.711874458 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 128189493262 ps |
| CPU time | 1814.75 seconds |
| Started | Aug 27 03:52:14 PM UTC 24 |
| Finished | Aug 27 04:22:50 PM UTC 24 |
| Peak memory | 297792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711874458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.711874458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/25.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.1497664078 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 10083164129 ps |
| CPU time | 349.52 seconds |
| Started | Aug 27 03:52:07 PM UTC 24 |
| Finished | Aug 27 03:58:02 PM UTC 24 |
| Peak memory | 269176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497664078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1497664078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.567071899 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 158374841 ps |
| CPU time | 25.1 seconds |
| Started | Aug 27 03:52:07 PM UTC 24 |
| Finished | Aug 27 03:52:33 PM UTC 24 |
| Peak memory | 269248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567071899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.567071899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.3540636018 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 16610870096 ps |
| CPU time | 754.74 seconds |
| Started | Aug 27 03:52:35 PM UTC 24 |
| Finished | Aug 27 04:05:19 PM UTC 24 |
| Peak memory | 285828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540636018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3540636018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/25.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.554743563 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 33120713861 ps |
| CPU time | 869.05 seconds |
| Started | Aug 27 03:52:38 PM UTC 24 |
| Finished | Aug 27 04:07:18 PM UTC 24 |
| Peak memory | 285828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554743563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.554743563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.3241480133 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 14719399832 ps |
| CPU time | 369.62 seconds |
| Started | Aug 27 03:52:20 PM UTC 24 |
| Finished | Aug 27 03:58:34 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241480133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3241480133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.3920204831 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 103012218 ps |
| CPU time | 19.07 seconds |
| Started | Aug 27 03:51:58 PM UTC 24 |
| Finished | Aug 27 03:52:18 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920204831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3920204831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.1580638510 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 300797566 ps |
| CPU time | 10.66 seconds |
| Started | Aug 27 03:51:59 PM UTC 24 |
| Finished | Aug 27 03:52:11 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580638510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1580638510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/25.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.1214607581 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 200241087 ps |
| CPU time | 30.29 seconds |
| Started | Aug 27 03:52:12 PM UTC 24 |
| Finished | Aug 27 03:52:44 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214607581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1214607581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.3566068122 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 203881036 ps |
| CPU time | 4.37 seconds |
| Started | Aug 27 03:51:53 PM UTC 24 |
| Finished | Aug 27 03:51:58 PM UTC 24 |
| Peak memory | 263240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566068122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3566068122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/25.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.4158337609 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 24838303820 ps |
| CPU time | 1158.36 seconds |
| Started | Aug 27 03:52:44 PM UTC 24 |
| Finished | Aug 27 04:12:16 PM UTC 24 |
| Peak memory | 301880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158337609 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.4158337609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/25.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all_with_rand_reset.3957716053 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 13916812551 ps |
| CPU time | 385.11 seconds |
| Started | Aug 27 03:53:04 PM UTC 24 |
| Finished | Aug 27 03:59:34 PM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3957716053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.a lert_handler_stress_all_with_rand_reset.3957716053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/25.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.1826544190 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 29097896001 ps |
| CPU time | 2011.42 seconds |
| Started | Aug 27 03:54:45 PM UTC 24 |
| Finished | Aug 27 04:28:39 PM UTC 24 |
| Peak memory | 288224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826544190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1826544190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/26.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.4013692823 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1763005377 ps |
| CPU time | 131.87 seconds |
| Started | Aug 27 03:54:36 PM UTC 24 |
| Finished | Aug 27 03:56:50 PM UTC 24 |
| Peak memory | 269368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013692823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.4013692823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.3697787337 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1359663086 ps |
| CPU time | 39.55 seconds |
| Started | Aug 27 03:54:10 PM UTC 24 |
| Finished | Aug 27 03:54:52 PM UTC 24 |
| Peak memory | 263264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697787337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3697787337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.132937653 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 42861106177 ps |
| CPU time | 1347.32 seconds |
| Started | Aug 27 03:54:46 PM UTC 24 |
| Finished | Aug 27 04:17:28 PM UTC 24 |
| Peak memory | 299824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132937653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.132937653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/26.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.3235522877 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 43781887816 ps |
| CPU time | 1051.69 seconds |
| Started | Aug 27 03:54:53 PM UTC 24 |
| Finished | Aug 27 04:12:36 PM UTC 24 |
| Peak memory | 285504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235522877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3235522877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.3187397789 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 11186389460 ps |
| CPU time | 369.99 seconds |
| Started | Aug 27 03:54:45 PM UTC 24 |
| Finished | Aug 27 04:00:59 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187397789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3187397789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.2251414264 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 204358861 ps |
| CPU time | 12.95 seconds |
| Started | Aug 27 03:53:50 PM UTC 24 |
| Finished | Aug 27 03:54:04 PM UTC 24 |
| Peak memory | 269340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251414264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2251414264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.3846424268 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 567246368 ps |
| CPU time | 38.21 seconds |
| Started | Aug 27 03:54:05 PM UTC 24 |
| Finished | Aug 27 03:54:45 PM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846424268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3846424268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/26.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.2900025914 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 623020920 ps |
| CPU time | 59.02 seconds |
| Started | Aug 27 03:54:40 PM UTC 24 |
| Finished | Aug 27 03:55:41 PM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900025914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2900025914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.2536654811 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2862914954 ps |
| CPU time | 47.56 seconds |
| Started | Aug 27 03:53:50 PM UTC 24 |
| Finished | Aug 27 03:54:39 PM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536654811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2536654811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/26.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.3353900256 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 29756980422 ps |
| CPU time | 400.55 seconds |
| Started | Aug 27 03:55:29 PM UTC 24 |
| Finished | Aug 27 04:02:15 PM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353900256 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.3353900256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/26.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all_with_rand_reset.2982359786 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3414770313 ps |
| CPU time | 422.94 seconds |
| Started | Aug 27 03:55:41 PM UTC 24 |
| Finished | Aug 27 04:02:50 PM UTC 24 |
| Peak memory | 283652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2982359786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.a lert_handler_stress_all_with_rand_reset.2982359786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.3987150268 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 92794853145 ps |
| CPU time | 1357.61 seconds |
| Started | Aug 27 03:57:20 PM UTC 24 |
| Finished | Aug 27 04:20:13 PM UTC 24 |
| Peak memory | 285568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987150268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3987150268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/27.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.3027487800 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 3982371286 ps |
| CPU time | 108.18 seconds |
| Started | Aug 27 03:56:47 PM UTC 24 |
| Finished | Aug 27 03:58:38 PM UTC 24 |
| Peak memory | 269432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027487800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3027487800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.2884785493 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 395838895 ps |
| CPU time | 50.6 seconds |
| Started | Aug 27 03:56:37 PM UTC 24 |
| Finished | Aug 27 03:57:29 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884785493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2884785493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.936916581 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 12178743984 ps |
| CPU time | 1325.82 seconds |
| Started | Aug 27 03:57:38 PM UTC 24 |
| Finished | Aug 27 04:20:00 PM UTC 24 |
| Peak memory | 298108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936916581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.936916581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/27.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.645452120 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 63954336612 ps |
| CPU time | 1103.21 seconds |
| Started | Aug 27 03:57:50 PM UTC 24 |
| Finished | Aug 27 04:16:26 PM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645452120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.645452120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.2913370053 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 3600289449 ps |
| CPU time | 203.24 seconds |
| Started | Aug 27 03:57:31 PM UTC 24 |
| Finished | Aug 27 04:00:58 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913370053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2913370053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.2926076451 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 3578976578 ps |
| CPU time | 79.69 seconds |
| Started | Aug 27 03:56:28 PM UTC 24 |
| Finished | Aug 27 03:57:49 PM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926076451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2926076451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.2549708315 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 295749319 ps |
| CPU time | 40.73 seconds |
| Started | Aug 27 03:56:36 PM UTC 24 |
| Finished | Aug 27 03:57:18 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549708315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2549708315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/27.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.1507243617 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 937936650 ps |
| CPU time | 43.74 seconds |
| Started | Aug 27 03:56:51 PM UTC 24 |
| Finished | Aug 27 03:57:37 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507243617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1507243617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.1465780403 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 481457024 ps |
| CPU time | 20.59 seconds |
| Started | Aug 27 03:56:15 PM UTC 24 |
| Finished | Aug 27 03:56:37 PM UTC 24 |
| Peak memory | 262912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465780403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1465780403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/27.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.156875251 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 9669591387 ps |
| CPU time | 278.59 seconds |
| Started | Aug 27 03:58:02 PM UTC 24 |
| Finished | Aug 27 04:02:45 PM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156875251 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.156875251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/27.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.3322795903 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 20736146902 ps |
| CPU time | 952.34 seconds |
| Started | Aug 27 03:59:36 PM UTC 24 |
| Finished | Aug 27 04:15:40 PM UTC 24 |
| Peak memory | 301952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322795903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3322795903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/28.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.1317043824 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 14930458448 ps |
| CPU time | 209.37 seconds |
| Started | Aug 27 03:59:02 PM UTC 24 |
| Finished | Aug 27 04:02:34 PM UTC 24 |
| Peak memory | 265080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317043824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1317043824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.2700925397 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 925347484 ps |
| CPU time | 44.06 seconds |
| Started | Aug 27 03:59:00 PM UTC 24 |
| Finished | Aug 27 03:59:45 PM UTC 24 |
| Peak memory | 263264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700925397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2700925397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.1999198733 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 61652595525 ps |
| CPU time | 1322.41 seconds |
| Started | Aug 27 03:59:46 PM UTC 24 |
| Finished | Aug 27 04:22:04 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999198733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1999198733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/28.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.675290107 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 13466775163 ps |
| CPU time | 1497.95 seconds |
| Started | Aug 27 03:59:56 PM UTC 24 |
| Finished | Aug 27 04:25:12 PM UTC 24 |
| Peak memory | 301956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675290107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.675290107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.3229755301 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 9221504335 ps |
| CPU time | 351.86 seconds |
| Started | Aug 27 03:59:38 PM UTC 24 |
| Finished | Aug 27 04:05:34 PM UTC 24 |
| Peak memory | 269448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229755301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3229755301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.3637701501 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 372016749 ps |
| CPU time | 21.56 seconds |
| Started | Aug 27 03:58:39 PM UTC 24 |
| Finished | Aug 27 03:59:01 PM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637701501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3637701501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.3622904823 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 311274342 ps |
| CPU time | 44.3 seconds |
| Started | Aug 27 03:58:51 PM UTC 24 |
| Finished | Aug 27 03:59:37 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622904823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3622904823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/28.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.3944628741 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1748086135 ps |
| CPU time | 54.87 seconds |
| Started | Aug 27 03:59:20 PM UTC 24 |
| Finished | Aug 27 04:00:17 PM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944628741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3944628741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.1071620852 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 755219525 ps |
| CPU time | 42.39 seconds |
| Started | Aug 27 03:58:35 PM UTC 24 |
| Finished | Aug 27 03:59:19 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071620852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1071620852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/28.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.3118561024 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 13631093769 ps |
| CPU time | 701.01 seconds |
| Started | Aug 27 04:00:08 PM UTC 24 |
| Finished | Aug 27 04:11:58 PM UTC 24 |
| Peak memory | 281472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118561024 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.3118561024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/28.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all_with_rand_reset.3567371081 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 24126296864 ps |
| CPU time | 659.55 seconds |
| Started | Aug 27 04:00:14 PM UTC 24 |
| Finished | Aug 27 04:11:22 PM UTC 24 |
| Peak memory | 285700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3567371081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.a lert_handler_stress_all_with_rand_reset.3567371081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.3633367203 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 71747137111 ps |
| CPU time | 2539.67 seconds |
| Started | Aug 27 04:01:17 PM UTC 24 |
| Finished | Aug 27 04:44:07 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633367203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3633367203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/29.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.2065536300 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 4510157967 ps |
| CPU time | 197.73 seconds |
| Started | Aug 27 04:00:59 PM UTC 24 |
| Finished | Aug 27 04:04:20 PM UTC 24 |
| Peak memory | 265084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065536300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2065536300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.2037598287 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 697788756 ps |
| CPU time | 63.6 seconds |
| Started | Aug 27 04:00:59 PM UTC 24 |
| Finished | Aug 27 04:02:05 PM UTC 24 |
| Peak memory | 269080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037598287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2037598287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.2082195177 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 39672538639 ps |
| CPU time | 2309.04 seconds |
| Started | Aug 27 04:01:38 PM UTC 24 |
| Finished | Aug 27 04:40:32 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082195177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2082195177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/29.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.2293608877 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 11150223456 ps |
| CPU time | 1090.62 seconds |
| Started | Aug 27 04:01:41 PM UTC 24 |
| Finished | Aug 27 04:20:05 PM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293608877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2293608877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.40721982 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 27588899860 ps |
| CPU time | 503.4 seconds |
| Started | Aug 27 04:01:17 PM UTC 24 |
| Finished | Aug 27 04:09:47 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40721982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.40721982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.1303256623 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 7367834269 ps |
| CPU time | 57.65 seconds |
| Started | Aug 27 04:00:38 PM UTC 24 |
| Finished | Aug 27 04:01:37 PM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303256623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1303256623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.3954243749 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 376813845 ps |
| CPU time | 18.56 seconds |
| Started | Aug 27 04:00:57 PM UTC 24 |
| Finished | Aug 27 04:01:17 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954243749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3954243749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/29.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.3849897593 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2870668134 ps |
| CPU time | 43.26 seconds |
| Started | Aug 27 04:01:00 PM UTC 24 |
| Finished | Aug 27 04:01:44 PM UTC 24 |
| Peak memory | 263292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849897593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3849897593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.927245391 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1120247419 ps |
| CPU time | 36.8 seconds |
| Started | Aug 27 04:00:17 PM UTC 24 |
| Finished | Aug 27 04:00:56 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927245391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.927245391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/29.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.4036775355 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 22459206271 ps |
| CPU time | 321 seconds |
| Started | Aug 27 04:01:44 PM UTC 24 |
| Finished | Aug 27 04:07:09 PM UTC 24 |
| Peak memory | 269440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036775355 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.4036775355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/29.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.51562962 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 62570702 ps |
| CPU time | 3.44 seconds |
| Started | Aug 27 03:12:36 PM UTC 24 |
| Finished | Aug 27 03:12:43 PM UTC 24 |
| Peak memory | 263244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51562962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h andler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.51562962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.2487186238 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 5362627187 ps |
| CPU time | 644.74 seconds |
| Started | Aug 27 03:12:29 PM UTC 24 |
| Finished | Aug 27 03:23:23 PM UTC 24 |
| Peak memory | 285820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487186238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2487186238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.4017787228 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1134704797 ps |
| CPU time | 6.68 seconds |
| Started | Aug 27 03:12:32 PM UTC 24 |
| Finished | Aug 27 03:12:46 PM UTC 24 |
| Peak memory | 263236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017787228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.4017787228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.2213902231 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2009268425 ps |
| CPU time | 110.89 seconds |
| Started | Aug 27 03:12:28 PM UTC 24 |
| Finished | Aug 27 03:14:27 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213902231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2213902231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.2448144717 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 25870269860 ps |
| CPU time | 675.9 seconds |
| Started | Aug 27 03:12:30 PM UTC 24 |
| Finished | Aug 27 03:23:56 PM UTC 24 |
| Peak memory | 283092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448144717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2448144717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.3741277723 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 28755845609 ps |
| CPU time | 1605.38 seconds |
| Started | Aug 27 03:12:30 PM UTC 24 |
| Finished | Aug 27 03:39:33 PM UTC 24 |
| Peak memory | 298200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741277723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3741277723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.971344393 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4881800645 ps |
| CPU time | 138.44 seconds |
| Started | Aug 27 03:12:29 PM UTC 24 |
| Finished | Aug 27 03:14:51 PM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971344393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.971344393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.1387788587 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1200818338 ps |
| CPU time | 39.71 seconds |
| Started | Aug 27 03:12:38 PM UTC 24 |
| Finished | Aug 27 03:13:21 PM UTC 24 |
| Peak memory | 297316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387788587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1387788587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.3494975724 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 192076001 ps |
| CPU time | 4.99 seconds |
| Started | Aug 27 03:12:25 PM UTC 24 |
| Finished | Aug 27 03:13:01 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494975724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3494975724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.419321489 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 39355355605 ps |
| CPU time | 2240.64 seconds |
| Started | Aug 27 03:12:33 PM UTC 24 |
| Finished | Aug 27 03:50:39 PM UTC 24 |
| Peak memory | 298456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419321489 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.419321489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/3.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.3603595304 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 75173946827 ps |
| CPU time | 2341.37 seconds |
| Started | Aug 27 04:02:58 PM UTC 24 |
| Finished | Aug 27 04:42:26 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603595304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3603595304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/30.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.136177053 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 16879891403 ps |
| CPU time | 258.49 seconds |
| Started | Aug 27 04:02:46 PM UTC 24 |
| Finished | Aug 27 04:07:08 PM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136177053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.136177053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.1325487041 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2188146332 ps |
| CPU time | 44.9 seconds |
| Started | Aug 27 04:02:36 PM UTC 24 |
| Finished | Aug 27 04:03:22 PM UTC 24 |
| Peak memory | 263072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325487041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1325487041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.2253620299 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 97814533359 ps |
| CPU time | 1343.85 seconds |
| Started | Aug 27 04:03:20 PM UTC 24 |
| Finished | Aug 27 04:26:00 PM UTC 24 |
| Peak memory | 301888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253620299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2253620299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.1459456781 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 129032924617 ps |
| CPU time | 469.78 seconds |
| Started | Aug 27 04:03:02 PM UTC 24 |
| Finished | Aug 27 04:10:58 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459456781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1459456781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.1793966720 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 322757382 ps |
| CPU time | 44.55 seconds |
| Started | Aug 27 04:02:16 PM UTC 24 |
| Finished | Aug 27 04:03:04 PM UTC 24 |
| Peak memory | 263132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793966720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1793966720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.1983621246 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 166882658 ps |
| CPU time | 24.58 seconds |
| Started | Aug 27 04:02:31 PM UTC 24 |
| Finished | Aug 27 04:02:56 PM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983621246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1983621246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/30.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.623813166 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 478521805 ps |
| CPU time | 39.49 seconds |
| Started | Aug 27 04:02:51 PM UTC 24 |
| Finished | Aug 27 04:03:31 PM UTC 24 |
| Peak memory | 269408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623813166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.623813166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.1588381593 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 378141331 ps |
| CPU time | 22.78 seconds |
| Started | Aug 27 04:02:06 PM UTC 24 |
| Finished | Aug 27 04:02:30 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588381593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1588381593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/30.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.3204109293 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 655507876410 ps |
| CPU time | 2228.35 seconds |
| Started | Aug 27 04:04:58 PM UTC 24 |
| Finished | Aug 27 04:42:32 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204109293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3204109293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/31.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.223095200 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 17768439956 ps |
| CPU time | 267.11 seconds |
| Started | Aug 27 04:04:33 PM UTC 24 |
| Finished | Aug 27 04:09:04 PM UTC 24 |
| Peak memory | 269144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223095200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.223095200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.3105249004 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 209833810 ps |
| CPU time | 6.22 seconds |
| Started | Aug 27 04:04:24 PM UTC 24 |
| Finished | Aug 27 04:04:32 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105249004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3105249004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.357381293 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 75366954630 ps |
| CPU time | 1312.04 seconds |
| Started | Aug 27 04:05:20 PM UTC 24 |
| Finished | Aug 27 04:27:27 PM UTC 24 |
| Peak memory | 299824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357381293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.357381293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/31.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.954355881 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 9512393203 ps |
| CPU time | 1199.6 seconds |
| Started | Aug 27 04:05:31 PM UTC 24 |
| Finished | Aug 27 04:25:45 PM UTC 24 |
| Peak memory | 301888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954355881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.954355881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.234823416 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 22085226217 ps |
| CPU time | 249.23 seconds |
| Started | Aug 27 04:05:15 PM UTC 24 |
| Finished | Aug 27 04:09:28 PM UTC 24 |
| Peak memory | 269444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234823416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.234823416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.2180470381 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 569763780 ps |
| CPU time | 41.66 seconds |
| Started | Aug 27 04:04:14 PM UTC 24 |
| Finished | Aug 27 04:04:58 PM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180470381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2180470381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.4074287515 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 124474002 ps |
| CPU time | 19.7 seconds |
| Started | Aug 27 04:04:21 PM UTC 24 |
| Finished | Aug 27 04:04:42 PM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074287515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4074287515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/31.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.1184941494 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 215333930 ps |
| CPU time | 5.93 seconds |
| Started | Aug 27 04:04:06 PM UTC 24 |
| Finished | Aug 27 04:04:14 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184941494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1184941494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/31.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.2106741280 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 10512814225 ps |
| CPU time | 483.31 seconds |
| Started | Aug 27 04:05:36 PM UTC 24 |
| Finished | Aug 27 04:13:45 PM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106741280 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.2106741280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/31.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.401785966 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 14999920778 ps |
| CPU time | 1474.63 seconds |
| Started | Aug 27 04:07:11 PM UTC 24 |
| Finished | Aug 27 04:32:03 PM UTC 24 |
| Peak memory | 301960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401785966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.401785966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/32.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.2421711620 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 13409337273 ps |
| CPU time | 70.58 seconds |
| Started | Aug 27 04:07:08 PM UTC 24 |
| Finished | Aug 27 04:08:21 PM UTC 24 |
| Peak memory | 269176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421711620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2421711620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.810164414 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 753177927 ps |
| CPU time | 47.4 seconds |
| Started | Aug 27 04:06:55 PM UTC 24 |
| Finished | Aug 27 04:07:44 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810164414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.810164414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.3063039706 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 142179165816 ps |
| CPU time | 2716.52 seconds |
| Started | Aug 27 04:07:20 PM UTC 24 |
| Finished | Aug 27 04:53:07 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063039706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3063039706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/32.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.2249825603 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 190935474756 ps |
| CPU time | 1926.86 seconds |
| Started | Aug 27 04:07:45 PM UTC 24 |
| Finished | Aug 27 04:40:15 PM UTC 24 |
| Peak memory | 288224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249825603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2249825603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.3130853836 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 10676932886 ps |
| CPU time | 126.04 seconds |
| Started | Aug 27 04:07:14 PM UTC 24 |
| Finished | Aug 27 04:09:22 PM UTC 24 |
| Peak memory | 267072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130853836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3130853836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.3376840741 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 222013885 ps |
| CPU time | 12.81 seconds |
| Started | Aug 27 04:06:28 PM UTC 24 |
| Finished | Aug 27 04:06:42 PM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376840741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3376840741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.890678797 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1395512049 ps |
| CPU time | 23.54 seconds |
| Started | Aug 27 04:06:43 PM UTC 24 |
| Finished | Aug 27 04:07:08 PM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890678797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.890678797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/32.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.739232833 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 196608035 ps |
| CPU time | 33.25 seconds |
| Started | Aug 27 04:07:09 PM UTC 24 |
| Finished | Aug 27 04:07:44 PM UTC 24 |
| Peak memory | 269060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739232833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.739232833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.434710803 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 4266887941 ps |
| CPU time | 76.31 seconds |
| Started | Aug 27 04:05:55 PM UTC 24 |
| Finished | Aug 27 04:07:13 PM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434710803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.434710803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/32.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.3718104830 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 79379320128 ps |
| CPU time | 1095.3 seconds |
| Started | Aug 27 04:07:46 PM UTC 24 |
| Finished | Aug 27 04:26:15 PM UTC 24 |
| Peak memory | 283776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718104830 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.3718104830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/32.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/33.alert_handler_entropy.1278184885 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 63613811746 ps |
| CPU time | 1533.72 seconds |
| Started | Aug 27 04:09:11 PM UTC 24 |
| Finished | Aug 27 04:35:02 PM UTC 24 |
| Peak memory | 301956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278184885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1278184885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/33.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.1946697548 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 2607925431 ps |
| CPU time | 110.26 seconds |
| Started | Aug 27 04:09:06 PM UTC 24 |
| Finished | Aug 27 04:10:59 PM UTC 24 |
| Peak memory | 262960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946697548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1946697548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.1808191503 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 198902735 ps |
| CPU time | 27.35 seconds |
| Started | Aug 27 04:09:06 PM UTC 24 |
| Finished | Aug 27 04:09:35 PM UTC 24 |
| Peak memory | 269080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808191503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1808191503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.2367212185 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 13625328465 ps |
| CPU time | 1484.99 seconds |
| Started | Aug 27 04:09:18 PM UTC 24 |
| Finished | Aug 27 04:34:21 PM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367212185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2367212185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/33.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.3607173784 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 10521920460 ps |
| CPU time | 847.09 seconds |
| Started | Aug 27 04:09:23 PM UTC 24 |
| Finished | Aug 27 04:23:40 PM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607173784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3607173784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.1498782696 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5209744337 ps |
| CPU time | 237.93 seconds |
| Started | Aug 27 04:09:12 PM UTC 24 |
| Finished | Aug 27 04:13:14 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498782696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1498782696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.1145714581 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1302721224 ps |
| CPU time | 47.77 seconds |
| Started | Aug 27 04:08:28 PM UTC 24 |
| Finished | Aug 27 04:09:18 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145714581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1145714581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.1205909133 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1200289160 ps |
| CPU time | 31.21 seconds |
| Started | Aug 27 04:08:37 PM UTC 24 |
| Finished | Aug 27 04:09:10 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205909133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1205909133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/33.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.998821623 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 13298272880 ps |
| CPU time | 73.24 seconds |
| Started | Aug 27 04:09:09 PM UTC 24 |
| Finished | Aug 27 04:10:24 PM UTC 24 |
| Peak memory | 269280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998821623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.998821623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.721610933 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2071668791 ps |
| CPU time | 47.51 seconds |
| Started | Aug 27 04:08:22 PM UTC 24 |
| Finished | Aug 27 04:09:11 PM UTC 24 |
| Peak memory | 269244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721610933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.721610933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/33.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.2359403047 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 15745947722 ps |
| CPU time | 1321.87 seconds |
| Started | Aug 27 04:09:29 PM UTC 24 |
| Finished | Aug 27 04:31:47 PM UTC 24 |
| Peak memory | 301952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359403047 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.2359403047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/33.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.2526405158 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 22488827281 ps |
| CPU time | 1388.45 seconds |
| Started | Aug 27 04:11:00 PM UTC 24 |
| Finished | Aug 27 04:34:24 PM UTC 24 |
| Peak memory | 285568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526405158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2526405158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/34.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.3432974456 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 10995437171 ps |
| CPU time | 180.67 seconds |
| Started | Aug 27 04:10:44 PM UTC 24 |
| Finished | Aug 27 04:13:48 PM UTC 24 |
| Peak memory | 269100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432974456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3432974456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.1511071885 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1515515323 ps |
| CPU time | 49.76 seconds |
| Started | Aug 27 04:10:25 PM UTC 24 |
| Finished | Aug 27 04:11:16 PM UTC 24 |
| Peak memory | 269408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511071885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1511071885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.937285297 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 18998881975 ps |
| CPU time | 1199.6 seconds |
| Started | Aug 27 04:11:08 PM UTC 24 |
| Finished | Aug 27 04:31:22 PM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937285297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.937285297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.1331371346 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 23180061052 ps |
| CPU time | 255.32 seconds |
| Started | Aug 27 04:11:03 PM UTC 24 |
| Finished | Aug 27 04:15:22 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331371346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1331371346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.3570544154 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 803758389 ps |
| CPU time | 67.08 seconds |
| Started | Aug 27 04:09:57 PM UTC 24 |
| Finished | Aug 27 04:11:07 PM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570544154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3570544154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.3292043721 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1337731097 ps |
| CPU time | 55.28 seconds |
| Started | Aug 27 04:10:16 PM UTC 24 |
| Finished | Aug 27 04:11:12 PM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292043721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3292043721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/34.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.4203074250 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 346365278 ps |
| CPU time | 22.3 seconds |
| Started | Aug 27 04:10:59 PM UTC 24 |
| Finished | Aug 27 04:11:23 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203074250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.4203074250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.2895500050 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 582420998 ps |
| CPU time | 53.11 seconds |
| Started | Aug 27 04:09:48 PM UTC 24 |
| Finished | Aug 27 04:10:43 PM UTC 24 |
| Peak memory | 269384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895500050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2895500050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/34.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.1134142980 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 11480071483 ps |
| CPU time | 1189.56 seconds |
| Started | Aug 27 04:11:13 PM UTC 24 |
| Finished | Aug 27 04:31:17 PM UTC 24 |
| Peak memory | 299832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134142980 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.1134142980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/34.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.488300425 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 54197516606 ps |
| CPU time | 1471.45 seconds |
| Started | Aug 27 04:12:08 PM UTC 24 |
| Finished | Aug 27 04:36:58 PM UTC 24 |
| Peak memory | 296072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488300425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.488300425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/35.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.4128783776 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2338619009 ps |
| CPU time | 140.48 seconds |
| Started | Aug 27 04:11:59 PM UTC 24 |
| Finished | Aug 27 04:14:22 PM UTC 24 |
| Peak memory | 269104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128783776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.4128783776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.2354152047 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 928719775 ps |
| CPU time | 45.57 seconds |
| Started | Aug 27 04:11:45 PM UTC 24 |
| Finished | Aug 27 04:12:32 PM UTC 24 |
| Peak memory | 269088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354152047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2354152047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.3192055052 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 371203049908 ps |
| CPU time | 1494.19 seconds |
| Started | Aug 27 04:12:19 PM UTC 24 |
| Finished | Aug 27 04:37:30 PM UTC 24 |
| Peak memory | 285580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192055052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3192055052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.3055228035 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 22367333785 ps |
| CPU time | 335.22 seconds |
| Started | Aug 27 04:12:12 PM UTC 24 |
| Finished | Aug 27 04:17:52 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055228035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3055228035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.2335915342 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 1210239177 ps |
| CPU time | 38.52 seconds |
| Started | Aug 27 04:11:23 PM UTC 24 |
| Finished | Aug 27 04:12:03 PM UTC 24 |
| Peak memory | 268584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335915342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2335915342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.2819508731 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 2406475395 ps |
| CPU time | 62.05 seconds |
| Started | Aug 27 04:11:23 PM UTC 24 |
| Finished | Aug 27 04:12:27 PM UTC 24 |
| Peak memory | 262568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819508731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2819508731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/35.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.479129007 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 2130962216 ps |
| CPU time | 52.08 seconds |
| Started | Aug 27 04:12:04 PM UTC 24 |
| Finished | Aug 27 04:12:58 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479129007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.479129007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.3831050017 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 332520099 ps |
| CPU time | 49.17 seconds |
| Started | Aug 27 04:11:20 PM UTC 24 |
| Finished | Aug 27 04:12:11 PM UTC 24 |
| Peak memory | 269056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831050017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3831050017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/35.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all_with_rand_reset.3177249807 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 5071301246 ps |
| CPU time | 303.56 seconds |
| Started | Aug 27 04:12:24 PM UTC 24 |
| Finished | Aug 27 04:17:32 PM UTC 24 |
| Peak memory | 281528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3177249807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.a lert_handler_stress_all_with_rand_reset.3177249807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.117321811 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 8963737921 ps |
| CPU time | 762.93 seconds |
| Started | Aug 27 04:13:14 PM UTC 24 |
| Finished | Aug 27 04:26:07 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117321811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.117321811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/36.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.4165065292 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 871977779 ps |
| CPU time | 74.18 seconds |
| Started | Aug 27 04:13:02 PM UTC 24 |
| Finished | Aug 27 04:14:18 PM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165065292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.4165065292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.2623614079 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 760786961 ps |
| CPU time | 30.83 seconds |
| Started | Aug 27 04:12:59 PM UTC 24 |
| Finished | Aug 27 04:13:32 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623614079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2623614079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg.1274713875 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 43505832887 ps |
| CPU time | 2683.26 seconds |
| Started | Aug 27 04:13:25 PM UTC 24 |
| Finished | Aug 27 04:58:39 PM UTC 24 |
| Peak memory | 300512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274713875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1274713875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/36.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.3876018279 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 64939038729 ps |
| CPU time | 1579.47 seconds |
| Started | Aug 27 04:13:33 PM UTC 24 |
| Finished | Aug 27 04:40:10 PM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876018279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3876018279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.4046108764 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 11779685362 ps |
| CPU time | 577.16 seconds |
| Started | Aug 27 04:13:23 PM UTC 24 |
| Finished | Aug 27 04:23:07 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046108764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.4046108764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.1137190852 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 500652798 ps |
| CPU time | 49.08 seconds |
| Started | Aug 27 04:12:33 PM UTC 24 |
| Finished | Aug 27 04:13:24 PM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137190852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1137190852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.1999267568 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1564265942 ps |
| CPU time | 26.82 seconds |
| Started | Aug 27 04:12:39 PM UTC 24 |
| Finished | Aug 27 04:13:07 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999267568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1999267568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/36.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.2841347210 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 90998804 ps |
| CPU time | 12.55 seconds |
| Started | Aug 27 04:13:08 PM UTC 24 |
| Finished | Aug 27 04:13:22 PM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841347210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2841347210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.4275854576 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 374527823 ps |
| CPU time | 31.36 seconds |
| Started | Aug 27 04:12:28 PM UTC 24 |
| Finished | Aug 27 04:13:01 PM UTC 24 |
| Peak memory | 269384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275854576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.4275854576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/36.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.3618615241 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 10321403179 ps |
| CPU time | 1121.83 seconds |
| Started | Aug 27 04:13:46 PM UTC 24 |
| Finished | Aug 27 04:32:42 PM UTC 24 |
| Peak memory | 285568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618615241 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.3618615241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/36.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.3517690495 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 13714379075 ps |
| CPU time | 1150.39 seconds |
| Started | Aug 27 04:14:52 PM UTC 24 |
| Finished | Aug 27 04:34:15 PM UTC 24 |
| Peak memory | 302024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517690495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3517690495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/37.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.3967589298 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 250352700 ps |
| CPU time | 19.65 seconds |
| Started | Aug 27 04:14:39 PM UTC 24 |
| Finished | Aug 27 04:15:00 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967589298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3967589298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.2834068649 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 771880455 ps |
| CPU time | 14.14 seconds |
| Started | Aug 27 04:14:30 PM UTC 24 |
| Finished | Aug 27 04:14:45 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834068649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2834068649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.2729923354 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 28005138790 ps |
| CPU time | 1823.75 seconds |
| Started | Aug 27 04:15:03 PM UTC 24 |
| Finished | Aug 27 04:45:47 PM UTC 24 |
| Peak memory | 298472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729923354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2729923354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/37.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.1547801174 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 163813066825 ps |
| CPU time | 2100.87 seconds |
| Started | Aug 27 04:15:15 PM UTC 24 |
| Finished | Aug 27 04:50:39 PM UTC 24 |
| Peak memory | 288300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547801174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1547801174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.816055887 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 4200515412 ps |
| CPU time | 156.44 seconds |
| Started | Aug 27 04:15:01 PM UTC 24 |
| Finished | Aug 27 04:17:40 PM UTC 24 |
| Peak memory | 263040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816055887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.816055887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.4027184054 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 399279993 ps |
| CPU time | 53.16 seconds |
| Started | Aug 27 04:14:19 PM UTC 24 |
| Finished | Aug 27 04:15:14 PM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027184054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.4027184054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.2231100003 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 327232883 ps |
| CPU time | 12.8 seconds |
| Started | Aug 27 04:14:24 PM UTC 24 |
| Finished | Aug 27 04:14:38 PM UTC 24 |
| Peak memory | 269340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231100003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2231100003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/37.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.2519063872 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 836488063 ps |
| CPU time | 14.27 seconds |
| Started | Aug 27 04:14:46 PM UTC 24 |
| Finished | Aug 27 04:15:02 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519063872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2519063872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.4164294861 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 986846914 ps |
| CPU time | 29.77 seconds |
| Started | Aug 27 04:13:58 PM UTC 24 |
| Finished | Aug 27 04:14:29 PM UTC 24 |
| Peak memory | 269056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164294861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.4164294861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/37.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.297058857 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 274278259 ps |
| CPU time | 6.32 seconds |
| Started | Aug 27 04:15:20 PM UTC 24 |
| Finished | Aug 27 04:15:28 PM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297058857 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.297058857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/37.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all_with_rand_reset.3247852351 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 10703361499 ps |
| CPU time | 319.27 seconds |
| Started | Aug 27 04:15:23 PM UTC 24 |
| Finished | Aug 27 04:20:48 PM UTC 24 |
| Peak memory | 279584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3247852351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.a lert_handler_stress_all_with_rand_reset.3247852351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.3694900922 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 8454340594 ps |
| CPU time | 652.38 seconds |
| Started | Aug 27 04:16:34 PM UTC 24 |
| Finished | Aug 27 04:27:35 PM UTC 24 |
| Peak memory | 285492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694900922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3694900922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/38.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.3780887256 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 102136074 ps |
| CPU time | 5.76 seconds |
| Started | Aug 27 04:16:29 PM UTC 24 |
| Finished | Aug 27 04:16:36 PM UTC 24 |
| Peak memory | 264944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780887256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3780887256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.1175178972 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 463005852 ps |
| CPU time | 36.14 seconds |
| Started | Aug 27 04:15:54 PM UTC 24 |
| Finished | Aug 27 04:16:32 PM UTC 24 |
| Peak memory | 269056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175178972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1175178972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.612079335 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 54631044668 ps |
| CPU time | 2974.67 seconds |
| Started | Aug 27 04:16:36 PM UTC 24 |
| Finished | Aug 27 05:06:44 PM UTC 24 |
| Peak memory | 298528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612079335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.612079335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/38.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.3340745419 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 167765411731 ps |
| CPU time | 1657.86 seconds |
| Started | Aug 27 04:16:41 PM UTC 24 |
| Finished | Aug 27 04:44:39 PM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340745419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3340745419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.4313629 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 18284448614 ps |
| CPU time | 315.4 seconds |
| Started | Aug 27 04:16:34 PM UTC 24 |
| Finished | Aug 27 04:21:53 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4313629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test + UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.4313629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.3961725155 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 352301835 ps |
| CPU time | 45.53 seconds |
| Started | Aug 27 04:15:42 PM UTC 24 |
| Finished | Aug 27 04:16:29 PM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961725155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3961725155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.2205553429 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 54640944 ps |
| CPU time | 7.66 seconds |
| Started | Aug 27 04:15:44 PM UTC 24 |
| Finished | Aug 27 04:15:53 PM UTC 24 |
| Peak memory | 262916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205553429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2205553429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/38.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.1685451139 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 55429940 ps |
| CPU time | 9.86 seconds |
| Started | Aug 27 04:16:30 PM UTC 24 |
| Finished | Aug 27 04:16:41 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685451139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1685451139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.3267938365 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 266640426 ps |
| CPU time | 13.46 seconds |
| Started | Aug 27 04:15:28 PM UTC 24 |
| Finished | Aug 27 04:15:43 PM UTC 24 |
| Peak memory | 269384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267938365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3267938365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/38.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.3353312842 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 285223495240 ps |
| CPU time | 3918.51 seconds |
| Started | Aug 27 04:16:54 PM UTC 24 |
| Finished | Aug 27 05:22:56 PM UTC 24 |
| Peak memory | 315172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353312842 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.3353312842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/38.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.3494415435 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 78020536280 ps |
| CPU time | 1465.7 seconds |
| Started | Aug 27 04:18:01 PM UTC 24 |
| Finished | Aug 27 04:42:43 PM UTC 24 |
| Peak memory | 302208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494415435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3494415435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/39.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.1456166514 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 716300288 ps |
| CPU time | 56.66 seconds |
| Started | Aug 27 04:17:52 PM UTC 24 |
| Finished | Aug 27 04:18:51 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456166514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1456166514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.2388308041 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 216686715 ps |
| CPU time | 16.88 seconds |
| Started | Aug 27 04:17:43 PM UTC 24 |
| Finished | Aug 27 04:18:01 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388308041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2388308041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.272980298 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 61406996375 ps |
| CPU time | 2123.22 seconds |
| Started | Aug 27 04:18:10 PM UTC 24 |
| Finished | Aug 27 04:54:00 PM UTC 24 |
| Peak memory | 298460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272980298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.272980298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/39.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.1562483628 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 11201632157 ps |
| CPU time | 1234.71 seconds |
| Started | Aug 27 04:18:20 PM UTC 24 |
| Finished | Aug 27 04:39:09 PM UTC 24 |
| Peak memory | 302280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562483628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1562483628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.4244498133 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 9062912470 ps |
| CPU time | 293.93 seconds |
| Started | Aug 27 04:18:04 PM UTC 24 |
| Finished | Aug 27 04:23:01 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244498133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.4244498133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.1280954979 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 3463354642 ps |
| CPU time | 27.12 seconds |
| Started | Aug 27 04:17:34 PM UTC 24 |
| Finished | Aug 27 04:18:03 PM UTC 24 |
| Peak memory | 262964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280954979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1280954979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.3591157997 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 3517310879 ps |
| CPU time | 37.13 seconds |
| Started | Aug 27 04:17:41 PM UTC 24 |
| Finished | Aug 27 04:18:19 PM UTC 24 |
| Peak memory | 262964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591157997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3591157997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/39.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.2495772497 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 717256776 ps |
| CPU time | 15.32 seconds |
| Started | Aug 27 04:17:52 PM UTC 24 |
| Finished | Aug 27 04:18:09 PM UTC 24 |
| Peak memory | 267324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495772497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2495772497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.1018805036 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1853329365 ps |
| CPU time | 73.37 seconds |
| Started | Aug 27 04:17:31 PM UTC 24 |
| Finished | Aug 27 04:18:47 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018805036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1018805036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/39.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.739082110 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3714989180 ps |
| CPU time | 379.3 seconds |
| Started | Aug 27 04:18:38 PM UTC 24 |
| Finished | Aug 27 04:25:03 PM UTC 24 |
| Peak memory | 279420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739082110 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.739082110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/39.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all_with_rand_reset.3190451512 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 4506489953 ps |
| CPU time | 236.55 seconds |
| Started | Aug 27 04:18:41 PM UTC 24 |
| Finished | Aug 27 04:22:42 PM UTC 24 |
| Peak memory | 279748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3190451512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.a lert_handler_stress_all_with_rand_reset.3190451512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/39.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.2129550508 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 312886419 ps |
| CPU time | 4.9 seconds |
| Started | Aug 27 03:13:00 PM UTC 24 |
| Finished | Aug 27 03:13:06 PM UTC 24 |
| Peak memory | 263172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129550508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2129550508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.2285775268 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 642731653 ps |
| CPU time | 41.89 seconds |
| Started | Aug 27 03:12:58 PM UTC 24 |
| Finished | Aug 27 03:13:41 PM UTC 24 |
| Peak memory | 263236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285775268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2285775268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.751473173 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 28595233524 ps |
| CPU time | 202.22 seconds |
| Started | Aug 27 03:12:51 PM UTC 24 |
| Finished | Aug 27 03:16:16 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751473173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.751473173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.1197687891 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 952460784 ps |
| CPU time | 64.2 seconds |
| Started | Aug 27 03:12:51 PM UTC 24 |
| Finished | Aug 27 03:13:57 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197687891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1197687891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.1743993984 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 8721346494 ps |
| CPU time | 877.29 seconds |
| Started | Aug 27 03:12:55 PM UTC 24 |
| Finished | Aug 27 03:27:43 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743993984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1743993984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.1259950 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 167955604 ps |
| CPU time | 12.07 seconds |
| Started | Aug 27 03:12:47 PM UTC 24 |
| Finished | Aug 27 03:13:04 PM UTC 24 |
| Peak memory | 266996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_rand om_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1259950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.1396928935 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2383182203 ps |
| CPU time | 38.34 seconds |
| Started | Aug 27 03:12:48 PM UTC 24 |
| Finished | Aug 27 03:13:29 PM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396928935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1396928935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.2304455578 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 624362333 ps |
| CPU time | 25.72 seconds |
| Started | Aug 27 03:13:01 PM UTC 24 |
| Finished | Aug 27 03:13:28 PM UTC 24 |
| Peak memory | 297472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304455578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2304455578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.2025589811 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 242246703 ps |
| CPU time | 8.4 seconds |
| Started | Aug 27 03:12:51 PM UTC 24 |
| Finished | Aug 27 03:13:00 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025589811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2025589811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.4135321380 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 579704170 ps |
| CPU time | 28.49 seconds |
| Started | Aug 27 03:12:44 PM UTC 24 |
| Finished | Aug 27 03:13:21 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135321380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.4135321380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.909372808 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 32615042772 ps |
| CPU time | 251.11 seconds |
| Started | Aug 27 03:12:58 PM UTC 24 |
| Finished | Aug 27 03:17:13 PM UTC 24 |
| Peak memory | 269444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909372808 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.909372808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/4.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.3044558968 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 22059319880 ps |
| CPU time | 1473.76 seconds |
| Started | Aug 27 04:20:02 PM UTC 24 |
| Finished | Aug 27 04:44:53 PM UTC 24 |
| Peak memory | 285568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044558968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3044558968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/40.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.2122780713 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 3195611395 ps |
| CPU time | 235 seconds |
| Started | Aug 27 04:19:48 PM UTC 24 |
| Finished | Aug 27 04:23:47 PM UTC 24 |
| Peak memory | 265080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122780713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2122780713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.845372887 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 199413804 ps |
| CPU time | 26.89 seconds |
| Started | Aug 27 04:19:19 PM UTC 24 |
| Finished | Aug 27 04:19:47 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845372887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.845372887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.3197683073 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 11565805999 ps |
| CPU time | 1027.19 seconds |
| Started | Aug 27 04:20:15 PM UTC 24 |
| Finished | Aug 27 04:37:34 PM UTC 24 |
| Peak memory | 302212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197683073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3197683073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/40.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.1365565899 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 92443236950 ps |
| CPU time | 1356.49 seconds |
| Started | Aug 27 04:20:16 PM UTC 24 |
| Finished | Aug 27 04:43:07 PM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365565899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1365565899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.2043527313 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 10239652599 ps |
| CPU time | 261.91 seconds |
| Started | Aug 27 04:20:08 PM UTC 24 |
| Finished | Aug 27 04:24:33 PM UTC 24 |
| Peak memory | 263368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043527313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2043527313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.3738446862 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 5943372792 ps |
| CPU time | 79.72 seconds |
| Started | Aug 27 04:18:52 PM UTC 24 |
| Finished | Aug 27 04:20:13 PM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738446862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3738446862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.2971934588 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 972204348 ps |
| CPU time | 82.78 seconds |
| Started | Aug 27 04:19:13 PM UTC 24 |
| Finished | Aug 27 04:20:38 PM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971934588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2971934588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/40.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.2071502779 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 292581766 ps |
| CPU time | 36.14 seconds |
| Started | Aug 27 04:19:59 PM UTC 24 |
| Finished | Aug 27 04:20:36 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071502779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2071502779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.2648830351 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 468838237 ps |
| CPU time | 28.89 seconds |
| Started | Aug 27 04:18:48 PM UTC 24 |
| Finished | Aug 27 04:19:18 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648830351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2648830351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/40.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.884864734 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1715488556 ps |
| CPU time | 53.04 seconds |
| Started | Aug 27 04:20:37 PM UTC 24 |
| Finished | Aug 27 04:21:32 PM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884864734 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.884864734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/40.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all_with_rand_reset.753389784 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 75757038510 ps |
| CPU time | 269.4 seconds |
| Started | Aug 27 04:20:39 PM UTC 24 |
| Finished | Aug 27 04:25:13 PM UTC 24 |
| Peak memory | 283648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=753389784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.al ert_handler_stress_all_with_rand_reset.753389784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.3778340602 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 118368055500 ps |
| CPU time | 1739.28 seconds |
| Started | Aug 27 04:21:57 PM UTC 24 |
| Finished | Aug 27 04:51:15 PM UTC 24 |
| Peak memory | 298788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778340602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3778340602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/41.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.3452705325 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 8759187527 ps |
| CPU time | 242.13 seconds |
| Started | Aug 27 04:21:47 PM UTC 24 |
| Finished | Aug 27 04:25:53 PM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452705325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3452705325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.3827114713 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2817206207 ps |
| CPU time | 31.42 seconds |
| Started | Aug 27 04:21:41 PM UTC 24 |
| Finished | Aug 27 04:22:14 PM UTC 24 |
| Peak memory | 263072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827114713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3827114713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.71113835 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 79243187463 ps |
| CPU time | 2314.47 seconds |
| Started | Aug 27 04:22:06 PM UTC 24 |
| Finished | Aug 27 05:01:06 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71113835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.71113835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/41.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.2415137191 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 26066120114 ps |
| CPU time | 1080.92 seconds |
| Started | Aug 27 04:22:09 PM UTC 24 |
| Finished | Aug 27 04:40:23 PM UTC 24 |
| Peak memory | 301888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415137191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2415137191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.3097964362 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 25472278484 ps |
| CPU time | 283.63 seconds |
| Started | Aug 27 04:21:57 PM UTC 24 |
| Finished | Aug 27 04:26:44 PM UTC 24 |
| Peak memory | 267144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097964362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3097964362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.3947835031 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 326914698 ps |
| CPU time | 25.43 seconds |
| Started | Aug 27 04:21:20 PM UTC 24 |
| Finished | Aug 27 04:21:47 PM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947835031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3947835031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.1117896253 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 954740138 ps |
| CPU time | 21.76 seconds |
| Started | Aug 27 04:21:32 PM UTC 24 |
| Finished | Aug 27 04:21:55 PM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117896253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1117896253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/41.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.564136277 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 119157809 ps |
| CPU time | 19.48 seconds |
| Started | Aug 27 04:21:54 PM UTC 24 |
| Finished | Aug 27 04:22:15 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564136277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.564136277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.388459249 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 783650591 ps |
| CPU time | 65.31 seconds |
| Started | Aug 27 04:20:49 PM UTC 24 |
| Finished | Aug 27 04:21:56 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388459249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.388459249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/41.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.960097836 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 66798437089 ps |
| CPU time | 1507.44 seconds |
| Started | Aug 27 04:22:15 PM UTC 24 |
| Finished | Aug 27 04:47:40 PM UTC 24 |
| Peak memory | 302268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960097836 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.960097836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/41.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.1622665487 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 21173922565 ps |
| CPU time | 1361.83 seconds |
| Started | Aug 27 04:23:08 PM UTC 24 |
| Finished | Aug 27 04:46:05 PM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622665487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1622665487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/42.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.3904052405 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 40072677168 ps |
| CPU time | 298.14 seconds |
| Started | Aug 27 04:22:52 PM UTC 24 |
| Finished | Aug 27 04:27:54 PM UTC 24 |
| Peak memory | 269176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904052405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3904052405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.3918489311 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 420404998 ps |
| CPU time | 53.95 seconds |
| Started | Aug 27 04:22:50 PM UTC 24 |
| Finished | Aug 27 04:23:45 PM UTC 24 |
| Peak memory | 269152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918489311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3918489311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg.4074903129 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 39244233678 ps |
| CPU time | 2225.71 seconds |
| Started | Aug 27 04:23:32 PM UTC 24 |
| Finished | Aug 27 05:01:03 PM UTC 24 |
| Peak memory | 288224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074903129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.4074903129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/42.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.1842569705 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 30966850142 ps |
| CPU time | 1132.08 seconds |
| Started | Aug 27 04:23:38 PM UTC 24 |
| Finished | Aug 27 04:42:44 PM UTC 24 |
| Peak memory | 283528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842569705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1842569705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.3524314910 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 21409926809 ps |
| CPU time | 448.03 seconds |
| Started | Aug 27 04:23:16 PM UTC 24 |
| Finished | Aug 27 04:30:50 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524314910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3524314910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.3680390508 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 1608806995 ps |
| CPU time | 47.61 seconds |
| Started | Aug 27 04:22:43 PM UTC 24 |
| Finished | Aug 27 04:23:32 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680390508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3680390508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.1727376515 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2143614670 ps |
| CPU time | 48.09 seconds |
| Started | Aug 27 04:22:47 PM UTC 24 |
| Finished | Aug 27 04:23:36 PM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727376515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1727376515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/42.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.3880296097 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1526898587 ps |
| CPU time | 39.87 seconds |
| Started | Aug 27 04:23:03 PM UTC 24 |
| Finished | Aug 27 04:23:44 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880296097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3880296097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.2257575659 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 91985424 ps |
| CPU time | 9.8 seconds |
| Started | Aug 27 04:22:35 PM UTC 24 |
| Finished | Aug 27 04:22:46 PM UTC 24 |
| Peak memory | 265032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257575659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2257575659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/42.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.3168133378 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 111074035662 ps |
| CPU time | 1901.54 seconds |
| Started | Aug 27 04:23:42 PM UTC 24 |
| Finished | Aug 27 04:55:45 PM UTC 24 |
| Peak memory | 304996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168133378 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.3168133378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/42.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.1711814311 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 102392969894 ps |
| CPU time | 1924.84 seconds |
| Started | Aug 27 04:24:36 PM UTC 24 |
| Finished | Aug 27 04:57:04 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711814311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1711814311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/43.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.3957909725 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 5602201566 ps |
| CPU time | 268.9 seconds |
| Started | Aug 27 04:24:29 PM UTC 24 |
| Finished | Aug 27 04:29:02 PM UTC 24 |
| Peak memory | 269176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957909725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3957909725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.1030507521 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1221718659 ps |
| CPU time | 11.6 seconds |
| Started | Aug 27 04:24:16 PM UTC 24 |
| Finished | Aug 27 04:24:29 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030507521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1030507521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.3237502249 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 34501515192 ps |
| CPU time | 1690.2 seconds |
| Started | Aug 27 04:25:04 PM UTC 24 |
| Finished | Aug 27 04:53:35 PM UTC 24 |
| Peak memory | 302216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237502249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3237502249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.1255447940 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 85636322843 ps |
| CPU time | 462.75 seconds |
| Started | Aug 27 04:24:36 PM UTC 24 |
| Finished | Aug 27 04:32:25 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255447940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1255447940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.217627405 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2359935966 ps |
| CPU time | 95.03 seconds |
| Started | Aug 27 04:23:47 PM UTC 24 |
| Finished | Aug 27 04:25:25 PM UTC 24 |
| Peak memory | 263288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217627405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.217627405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.1045370825 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 356829039 ps |
| CPU time | 28.72 seconds |
| Started | Aug 27 04:24:05 PM UTC 24 |
| Finished | Aug 27 04:24:35 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045370825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1045370825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/43.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.3481405400 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 413664952 ps |
| CPU time | 27.4 seconds |
| Started | Aug 27 04:23:46 PM UTC 24 |
| Finished | Aug 27 04:24:15 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481405400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3481405400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/43.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.1128073466 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 493012365363 ps |
| CPU time | 2251.58 seconds |
| Started | Aug 27 04:25:10 PM UTC 24 |
| Finished | Aug 27 05:03:08 PM UTC 24 |
| Peak memory | 302556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128073466 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.1128073466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/43.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.1364686819 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 242513219140 ps |
| CPU time | 1319.44 seconds |
| Started | Aug 27 04:26:02 PM UTC 24 |
| Finished | Aug 27 04:48:17 PM UTC 24 |
| Peak memory | 301952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364686819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1364686819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/44.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.2356787991 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1975218778 ps |
| CPU time | 54.35 seconds |
| Started | Aug 27 04:25:50 PM UTC 24 |
| Finished | Aug 27 04:26:46 PM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356787991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2356787991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.906356398 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 265080326 ps |
| CPU time | 30.95 seconds |
| Started | Aug 27 04:25:47 PM UTC 24 |
| Finished | Aug 27 04:26:20 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906356398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.906356398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.609262546 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 37440236174 ps |
| CPU time | 2349.07 seconds |
| Started | Aug 27 04:26:04 PM UTC 24 |
| Finished | Aug 27 05:05:40 PM UTC 24 |
| Peak memory | 298528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609262546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.609262546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/44.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.3938194024 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 56648074255 ps |
| CPU time | 1573.56 seconds |
| Started | Aug 27 04:26:08 PM UTC 24 |
| Finished | Aug 27 04:52:40 PM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938194024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3938194024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.2393158329 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 17717709591 ps |
| CPU time | 318.94 seconds |
| Started | Aug 27 04:26:04 PM UTC 24 |
| Finished | Aug 27 04:31:27 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393158329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2393158329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.1530444471 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 241143020 ps |
| CPU time | 20.81 seconds |
| Started | Aug 27 04:25:26 PM UTC 24 |
| Finished | Aug 27 04:25:49 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530444471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1530444471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.799764787 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 776396276 ps |
| CPU time | 64.88 seconds |
| Started | Aug 27 04:25:26 PM UTC 24 |
| Finished | Aug 27 04:26:34 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799764787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.799764787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/44.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.3147952570 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 120988827 ps |
| CPU time | 6.16 seconds |
| Started | Aug 27 04:25:54 PM UTC 24 |
| Finished | Aug 27 04:26:01 PM UTC 24 |
| Peak memory | 265276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147952570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3147952570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.1675593142 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 1138690283 ps |
| CPU time | 46.01 seconds |
| Started | Aug 27 04:25:15 PM UTC 24 |
| Finished | Aug 27 04:26:03 PM UTC 24 |
| Peak memory | 269384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675593142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1675593142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/44.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.38892044 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 21452706860 ps |
| CPU time | 974.51 seconds |
| Started | Aug 27 04:26:17 PM UTC 24 |
| Finished | Aug 27 04:42:42 PM UTC 24 |
| Peak memory | 300164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38892044 -assert nopostproc +UVM_TES TNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.38892044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/44.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.3999351434 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 143042622683 ps |
| CPU time | 2040.51 seconds |
| Started | Aug 27 04:26:59 PM UTC 24 |
| Finished | Aug 27 05:01:23 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999351434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3999351434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/45.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.1499582703 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1365998723 ps |
| CPU time | 53.46 seconds |
| Started | Aug 27 04:26:55 PM UTC 24 |
| Finished | Aug 27 04:27:50 PM UTC 24 |
| Peak memory | 269368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499582703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1499582703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.374180118 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 110747710 ps |
| CPU time | 10.11 seconds |
| Started | Aug 27 04:26:50 PM UTC 24 |
| Finished | Aug 27 04:27:02 PM UTC 24 |
| Peak memory | 263168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374180118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.374180118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg.3737458139 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 34051328071 ps |
| CPU time | 1459.88 seconds |
| Started | Aug 27 04:27:10 PM UTC 24 |
| Finished | Aug 27 04:51:46 PM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737458139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3737458139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/45.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.328061295 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 15959360533 ps |
| CPU time | 1123.84 seconds |
| Started | Aug 27 04:27:19 PM UTC 24 |
| Finished | Aug 27 04:46:17 PM UTC 24 |
| Peak memory | 279352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328061295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.328061295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.923226185 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 18202531913 ps |
| CPU time | 115.51 seconds |
| Started | Aug 27 04:27:03 PM UTC 24 |
| Finished | Aug 27 04:29:00 PM UTC 24 |
| Peak memory | 263040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923226185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.923226185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.1908740299 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 369786555 ps |
| CPU time | 11.5 seconds |
| Started | Aug 27 04:26:45 PM UTC 24 |
| Finished | Aug 27 04:26:58 PM UTC 24 |
| Peak memory | 267100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908740299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1908740299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.760758318 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 101729934 ps |
| CPU time | 20.38 seconds |
| Started | Aug 27 04:26:47 PM UTC 24 |
| Finished | Aug 27 04:27:09 PM UTC 24 |
| Peak memory | 269080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760758318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.760758318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/45.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.3960656352 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 319074135 ps |
| CPU time | 19.06 seconds |
| Started | Aug 27 04:26:59 PM UTC 24 |
| Finished | Aug 27 04:27:19 PM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960656352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3960656352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.1382982351 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1061931497 ps |
| CPU time | 18.97 seconds |
| Started | Aug 27 04:26:35 PM UTC 24 |
| Finished | Aug 27 04:26:55 PM UTC 24 |
| Peak memory | 262984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382982351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1382982351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/45.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.1983082299 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 104537274305 ps |
| CPU time | 2502.28 seconds |
| Started | Aug 27 04:27:20 PM UTC 24 |
| Finished | Aug 27 05:09:32 PM UTC 24 |
| Peak memory | 320988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983082299 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.1983082299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/45.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.3182337788 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 21101905024 ps |
| CPU time | 341.93 seconds |
| Started | Aug 27 04:28:10 PM UTC 24 |
| Finished | Aug 27 04:33:57 PM UTC 24 |
| Peak memory | 269432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182337788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3182337788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.3356905861 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1398351090 ps |
| CPU time | 38.95 seconds |
| Started | Aug 27 04:28:03 PM UTC 24 |
| Finished | Aug 27 04:28:43 PM UTC 24 |
| Peak memory | 263328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356905861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3356905861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.3697010346 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 27282900005 ps |
| CPU time | 1418.21 seconds |
| Started | Aug 27 04:29:02 PM UTC 24 |
| Finished | Aug 27 04:52:57 PM UTC 24 |
| Peak memory | 297864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697010346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3697010346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.3159722446 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 5571388083 ps |
| CPU time | 347.02 seconds |
| Started | Aug 27 04:28:41 PM UTC 24 |
| Finished | Aug 27 04:34:33 PM UTC 24 |
| Peak memory | 269448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159722446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3159722446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.2183082928 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 95950098 ps |
| CPU time | 9.89 seconds |
| Started | Aug 27 04:27:51 PM UTC 24 |
| Finished | Aug 27 04:28:02 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183082928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2183082928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.2383490168 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 2449331335 ps |
| CPU time | 27.21 seconds |
| Started | Aug 27 04:27:55 PM UTC 24 |
| Finished | Aug 27 04:28:24 PM UTC 24 |
| Peak memory | 262996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383490168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2383490168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/46.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.2661578908 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 818487124 ps |
| CPU time | 66.54 seconds |
| Started | Aug 27 04:28:19 PM UTC 24 |
| Finished | Aug 27 04:29:27 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661578908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2661578908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.3991490488 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 558113207 ps |
| CPU time | 31.84 seconds |
| Started | Aug 27 04:27:36 PM UTC 24 |
| Finished | Aug 27 04:28:09 PM UTC 24 |
| Peak memory | 269056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991490488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3991490488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/46.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.1173875310 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 181457517796 ps |
| CPU time | 2488.17 seconds |
| Started | Aug 27 04:29:03 PM UTC 24 |
| Finished | Aug 27 05:10:59 PM UTC 24 |
| Peak memory | 304804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173875310 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.1173875310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/46.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all_with_rand_reset.3349943230 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 18525686295 ps |
| CPU time | 338.51 seconds |
| Started | Aug 27 04:29:28 PM UTC 24 |
| Finished | Aug 27 04:35:11 PM UTC 24 |
| Peak memory | 279480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3349943230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.a lert_handler_stress_all_with_rand_reset.3349943230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.250622714 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 12332797814 ps |
| CPU time | 1051.06 seconds |
| Started | Aug 27 04:31:50 PM UTC 24 |
| Finished | Aug 27 04:49:33 PM UTC 24 |
| Peak memory | 301880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250622714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.250622714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/47.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.2226255764 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 6824659779 ps |
| CPU time | 145.17 seconds |
| Started | Aug 27 04:31:28 PM UTC 24 |
| Finished | Aug 27 04:33:55 PM UTC 24 |
| Peak memory | 265084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226255764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2226255764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.2988128977 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 2556990049 ps |
| CPU time | 29.33 seconds |
| Started | Aug 27 04:31:23 PM UTC 24 |
| Finished | Aug 27 04:31:54 PM UTC 24 |
| Peak memory | 269216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988128977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2988128977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.1905788148 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 21381195355 ps |
| CPU time | 1598.93 seconds |
| Started | Aug 27 04:32:06 PM UTC 24 |
| Finished | Aug 27 04:59:04 PM UTC 24 |
| Peak memory | 295812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905788148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1905788148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/47.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.3446558809 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 16258070889 ps |
| CPU time | 675.46 seconds |
| Started | Aug 27 04:32:09 PM UTC 24 |
| Finished | Aug 27 04:43:32 PM UTC 24 |
| Peak memory | 285504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446558809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3446558809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.3521066531 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 6544573268 ps |
| CPU time | 256.76 seconds |
| Started | Aug 27 04:31:55 PM UTC 24 |
| Finished | Aug 27 04:36:16 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521066531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3521066531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.299245339 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 732838689 ps |
| CPU time | 15.07 seconds |
| Started | Aug 27 04:31:11 PM UTC 24 |
| Finished | Aug 27 04:31:27 PM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299245339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.299245339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.3916995030 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2503915768 ps |
| CPU time | 46.76 seconds |
| Started | Aug 27 04:31:19 PM UTC 24 |
| Finished | Aug 27 04:32:08 PM UTC 24 |
| Peak memory | 263324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916995030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3916995030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/47.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.326125846 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 257558832 ps |
| CPU time | 18.4 seconds |
| Started | Aug 27 04:30:51 PM UTC 24 |
| Finished | Aug 27 04:31:10 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326125846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.326125846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/47.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.672641221 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 97349011467 ps |
| CPU time | 633.25 seconds |
| Started | Aug 27 04:32:17 PM UTC 24 |
| Finished | Aug 27 04:42:58 PM UTC 24 |
| Peak memory | 279484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672641221 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.672641221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/47.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all_with_rand_reset.3566666514 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 11783023012 ps |
| CPU time | 276.26 seconds |
| Started | Aug 27 04:32:25 PM UTC 24 |
| Finished | Aug 27 04:37:06 PM UTC 24 |
| Peak memory | 285700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3566666514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.a lert_handler_stress_all_with_rand_reset.3566666514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.2635325188 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 177892555503 ps |
| CPU time | 2733.89 seconds |
| Started | Aug 27 04:34:17 PM UTC 24 |
| Finished | Aug 27 05:20:23 PM UTC 24 |
| Peak memory | 300580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635325188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2635325188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/48.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.539579738 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1531612107 ps |
| CPU time | 118.2 seconds |
| Started | Aug 27 04:33:58 PM UTC 24 |
| Finished | Aug 27 04:35:59 PM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539579738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.539579738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.3811660278 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 42978094 ps |
| CPU time | 5.3 seconds |
| Started | Aug 27 04:33:56 PM UTC 24 |
| Finished | Aug 27 04:34:02 PM UTC 24 |
| Peak memory | 253024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811660278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3811660278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.2398017283 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 109480942691 ps |
| CPU time | 2997.18 seconds |
| Started | Aug 27 04:34:24 PM UTC 24 |
| Finished | Aug 27 05:24:55 PM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398017283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2398017283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/48.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.2923649248 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 129251795718 ps |
| CPU time | 2200.66 seconds |
| Started | Aug 27 04:34:26 PM UTC 24 |
| Finished | Aug 27 05:11:32 PM UTC 24 |
| Peak memory | 298604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923649248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2923649248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.3120943507 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 68549834422 ps |
| CPU time | 321.18 seconds |
| Started | Aug 27 04:34:17 PM UTC 24 |
| Finished | Aug 27 04:39:43 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120943507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3120943507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.1012007081 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 433408156 ps |
| CPU time | 20.68 seconds |
| Started | Aug 27 04:33:29 PM UTC 24 |
| Finished | Aug 27 04:33:51 PM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012007081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1012007081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.3296122171 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 5166735051 ps |
| CPU time | 88.93 seconds |
| Started | Aug 27 04:33:52 PM UTC 24 |
| Finished | Aug 27 04:35:23 PM UTC 24 |
| Peak memory | 263324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296122171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3296122171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/48.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.3040186644 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 67137724 ps |
| CPU time | 11.94 seconds |
| Started | Aug 27 04:34:04 PM UTC 24 |
| Finished | Aug 27 04:34:17 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040186644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3040186644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.701366208 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1336403338 ps |
| CPU time | 42.7 seconds |
| Started | Aug 27 04:32:43 PM UTC 24 |
| Finished | Aug 27 04:33:28 PM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701366208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.701366208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/48.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.2283871902 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 11994986585 ps |
| CPU time | 1503.71 seconds |
| Started | Aug 27 04:34:34 PM UTC 24 |
| Finished | Aug 27 04:59:56 PM UTC 24 |
| Peak memory | 301952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283871902 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.2283871902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/48.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all_with_rand_reset.1385183303 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 3478928680 ps |
| CPU time | 127.74 seconds |
| Started | Aug 27 04:35:05 PM UTC 24 |
| Finished | Aug 27 04:37:16 PM UTC 24 |
| Peak memory | 283652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1385183303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.a lert_handler_stress_all_with_rand_reset.1385183303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.3071922907 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 28175824115 ps |
| CPU time | 1323.74 seconds |
| Started | Aug 27 04:36:16 PM UTC 24 |
| Finished | Aug 27 04:58:36 PM UTC 24 |
| Peak memory | 301952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071922907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3071922907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/49.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.40142084 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 5537760709 ps |
| CPU time | 192.9 seconds |
| Started | Aug 27 04:36:08 PM UTC 24 |
| Finished | Aug 27 04:39:25 PM UTC 24 |
| Peak memory | 265116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40142084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc _alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.40142084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.2059437378 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 44782416 ps |
| CPU time | 5.98 seconds |
| Started | Aug 27 04:36:00 PM UTC 24 |
| Finished | Aug 27 04:36:07 PM UTC 24 |
| Peak memory | 263200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059437378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2059437378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.2785028091 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 375961944231 ps |
| CPU time | 2602.36 seconds |
| Started | Aug 27 04:36:29 PM UTC 24 |
| Finished | Aug 27 05:20:20 PM UTC 24 |
| Peak memory | 304612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785028091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2785028091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/49.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.1043160138 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 39302381421 ps |
| CPU time | 1090.28 seconds |
| Started | Aug 27 04:37:00 PM UTC 24 |
| Finished | Aug 27 04:55:24 PM UTC 24 |
| Peak memory | 295744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043160138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1043160138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.1617808661 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 25487876329 ps |
| CPU time | 560.83 seconds |
| Started | Aug 27 04:36:26 PM UTC 24 |
| Finished | Aug 27 04:45:54 PM UTC 24 |
| Peak memory | 263368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617808661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1617808661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.4284241025 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 783622216 ps |
| CPU time | 43.87 seconds |
| Started | Aug 27 04:35:23 PM UTC 24 |
| Finished | Aug 27 04:36:09 PM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284241025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.4284241025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.2546546127 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 208637563 ps |
| CPU time | 28.65 seconds |
| Started | Aug 27 04:35:56 PM UTC 24 |
| Finished | Aug 27 04:36:26 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546546127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2546546127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/49.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.385341846 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 765639403 ps |
| CPU time | 41.18 seconds |
| Started | Aug 27 04:35:12 PM UTC 24 |
| Finished | Aug 27 04:35:55 PM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385341846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.385341846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/49.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.116925793 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 24737259274 ps |
| CPU time | 2174.86 seconds |
| Started | Aug 27 04:37:02 PM UTC 24 |
| Finished | Aug 27 05:13:42 PM UTC 24 |
| Peak memory | 319752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116925793 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.116925793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/49.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.24610830 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 36234637 ps |
| CPU time | 3.51 seconds |
| Started | Aug 27 03:13:19 PM UTC 24 |
| Finished | Aug 27 03:13:23 PM UTC 24 |
| Peak memory | 263244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24610830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h andler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_h andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.24610830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.442977414 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 56080102981 ps |
| CPU time | 2785.56 seconds |
| Started | Aug 27 03:13:08 PM UTC 24 |
| Finished | Aug 27 04:00:03 PM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442977414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.442977414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.1604527283 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 866357335 ps |
| CPU time | 18.64 seconds |
| Started | Aug 27 03:13:14 PM UTC 24 |
| Finished | Aug 27 03:13:34 PM UTC 24 |
| Peak memory | 262940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604527283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1604527283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.573820524 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 19049307756 ps |
| CPU time | 106.9 seconds |
| Started | Aug 27 03:13:06 PM UTC 24 |
| Finished | Aug 27 03:14:55 PM UTC 24 |
| Peak memory | 269468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573820524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.573820524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.314337677 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1043223676 ps |
| CPU time | 35.01 seconds |
| Started | Aug 27 03:13:05 PM UTC 24 |
| Finished | Aug 27 03:13:41 PM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314337677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.314337677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.424042741 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 41220024511 ps |
| CPU time | 2407.26 seconds |
| Started | Aug 27 03:13:13 PM UTC 24 |
| Finished | Aug 27 03:53:48 PM UTC 24 |
| Peak memory | 288224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424042741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.424042741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.3564705895 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1134195296 ps |
| CPU time | 61.42 seconds |
| Started | Aug 27 03:13:03 PM UTC 24 |
| Finished | Aug 27 03:14:06 PM UTC 24 |
| Peak memory | 269380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564705895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3564705895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.515397762 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 280506887 ps |
| CPU time | 45.48 seconds |
| Started | Aug 27 03:13:07 PM UTC 24 |
| Finished | Aug 27 03:13:54 PM UTC 24 |
| Peak memory | 263296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515397762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.515397762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.2165890897 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1512422387 ps |
| CPU time | 72.04 seconds |
| Started | Aug 27 03:13:02 PM UTC 24 |
| Finished | Aug 27 03:14:15 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165890897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2165890897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all.2622112432 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 76496758320 ps |
| CPU time | 1983.85 seconds |
| Started | Aug 27 03:13:19 PM UTC 24 |
| Finished | Aug 27 03:46:44 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622112432 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.2622112432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all_with_rand_reset.949701395 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3687535844 ps |
| CPU time | 130.87 seconds |
| Started | Aug 27 03:13:22 PM UTC 24 |
| Finished | Aug 27 03:15:35 PM UTC 24 |
| Peak memory | 279616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=949701395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.ale rt_handler_stress_all_with_rand_reset.949701395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.1698159944 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 52781755 ps |
| CPU time | 4.24 seconds |
| Started | Aug 27 03:13:42 PM UTC 24 |
| Finished | Aug 27 03:13:48 PM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698159944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1698159944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.3955248265 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 233421216554 ps |
| CPU time | 1280.48 seconds |
| Started | Aug 27 03:13:31 PM UTC 24 |
| Finished | Aug 27 03:35:05 PM UTC 24 |
| Peak memory | 285828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955248265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3955248265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.131057530 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 136244560 ps |
| CPU time | 11.38 seconds |
| Started | Aug 27 03:13:35 PM UTC 24 |
| Finished | Aug 27 03:13:48 PM UTC 24 |
| Peak memory | 263044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131057530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.131057530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.3489279137 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1136366990 ps |
| CPU time | 74.12 seconds |
| Started | Aug 27 03:13:26 PM UTC 24 |
| Finished | Aug 27 03:14:42 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489279137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3489279137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.3400659512 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 190971508 ps |
| CPU time | 3.47 seconds |
| Started | Aug 27 03:13:25 PM UTC 24 |
| Finished | Aug 27 03:13:30 PM UTC 24 |
| Peak memory | 252992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400659512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3400659512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.2849729195 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 13033838976 ps |
| CPU time | 1481.02 seconds |
| Started | Aug 27 03:13:33 PM UTC 24 |
| Finished | Aug 27 03:38:33 PM UTC 24 |
| Peak memory | 301880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849729195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2849729195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.2662571069 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 9139509601 ps |
| CPU time | 367.88 seconds |
| Started | Aug 27 03:13:31 PM UTC 24 |
| Finished | Aug 27 03:19:43 PM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662571069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2662571069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.3645696491 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 392211551 ps |
| CPU time | 35.75 seconds |
| Started | Aug 27 03:13:24 PM UTC 24 |
| Finished | Aug 27 03:14:01 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645696491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3645696491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.4273568820 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 439082968 ps |
| CPU time | 41.59 seconds |
| Started | Aug 27 03:13:28 PM UTC 24 |
| Finished | Aug 27 03:14:12 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273568820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.4273568820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.2366892604 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2481965833 ps |
| CPU time | 32.96 seconds |
| Started | Aug 27 03:13:22 PM UTC 24 |
| Finished | Aug 27 03:13:56 PM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366892604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2366892604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.661980767 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 374314493490 ps |
| CPU time | 2197.6 seconds |
| Started | Aug 27 03:13:42 PM UTC 24 |
| Finished | Aug 27 03:50:43 PM UTC 24 |
| Peak memory | 302560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661980767 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.661980767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/6.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.1033959429 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 20452807 ps |
| CPU time | 3.62 seconds |
| Started | Aug 27 03:14:07 PM UTC 24 |
| Finished | Aug 27 03:14:11 PM UTC 24 |
| Peak memory | 263500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033959429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1033959429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.2419715257 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 844126535 ps |
| CPU time | 18.17 seconds |
| Started | Aug 27 03:14:02 PM UTC 24 |
| Finished | Aug 27 03:14:22 PM UTC 24 |
| Peak memory | 263044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419715257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2419715257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.2927776776 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2205736011 ps |
| CPU time | 116.09 seconds |
| Started | Aug 27 03:13:50 PM UTC 24 |
| Finished | Aug 27 03:15:48 PM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927776776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2927776776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.3612005764 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1041457146 ps |
| CPU time | 59.43 seconds |
| Started | Aug 27 03:13:50 PM UTC 24 |
| Finished | Aug 27 03:14:51 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612005764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3612005764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.3954549772 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 139970900072 ps |
| CPU time | 2152.99 seconds |
| Started | Aug 27 03:13:57 PM UTC 24 |
| Finished | Aug 27 03:50:13 PM UTC 24 |
| Peak memory | 304944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954549772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3954549772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.2544459986 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 236948805 ps |
| CPU time | 14.33 seconds |
| Started | Aug 27 03:13:48 PM UTC 24 |
| Finished | Aug 27 03:14:04 PM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544459986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2544459986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.294800003 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 997995436 ps |
| CPU time | 23.04 seconds |
| Started | Aug 27 03:13:49 PM UTC 24 |
| Finished | Aug 27 03:14:13 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294800003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.294800003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.166227174 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 259804715 ps |
| CPU time | 15.73 seconds |
| Started | Aug 27 03:13:51 PM UTC 24 |
| Finished | Aug 27 03:14:08 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166227174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.166227174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.969574751 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 353435723 ps |
| CPU time | 7.93 seconds |
| Started | Aug 27 03:13:44 PM UTC 24 |
| Finished | Aug 27 03:13:54 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969574751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.969574751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all_with_rand_reset.1376146679 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4533104163 ps |
| CPU time | 149.21 seconds |
| Started | Aug 27 03:14:09 PM UTC 24 |
| Finished | Aug 27 03:16:41 PM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1376146679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.al ert_handler_stress_all_with_rand_reset.1376146679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.3936761580 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 43353689 ps |
| CPU time | 4.64 seconds |
| Started | Aug 27 03:14:44 PM UTC 24 |
| Finished | Aug 27 03:14:50 PM UTC 24 |
| Peak memory | 263500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936761580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3936761580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.1558604079 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 38288216110 ps |
| CPU time | 2493.18 seconds |
| Started | Aug 27 03:14:25 PM UTC 24 |
| Finished | Aug 27 03:56:26 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558604079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1558604079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.2244894599 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 766754106 ps |
| CPU time | 12.51 seconds |
| Started | Aug 27 03:14:42 PM UTC 24 |
| Finished | Aug 27 03:14:56 PM UTC 24 |
| Peak memory | 263016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244894599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2244894599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.2717253738 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 5687435841 ps |
| CPU time | 208.45 seconds |
| Started | Aug 27 03:14:16 PM UTC 24 |
| Finished | Aug 27 03:17:48 PM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717253738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2717253738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.3596134485 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 230727236 ps |
| CPU time | 25.58 seconds |
| Started | Aug 27 03:14:14 PM UTC 24 |
| Finished | Aug 27 03:14:41 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596134485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3596134485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.2547184248 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 194790265599 ps |
| CPU time | 2714.14 seconds |
| Started | Aug 27 03:14:28 PM UTC 24 |
| Finished | Aug 27 04:00:11 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547184248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2547184248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.224741388 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 89508279361 ps |
| CPU time | 1444.16 seconds |
| Started | Aug 27 03:14:33 PM UTC 24 |
| Finished | Aug 27 03:38:54 PM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224741388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.224741388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.956996695 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 8187994316 ps |
| CPU time | 139.44 seconds |
| Started | Aug 27 03:14:25 PM UTC 24 |
| Finished | Aug 27 03:16:46 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956996695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.956996695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.1645635624 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8701705959 ps |
| CPU time | 44.85 seconds |
| Started | Aug 27 03:14:12 PM UTC 24 |
| Finished | Aug 27 03:14:58 PM UTC 24 |
| Peak memory | 269436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645635624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1645635624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.3392136086 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 31563880 ps |
| CPU time | 5.33 seconds |
| Started | Aug 27 03:14:13 PM UTC 24 |
| Finished | Aug 27 03:14:20 PM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392136086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3392136086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.2290034160 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1267416578 ps |
| CPU time | 10.5 seconds |
| Started | Aug 27 03:14:20 PM UTC 24 |
| Finished | Aug 27 03:14:32 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290034160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2290034160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.1111442851 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1467956161 ps |
| CPU time | 39.91 seconds |
| Started | Aug 27 03:14:12 PM UTC 24 |
| Finished | Aug 27 03:14:53 PM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111442851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1111442851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.2080776653 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 67963923686 ps |
| CPU time | 1475.26 seconds |
| Started | Aug 27 03:14:43 PM UTC 24 |
| Finished | Aug 27 03:39:35 PM UTC 24 |
| Peak memory | 302204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080776653 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.2080776653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/8.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.2838986986 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 22561143 ps |
| CPU time | 3.5 seconds |
| Started | Aug 27 03:15:48 PM UTC 24 |
| Finished | Aug 27 03:15:52 PM UTC 24 |
| Peak memory | 263500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838986986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2838986986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.3812643071 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 89208155643 ps |
| CPU time | 2549.25 seconds |
| Started | Aug 27 03:15:06 PM UTC 24 |
| Finished | Aug 27 03:58:03 PM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812643071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3812643071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.1672269993 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 539446021 ps |
| CPU time | 34.49 seconds |
| Started | Aug 27 03:15:35 PM UTC 24 |
| Finished | Aug 27 03:16:12 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672269993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1672269993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.639592440 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1824878794 ps |
| CPU time | 99.9 seconds |
| Started | Aug 27 03:14:57 PM UTC 24 |
| Finished | Aug 27 03:16:39 PM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639592440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.639592440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.983584639 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1609695560 ps |
| CPU time | 48.41 seconds |
| Started | Aug 27 03:14:56 PM UTC 24 |
| Finished | Aug 27 03:15:46 PM UTC 24 |
| Peak memory | 263224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983584639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.983584639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.1777440956 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 57741940128 ps |
| CPU time | 1388.82 seconds |
| Started | Aug 27 03:15:15 PM UTC 24 |
| Finished | Aug 27 03:38:40 PM UTC 24 |
| Peak memory | 297860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777440956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1777440956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.574758929 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 36710824133 ps |
| CPU time | 149.29 seconds |
| Started | Aug 27 03:15:07 PM UTC 24 |
| Finished | Aug 27 03:17:39 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574758929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.574758929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.1897192658 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1236092203 ps |
| CPU time | 41.5 seconds |
| Started | Aug 27 03:14:52 PM UTC 24 |
| Finished | Aug 27 03:15:35 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897192658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1897192658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.2368013616 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 258251516 ps |
| CPU time | 9.6 seconds |
| Started | Aug 27 03:14:54 PM UTC 24 |
| Finished | Aug 27 03:15:05 PM UTC 24 |
| Peak memory | 266996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368013616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2368013616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.2326461106 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 61827447 ps |
| CPU time | 12.87 seconds |
| Started | Aug 27 03:14:59 PM UTC 24 |
| Finished | Aug 27 03:15:14 PM UTC 24 |
| Peak memory | 267000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326461106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2326461106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.4011246413 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 765276930 ps |
| CPU time | 59.9 seconds |
| Started | Aug 27 03:14:52 PM UTC 24 |
| Finished | Aug 27 03:15:53 PM UTC 24 |
| Peak memory | 269376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011246413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.4011246413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.3457957935 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 542635505394 ps |
| CPU time | 2980.36 seconds |
| Started | Aug 27 03:15:38 PM UTC 24 |
| Finished | Aug 27 04:05:51 PM UTC 24 |
| Peak memory | 304600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457957935 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.3457957935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all_with_rand_reset.2894325203 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 66902228003 ps |
| CPU time | 295.3 seconds |
| Started | Aug 27 03:15:50 PM UTC 24 |
| Finished | Aug 27 03:20:50 PM UTC 24 |
| Peak memory | 281528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2894325203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.al ert_handler_stress_all_with_rand_reset.2894325203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |